//**************************************************************************************
//D0CS09.TST
//By B. Rosen and M. Thomson  							February 21, 1979
//Sub Test Program for D0 CS Module
//**************************************************************************************
get "d0cs.d"

//Edge pin and test connector signal busses available to this sub-test:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{CS-A': TrmCS-A.00'a,TrmCS-A.01'a,TrmCS-A.02'a,  TrmCS-A.03'a,TrmCS-A.04'a,TrmCS-A.05'a,  TrmCS-A.06'a,TrmCS-A.07'a,TrmCS-A.08'a,  TrmCS-A.09'a,TrmCS-A.10'a,CS-A.11'}

//{H2: H2.12,  H2.13,H2.14,H2.15}

//{R: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Test 14: Test Almost all of Control Store Ram

let Test14() be
[
	SpeakTest(14) //set initial conditions (see notes at end of D0CS.TST)

	let v = vec 64
	let str = v

//This test is similar to test 13, except the data stored and retrieved is the
//	complement of that used in Test 13.

	TwoClocks()	//Load Page 2 @1411
	TwoClocks()	//goto page 2 @1425

	Ws("*nWriting Page")
	RxCSData()
	let d = #123456 //start random data

	for l = 0 to 15 do //16 pages
	[
		Ws(FORMATN(" <B>",l))
		FORMAT(str,"in dual address complement test write of Page <B>",l)

		for k = (l gr 3? 0,1) to 3 do //64 word quarter pages, don't do first quarter
		[
			let lk = (l lshift 8) % (k lshift 6)  //form address bits [4:9]

			for j = 0 to 1 do //first two passes have extra Checks
			[
				let i = lk % j		//form address
				d = (d<<w.b1 xor d<<w.b4) % (d lshift 1); //up-date random data
				let e = not d

				{ALUA} = e;		//Data to be loaded
				{H2} = e;		//extra 4 bit data
				TwoClocks()		//CSIn_ @1022

				{ALUA} = i;		//Address to load
				TwoClocks()		//APC_ @1003
				Check("Cycle0Feed'",{Cycle0Feed'},0,"before write",14000,i)

				EClock()		//WriteCS @1004
				Check("CS-A'",{CS-A'} xor #7777,i,"middle of write",14001,i)

				{LoadAPC'xxx} = {LoadAPC'}
				TwoEClocks()
				Check("CS-A'",{CS-A'} xor #7777,#1005,"middle of fetch",14002,i)

				{LoadAPC'xxx} = {LoadAPC'}
				EClock()

				{H2.15} = 0;		//CSData[0:15] _ bits[0:15]
				FourClocks()		//APC_ @1005; ReadCS @1006
				Check("Msb Read Data",{R},e,str,14100,i)

				{ALUA} = e;		//Data to be loaded
				TwoClocks()		//Read Fetch

				{ALUA} = i;		//Address to load
				FourClocks()		//APC_ @1007; WriteCS1 @1010
				TwoClocks()		//Write Fetch

				//there is a branch instruction at the end of the loop
				{J-TestResult'} = (i eq 4095?0,1)
				TwoClocks()		//Branch Loop @1011
			]

			for j = 2 to 63 do //remaining passes omit extra Checks for speed
			[
				let i = lk % j		//form address
				d = (d<<w.b1 xor d<<w.b4) % (d lshift 1); //up-date random data
				let e = not d

				{ALUA} = e;		//Data to be loaded
				{H2} = e;		//extra 4 bit data
				TwoClocks()		//CSIn_ @1022

				{ALUA} = i;		//Address to load
				TwoClocks()		//APC_ @1003
				FourClocks()		//insert note here ******

				{H2.15} = 0;		//CSData[0:15] _ bits[0:15]
				FourClocks()		//APC_ @1005; ReadCS @1006
				Check("Msb Read Data",{R},e,str,14200,i)

				{ALUA} = e;		//Data to be loaded
				TwoClocks()		//Read Fetch

				{ALUA} = i;		//Address to load
				FourClocks()		//APC_ @1007; WriteCS1 @1010
				TwoClocks()		//Write Fetch

				//there is a branch instruction at the end of the loop
				{J-TestResult'} = (i eq 4095?0,1)
				TwoClocks()		//Branch Loop @1011
			]
		]
	]

	EClock()		//Burp
	{J-TestResult'} = 1
	TwoClocks()		// Noop @1023
	Check("CS-A",(not {CS-A'})&#7777,#1013,"between write and read",14300)

	Ws("*nReading Page")
	let d = #123456 //start random data

	for l = 0 to 15 do //16 pages
	[
		Ws(FORMATN(" <B>",l))
		FORMAT(str,"in dual address complement test read of Page <B>",l)

		for k = (l gr 3? 0,1) to 3 do //64 word quarter pages, don't do first quarter
		[
			let lk = (l lshift 8) % (k lshift 6)  //form address bits [4:9]

			for j = 0 to 63 do
			[
				let i = lk % j		//form address
				d = (d<<w.b1 xor d<<w.b4) % (d lshift 1); //up-date random data
				let e = not d

				{ALUA} = i;		//Address to read
				{H2.15} = 0;		//CSData[0:15] _ bits[0:15]
				FourClocks()		//APC_; ReadCS0
				Check("Msb Read Data",{R},e,str,14400,i)

				TwoClocks()		//Read Fetch
				{H2.15} = 1;		//CSData _ LCSD[0:3],,bits[20:31]
				{H2.14} = 0;		//LCSD[0:3] _ bits[16:19]
				FourClocks()		//APC_; ReadCS1
				Check("Middle Read Data",{R},e,str,14401,i)

				TwoClocks()		//Read Fetch
				{H2.14} = 1;		//LCSD[0:3] _ bits[32:35]
				FourClocks()		//APC_; ReadCS2
				Check("Xtra Read Data",{R}&#170000,e lshift 12,str,14402,i)

				TwoClocks()		//Read Fetch
				{J-TestResult'} = (i eq 4095?0,1)
				TwoClocks()		//Branch Loop
			]
		]
	]

	EClock() //Burp
]