//**************************************************************************************
//D0CS03.TST
//By B. Rosen and M. Thomson  							February 7, 1979
//Sub Test Program for D0 CS Module
//**************************************************************************************
get "d0cs.d"

//Edge pin and test connector signal busses available to this sub-test:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{ALUF: ALUF.0,  ALUF.1,ALUF.2,ALUF.3}

//{BSEL: BSEL.0,BSEL.1}

//{CS-A': TrmCS-A.00'a,TrmCS-A.01'a,TrmCS-A.02'a,  TrmCS-A.03'a,TrmCS-A.04'a,TrmCS-A.05'a,  TrmCS-A.06'a,TrmCS-A.07'a,TrmCS-A.08'a,  TrmCS-A.09'a,TrmCS-A.10'a,CS-A.11'}

//{CTask: CTask.0,  CTask.1,CTask.2,CTask.3}

//{F1: F1.0,  F1.1,F1.2,F1.3}

//{F2: F2.0,  F2.1,F2.2,F2.3}

//{H2: H2.12,  H2.13,H2.14,H2.15}

//{JA: JA.0,JA.1,  JA.2,JA.3,JA.4,  JA.5,JA.6,JA.7}

//{JC: JC.0,JC.1,JC.2}

//{R: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{RSEL/d: RSEL.0/d',RSEL.1/d',RSEL.2/d,  RSEL.3/d,RSEL.4/d,RSEL.5/d}

//**************************************************************************************
//Test 3: Test of Control Store

let Test3() be
[
	SpeakTest(3) //set initial conditions (see notes at end of D0CS.TST)

	let sb = 0
	let v = vec 64
	let str = v
	let st = vec 64

	RxCIA()

//Initial starting position is just after boot.
//The first 16 instructions have count patterns in most fields.

	for i = 0 to 15 do
	[
		FORMAT(st,"instruction number = <B>",i)

//If this is not correct, JC, JA or the CS-A multiplexors aren't right
		Check("CS-A",((not {CS-A'})&#7777),i,st,3000)
		//Check("CS-A",((not {CS-A'})&#7777),0,st,3000)//test case only
//WaitForKey("just AFTER  Check CS-A ")
		EClock() //get into the middle of the fetch
		Check("RUN",{RUN},1,st,3001) //RUN should go high after first clock

//If these are not right, usually the data was not written correctly,
//but it can also be a bad ram chip (or the S240/241 driver)
		Check("MemInst/d",{MemInst/d},i&1,st,3002)
		Check("MemInst/d'",{MemInst/d'},(not i)&1,st,3003)
		Check("RMOD/d",{RMOD/d},i&1,st,3004)
		Check("RMOD/d'",{RMOD/d'},(not i)&1,st,3005)
		Check("RSEL/d",{RSEL/d},((i lshift 2)+3) xor #60,st,3006)
		Check("RSEL4and5/d",{RSEL4and5/d},1,3007)

		Check("LoadMIR",{LoadMIR},1,"in cycle 1",3008)

//After the clock, wrong data can be bad write data, bad CS chip or bad MIR register.
WaitForKey("just before 1st LoadMIR")
		EClock()
WaitForKey("just after 1st LoadMIR")
		Check("ALUF",{ALUF},i,st,3009)
		Check("BSEL",{BSEL},i&3,st,3010)

//F1 is always 0 in this sequence
		Check("F1",{F1},0,st,3011)
		Check("LR",{LR},i&1,st,3012)
		Check("LT",{LT},i&1,st,3013)
		Check("F2",{F2},i,st,3014)

//JC sb 4 always
		Check("JC",{JC},GoTo,st,3015)

//JA points to next address (=i+1)
		Check("JA",{JA},i+1,st,3016)
		Check("CIA",(not {R})&#7777,i,"via R bus",3017)

		FORMAT(str,"with i=<B> via R bus",i)

//See page 10 for the gate that computes F1ok
		sb = (i&3) eq 2? 1,0
		Check("F1ok",{F1ok},sb,st,3018)

//Check F2ok
		sb = (i&3) eq 2? (i&#14 eq 4?0,1),0
		Check("F2ok",{F2ok},sb,st,3019)

//F1 is forced 0, EnabGrp A/B cannot occur
		Check("EnabGrpA/B",{EnabGrpA/B},0,"always in initial execution",3020)
	]
] 

//**************************************************************************************
//Test 4: Test Branch & Load APC

and Test4() be
[
	SpeakTest(4) //set initial conditions (see notes at end of D0CS.TST)

	let sb = 0
	let v = vec 64
	let str = v
	let st = vec 64

//The next 16 instructions check branching and loading of APC

	for i = 0 to 15 do
	[
		let bdir  = i&1
		let nbdir = bdir xor 1

		FORMAT(st,"Branch & Load APC Test: instruction number = <B>",i+16)

//load 1 bit of APC with a 1, all others 0
//APC loads from ALUA
		{ALUA} = 1 lshift i

//branch direction: 1 for odd cycles, 0 for even (causes sequential addresses)
		{J-TestResult'} = nbdir
		EClock()	//Branch Burp test

//WaitForKey("just b4 branchburp clock")
//if we are branching, we should need an extra clock, see pages 10 & 12.

//Verify that branch burp holds up EdgeClock

		if bdir then
 
		for j = 0 to 3 do
		[
			ExtClock()
			Check("EdgeClockFeed'",{EdgeClockFeed'},1,"in BranchBurp",4000,j)
		]

//Verify that branch burp holds off cycle advance
		Check("Cycle0Feed'",{Cycle0Feed'},1,"in Branch Burp test",4001)

//WaitForKey("just before cycle1 clock")
//Verify that low order address bit followed J-TestResult
		Check("CS-A.11'",{CS-A.11'},nbdir,st,4002)

//We specifed LoadAPC in the instruction (BSEL=2,F1=7,F2=0)
		Check("LoadAPC'",{LoadAPC'},0,st,4003)

//We get to control the actual load anyway
		{LoadAPC'xxx} = 0
		EClock() //t2

//We should always be back in cycle 0 at this point
		Check("Cycle0Feed'",{Cycle0Feed'},0,"in Branch Burp test",4004)

//and CIA.11 should follow J-TestResult
		Check("CS-A.11'",{CS-A.11'},1,st,4005)

//Turn off load APC
		{LoadAPC'xxx} = 1

//We should always end up at the next sequential address
		RxCIA()
		Check("CIA",(not {R})&#7777,i+16,st,4006)

//Check that all the conditions to cause LoadAPC happened
		Check("F1",{F1},7,st,4007)
		Check("F2",{F2},#10,st,4008)
		Check("F1ok",{F1ok},1,st,4009)
		Check("EnabGrpA/B",{EnabGrpA/B},1,st,4010)

//We use this to check that the other 2 bits of JC work
		Check("JC",{JC},Branch+(i&3),st,4011)
		Check("JA",{JA},i+17,st,4012)

//Did APC get loaded correctly?

		if i>0 then 
		[
			RxAPC()
			Check("APC",{R},1 lshift i,st,4013)

		]
	]

//a last effort check to see that we escape the clutches of branch burp
	Check("Cycle0Feed'",{Cycle0Feed'},0,"after branch test",4014)
]