//**************************************************************************************
//D0CS.TST
//By B. Rosen and M. Thomson  							February 21, 1979
//Main Test Program for UTFP Controller Module
//**************************************************************************************

//NOTE: This test is for rev. I boards (see below for prom revisions)

//Change History:
//	!4  2/22/79: Up-dated d0cs.tst; improved d0cs08.tst and d0cs09.tst.
//	!3  2/16/79: Dump-file reorganization only (moved .cm's to .dmtests).
//	!2  2/09/79: Edited !1 to conform to present format; corrected Test 2 error.
//	!1  1/??/79: Slightly revised [ivy]<thacker>d0cs-I.dmtest of 11/27/78.

//**************************************************************************************

//CURRENT PROM REVISION (for 8G systems):
//	Rev. F thru B: d4(u107) (HM7603 on page 11)
//	Rev. F: c12(u117) and g12(u118) (i2716 EPROMS on page 11)

//CURRENT PROM REVISION (for systems earlier than 8G):
//	Rev. E thru B: d4(u107) (HM7603 on page 11)
//	Rev. E: c12(u117) and g12(u118) (i2716 EPROMS on page 11)

//This test can be used with either prom configuration since the EPROMS are unplugged.

//**************************************************************************************

//DUMP FILES in ifs-2 under <Thomson>:

//D0CS-I.DMTESTS contains
//	d0cs*.tst, d0cs.d, d0cs.bp, d0cs.run, d0cs*.cm, d0csall.cm1, d0csall.cm2

//The next two dump files permit modification of the tests

//D0CSTESTAUX-I.DM contains
//	d0cs*.br, d0cs*.bt, d0cs.bs, d0cs.syms, readd0mb.br

//TEST.DM contains
//	BCPL.RUN, BLDR.RUN, TC.RUN, format.br, testfns,br, SYS.BK, STREAMS.D
//	(tester.d and testdefs.d are not used; d0cs.d contains their information)

//**************************************************************************************

//INSTALL THE FOLLOWING TEST CLIPS:

//Remove EPROMS from locations c12(u117) and g12(u118)

//Connect Prom Simulator cables:
//	Tester socket "E8" to location c12(u117)
//	Tester socket "E6" to location g12(u118)

//Tester socket "B" to location b11(u24) - page 5  (20-pin clip on 18-pin component)
//	TrmCS-A.00'a: b11.1,1
//	TrmCS-A.01'a: b11.2,2
//	TrmCS-A.02'a: b11.3,3
//	TrmCS-A.03'a: b11.4,4
//	TrmCS-A.04'a: b11.5,5
//	TrmCS-A.05'a: b11.6,6
//	TrmCS-A.06'a: b11.17,16
//	TrmCS-A.07'a: b11.16,15
//	TrmCS-A.08'a: b11.15,14
//	TrmCS-A.09'a: b11.14,13
//	TrmCS-A.10'a: b11.13,12
//	TrmCS-A.11'a: b11.12,11

//Tester socket "C" to location e13(u67) - page 13 (16-pin clip on 14-pin component)
//	JA.0: e13.4,4
//	JA.1: e13.2,2
//	JA.2: e13.13,15
//	JA.3: e13.12,14
//	JA.4: e13.11,13
//	JA.5: e13.10,12
//	JA.6: e13.9,11
//     (JA.7 is available on edge-pin E048)

//Clip pre-fabricated test connector to location b1(u123)
//	This applies a resistor network to the ExtClock signal (page 12)

//**************************************************************************************
get "D0cs.d"
get "streams.d"

external //O.S.
[
	Puts
	Closes
	OpenFile
	AnnounceFirstWrite
]

static
[
	pass = 0
	otime = 0
	exectime = 0
	looping = false
	AnnounceFirstWrite = false
]

//**************************************************************************************
//Edge pin and test connector signal busses available to this sub-test:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{Clock: ExtClock,  ExtClock,ExtClock,ExtClock,  ExtClock,ExtClock,ExtClock,  ExtClock,ExtClock,ExtClock,  ExtClock,ExtClock,ExtClock,  ExtClock,ExtClock,ExtClock}

//{CS-A': TrmCS-A.00'a,TrmCS-A.01'a,TrmCS-A.02'a,  TrmCS-A.03'a,TrmCS-A.04'a,TrmCS-A.05'a,  TrmCS-A.06'a,TrmCS-A.07'a,TrmCS-A.08'a,  TrmCS-A.09'a,TrmCS-A.10'a,CS-A.11'}

//{JA: JA.0,JA.1,  JA.2,JA.3,JA.4,  JA.5,JA.6,JA.7}

//{JC: JC.0,JC.1,JC.2}

//{R: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Main program for D0CS module test

let main() be
[
	Ws("*nControl Board Test, board level: Rev I")
	Ws("*n*nShall I wait before I write the Control store the first time? Y or N:")

	LoadBootROM()
	while Endofs(keys) do [ ]
	let char = Gets(keys)
	if (char eq $y) % (char eq $Y) then AnnounceFirstWrite = true
	[
		pass = pass + 1

		Test1()
		Test2()
		Test3()
		Test4()
		Test5()
		Test6()
		Test7()
		Test8()
		Test9()
		Test10()
		Test11()
		Test12()
		Test13()
		Test14()
	] repeat
]

//**************************************************************************************
//Routines available for D0CS module tests:

and normalize() be
//bring clock gen to first click of cycle0
[
	while ({EdgeClockFeed'} eq 1) % ({Cycle0Feed'} eq 0) do ExtClock()
	ExtClock()
	if {EdgeClockFeed'} ne 1 then ExtClock()
	if {RamClockFeed'} ne 1 then Ws("*nSomehow, normalize isn't working")
]

and WaitForKey(msg) be
[
	Ws(msg)
	Ws("   Waiting...")
	while Endofs(keys) do [ ]
	Gets(keys)
	Ws("*nRunning...")
]

and WCompare(was,sb,testno,drive; numargs na) be
//Wait-Comparison routine
[
	if was eq sb then return

	Ws(FORMATN("*nTest <D>: Was = <B>, Should be = <B>",testno,was,sb))
	if na gr 3 then Ws(FORMATN(", drive = <B>",drive))

	while Endofs(keys) do [  ]
	Gets(keys)
	Ws("*nRunning...")
]

and Check(ini,was,sb,fin,testno,drive; numargs na) be
//verify that "was" = "sb", complain if not, allow single step
[
	if was eq sb then return

	Ws(FORMATN("*nTest <D>: <S> was=<B>, should be=<B> <S>",testno,ini,was,sb,fin))
	if na gr 5 then Ws(FORMATN(", drive=<B>",drive))

	let csa = (not {CS-A'}) & #7777
	let ja = {JA}
	let jc = {JC}

	Ws(FORMATN("*n  CS-A=<B>, JA=<B>, JC=<B>",
		csa,ja,jc))

	if {Cycle0Feed'} eq 0 do //can't read from R bus mux's during Cycle1
	[
		let oc2 = {RSEL.2/bxxx}
		let oc3 = {RSEL.3/bxxx}

		RxCIA()
		let cia = {R} xor #7777

		RxAPC()
		let apc = {R}

		RxCSData()
		let csd = {R}

		Ws(FORMATN(", CIA/CTsk=<B>, APC/APCTsk=<B>, CSData=<B>",
		cia,apc,csd))

		{RSEL.2/bxxx} = oc2
		{RSEL.3/bxxx} = oc3
	]

	[
		while Endofs(keys) do [   ]
		let char = Gets(keys)
		switchon char into
		[
		case $c: case $C: EClock();endcase
		case $t: case $T: ExtClock();endcase
		case $q: case $Q: finish
		case $*s: [ Ws("..Running");return ]
		case $h: case $H:

			let s = OpenFile("csHelp.msg",ksTypeReadOnly,charItem)
			if s eq 0 then [ Ws("*n can't open csHelp.msg");endcase ]
			[
				let c = Gets(s)
				if c eq $! then
				[
					let n = GetNum(s)

					if n eq testno then
					[
						until c eq $! do [ c = Gets(s); Puts(s,c) ]
						Closes(s)
						endcase
					]
				]
			] repeatuntil Endofs(s)

			Ws("*n I'm sorry, I can't help you with this one")
			endcase
		]
	] repeat
]

and GetNum(s) = valof
//This procedure supports the "Check(...)" procedure (directly above)
[
	let n = 0
	let char = 0
	[
		if Endofs(s) then resultis -1
		char = Gets(s)
		if (char ls $0) % (char gr $9) then resultis n
		n = (n*10) + char - $0
	] repeat
]

//**************************************************************************************
//Clocking routines defined on pages 2 and 12:

and ExtClock() be
[
//"External Clock" (input to module - page 12)
	{ExtClock} = 1
	{ExtClock} = 0
]

and EClock() be
//"Edge Clock" - consists of 4 ExtClocks
[
	{Clock} = #125
]

and TwoEClocks() be
//"Two Edge Clocks" - consists of 8 ExtClocks
[
	{Clock} = #52525
]

and TwoClocks() be
//"Special Two Edge Clocks" - consists of 8 ExtClocks with LoadAPC'xxx up-date
[
	{Clock} = #125
	{LoadAPC'xxx} = {LoadAPC'}
	{Clock} = #125
]

and FourClocks() be
//"Special Four Edge Clocks" - consists of 16 ExtClocks with LoadAPC'xxx up-date
//(i.e., this is a pair of TwoClocks() (above) for improved speed)
[
	{Clock} = #125
	{LoadAPC'xxx} = {LoadAPC'}
	{Clock} = #52525
	{LoadAPC'xxx} = {LoadAPC'}
	{Clock} = #125
]

//**************************************************************************************
//R bus display control (page 3)

and RxAPC() be
//R[0:3] _ APCTask[0:3],  R[4:15] _ APC[0:11]
[
	{RSEL.2/bxxx} = 0
	{RSEL.3/bxxx} = 0
]

and RxCIA() be
//R[0:3] _ InCTsk[0:3],  R[4:15] _ CIA[0:11]'
[
	{RSEL.2/bxxx} = 0
	{RSEL.3/bxxx} = 1
]

and RxCSData() be
//R[0:15] _ CS-Data[0:15]
[
	{RSEL.2/bxxx} = 1
	{RSEL.3/bxxx} = 0
]

and RxPage() be
//R[0:3] _ Page[0:3],  R.04 _ gnd
//R[5:7] _ CS-ParErr,,R-ParErr,,MemErr
//R[8:9] _ gnd,  R[10:15] _ RFB[0:5]
[
	{RSEL.2/bxxx} = 1
	{RSEL.3/bxxx} = 1
]

//**************************************************************************************
and SpeakTest(testno) be
[

//Calculate the execution time for each test
	let tv = vec 2
	Timer(tv)
	exectime = tv!1 - otime
	otime = tv!1
	Ws(FORMATN("*nExection Time for this test is <D> msec.",exectime))

//Set up the title display
	Ws("*n")
	Ws("*n")
	Ws(FORMATN("*nD0CS TEST (rev. I): Pass <D>, Test <D>...",pass,testno))
	
//Set up misc. initial conditions:

	{R} = ###
	{ALUA} = 0

//{D0CSbus1: BBDisp.0,BBDisp.1,BBDisp.2,  EnCtrlAuxRa,EnCtrlAuxRb,H2.12,  H2.13,H2.14,H2.15,  WakeP1',WakeP2',WakeP3'}
	{D0CSbus1} = #600

//{D0CSbus2: ExtClockEnab',InstReadingR,  MemSetFault,NextInstOpTrp,PCF.0,  RSEL-Parity,StackEmpty,Suspend-a}
	{D0CSbus2} = 0

//{D0CSbus3: Abort',  BBFA',BootOkxxx,BranchShift',  CPar'xxx,J-TestResult',LoadAPC'xxx,  NextInst',Overflow',PnlBoot',  PwrBoot',RParityError',ShortFldDisp',  StackBadNow',TesterBoot',UseTPC'xxx}
	{D0CSbus3} = #177777

	{D0cs12.sil+3} = 1; //delay line input for RamClockFeed' (page 12)
]
(635)\2925f1 1f0