//**************************************************************************************
//ALU6.TST
//By F. Itami and M. Thomson  							January 23, 1979
//Sub Test Program for D0 ALU Module
//**************************************************************************************
get "alu.d"

//Edge pin signal busses used by ALU module:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{aluf: ALUF.0,  ALUF.1,ALUF.2,ALUF.3}

//{clkbus: LT,LR,  Abort',LoadMIR,Cycle0Feed'}

//{CTask: CTask.0,  CTask.1,CTask.2,CTask.3}

//{F1F2: F1.0,F1.1,  F1.2,F1.3,F2.0,  F2.1,F2.2,F2.3}

//{H2: H2.08,H2.09,  H2.10,H2.11,H2.12,  H2.13,H2.14,H2.15}

//{MASK: MASK.00,  MASK.01,MASK.02,MASK.03,  MASK.04,MASK.05,MASK.06,  MASK.07,MASK.08,MASK.09,  MASK.10,MASK.11,MASK.12,  MASK.13,MASK.14,MASK.15}

//{MC1SA: BSEL.0,BSEL.1,  F1.0,F1.1,F1.2,  F1.3,LR,LT}

//{mcbus: MC1WriteR,  MC2AllowWrite,MC1NeedsR,MC2WillGetR}

//{mirbus: MemInst/d,MemInst/d',  RMOD/d,RMOD/d',RSEL.0/d',  RSEL.1/d',RSEL.2/d,RSEL.3/d,  RSEL.4/d,RSEL4and5/d,RSEL.5/d}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{TA: TA.0,  TA.1,TA.2,TA.3}

//**************************************************************************************
//Test 17: Check the R file addressing logic (pages 13,14)
//         Check the MC1Ad_Stkp logic (pages 11,20)
//         Check that MC2XferWord=0 blocks RSA.1_1 and RSB.2_1 when MC2WillGetR=1 (page 13)

let Test17() be
[
	SpeakTest(17) //set initial conditions (see notes at end of ALU.TST)

//Write all R locations with their own addresses as data

	 SetPinValue(21,1); //for prom f2 address = xxxx x1x0 and output = 1111 (page 16)
	            //to keep MC1XferWord=1, and MC2XferWord=1 for Suspend control
	 SetPinValue(10,1); //keep Stkp=0
	 SetPinValue(136,1); //enable b13 prom (page 11) for MC1Ad_Stkp+0 when SRC/DEST=0 (i.e. when i=0)
	 SetBusValue(4,79,27,78,80,#12); //write into R (address from MC1Ad)
	ClockMIR() //MemInst_1, Suspend_1, RSA,B_4,6

	for i = 0 to 255 do 
	[
		 SetBusValue(8,95,31,224,160,223,159,225,161,i)
		 SetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23,i)
		ClockAd() //MC1Ad_i
		RClock()
		EClock()  //clear EnMapRow (avoid StorA bus conflict)
	]

	 SetBusOpen(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23)
	 SetPinValue(79,0)

//Test MC1Ad (RSA,B=4,6) and MC2Ad (RSA,B=6,7) inputs to RA's

	//Stkp, RASAVE, and WA remain = 0 since Suspend = 1

	 SetBusValue(8,95,31,224,160,223,159,225,161,0)
	ClockAd()  //MC1Ad_0's
	ClockMC2() //MC2Ad_(MC1Ad=0)

	for i = 0 to 8 do
	[
		let a = #200 rshift i
		let b = #400 rshift i
		 SetBusValue(8,95,31,224,160,223,159,225,161,a)

		ClockAd() //RSA,B_4,6(MC1Ad), MC1Ad_a
		WCompare(GetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23),a,17000+i) //rbus=RA=MC1Ad

		 SetPinValue(80,1)
		EClock() //RSA,B_6,7(MC2Ad)
		         //MC1Ad[4:7] increments since MC1HasR=1
		WCompare(GetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23),b&#377,17020+i) //rbus=RA=MC2Ad

		 SetPinValue(80,0)
		ClockAd() //restore MC1Ad=a
		ClockMC2() //MC2Ad_(MC1Ad=a)
		//the sequence above assures MC1Ad not = MC2Ad when tested
	]

//Test Stkp (RSA,B=3,3) and WA (RSA,B=2,5) inputs to RA's

	//MC1Ad=MC2Ad=Stkp=RASAVE=WA=0 from previous steps

	 SetBusValue(4,79,27,78,80,0); //initialize memory control
	EClock() //reset Suspend

	for i = 0 to 8 do
	[
		let a = #1200 rshift i
		let b = #2400 rshift i

		 SetBusValue(11,136,200,137,201,132,196,133,197,134,135,198,#1537); //MemInst=0, RMOD=1, RSEL=01 11 11
		 SetPinValue(10,1)
		ClockMIR() //RSA,B_3,3(Stkp), open rbus, don't Stkp_ALUA
		 SetPinValue(10,0)

		 SetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23,a)
		EClock() //H1_(rbus=a), RASAVE_(RA=Stkp)
		 SetBusOpen(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23)

		 SetBusValue(11,136,200,137,201,132,196,133,197,134,135,198,#1407); //MemInst=0, RMOD=1, RSEL=11 00 11
		ClockMIR() //RSA,B_3,3(Stkp), rbus_R, Stkp_(ALUA=a),
		           //WA_(RASAVE = prior Stkp)
		WCompare(GetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23),a&#377,17040+i) //rbus=RA=Stkp

		EClock() //RSA,B_2,5(WA)
		WCompare(GetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23),b&#377,17060+i) //rbus=RA=WA
	]

	 SetPinValue(10,1); //keep Stkp=2 for later in test

//Test RSA,B=0,0 (when i = 2,3) and RSA,B=1,0 (when i not = 2,3)

	//{racon1: CTask.0,CTask.1,  RSEL.0/d',RSEL.1/d',RSEL.2/d,  RSEL.3/d,PCF.1,PCF.2}

	 SetBusValue(11,136,200,137,201,132,196,133,197,134,135,198,#1540); //MemInst=0, RMOD=1, RSEL=00 00 00

	for i = 0 to 8 do
	[
		let a = #200 rshift i
		 SetBusValue(8,29,93,132,196,133,197,213,214,a xor #60)
		ClockMIR() //RSEL[0:3]_RSEL[0:3]/d, RSA_0 or 1, RSB_1, rbus_R
		WCompare(GetBusValue(16,233,169,232,168,211,147,207,143,104,40,103,39,89,25,87,23),a,17080+i) //rbus=RA={racon1}
	]

//Test RSA,B=1,1

	//{racon2: FOR POSITIVE SCOPE SYNC. and OBSERVE Cycle0Feed', Cycle0, clkCycle0'a.  THE INTERFERENCE SHOULD BE SEEN DURING ClockMC2 WHEN H2.12 (and others) GETS ILLEGALLY RESET BY A clkCycle0'a THAT SHOULDN'T EXIST.

		ClockAd()  //MC1Ad[0:3]_i, Stkp[0:3]_i
		ClockMC2() //MC2Ad[0:3]_i, TROUBLE IS HERE WHEN i=8

		{MASK}=0; //TO LOOK AT ALL OF H1 on ALUA

		//PUT "//" IN FRONT OF WCompare FOR SCOPING **********
		WCompare(GetBusValue(16,229,165,228,164,212,148,204,140,102,38,101,37,83,19,82,18),-1,16800+i) //if not -1, contains contents of R file (address from Stkp = i lshift 4). (H1

//UNKNOWN SIGNALS REQUIRED:
//TEST CLIP ? ->  (FORPOSITIVESCOPESYNC.andOBSERVECycle0Feed')
//TEST CLIP ? ->  (Cycle0)
//TEST CLIP ? ->  (Stkp[0:3]_i
ClockMC2()//MC2Ad[0:3]_i)
//TEST CLIP ? ->  (clkCycle0'a.THEINTERFERENCESHOULDBESEENDURINGClockMC2WHENH2.12(andothers)GETSILLEGALLYRESETBYAclkCycle0'aTHATSHOULDN'TEXIST.

ClockAd()//MC1Ad[0:3]_i)
//TEST CLIP ? ->  (TROUBLEISHEREWHENi=8

{MASK)