//**************************************************************************************
//ALU2.TST
//By F. Itami and M. Thomson  							January 23, 1979
//Sub Test Program for D0 ALU Module
//**************************************************************************************
get "alu.d"

//Edge pin signal busses used by ALU module:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{aluf: ALUF.0,  ALUF.1,ALUF.2,ALUF.3}

//{clkbus: LT,LR,  Abort',LoadMIR,Cycle0Feed'}

//{CTask: CTask.0,  CTask.1,CTask.2,CTask.3}

//{F1F2: F1.0,F1.1,  F1.2,F1.3,F2.0,  F2.1,F2.2,F2.3}

//{H2: H2.08,H2.09,  H2.10,H2.11,H2.12,  H2.13,H2.14,H2.15}

//{MASK: MASK.00,  MASK.01,MASK.02,MASK.03,  MASK.04,MASK.05,MASK.06,  MASK.07,MASK.08,MASK.09,  MASK.10,MASK.11,MASK.12,  MASK.13,MASK.14,MASK.15}

//{MC1SA: BSEL.0,BSEL.1,  F1.0,F1.1,F1.2,  F1.3,LR,LT}

//{mcbus: MC1WriteR,  MC2AllowWrite,MC1NeedsR,MC2WillGetR}

//{mirbus: MemInst/d,MemInst/d',  RMOD/d,RMOD/d',RSEL.0/d',  RSEL.1/d',RSEL.2/d,RSEL.3/d,  RSEL.4/d,RSEL4and5/d,RSEL.5/d}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{TA: TA.0,  TA.1,TA.2,TA.3}

//**************************************************************************************
//Test 5: Test the ALUA input to the ALU (using ALUOUT = "R")
//        Check R_H3P_ALUOUT_ALUA.IN_ALUA_MASKER_CYCLER_H1_R

let Test5() be
[
	SpeakTest(5) //set initial conditions (see notes at end of ALU.TST)

	//{CYCOUNT:  CYCOUNT.0,   CYCOUNT.1, CYCOUNT.2, CYCOUNT.3 }
	//{NCYCOUNT: CYCOUNT.0',  CYCOUNT.1',CYCOUNT.2',CYCOUNT.3'}

	//SpeakTest set up: {aluf}=1 ("R"), TComing=1 (for clkH3P'), Cycle0=1

//PART 1: Test H1_R and the CYCLER (MASK=0 for pass all CYCLER bits to ALUA)

	for i = 0 to 15 do
	[
		let drive = 1 lshift i
		{rbus}=drive
		EClock() //H1_(rbus=drive)

		for j = 0 to 15 do
		[
			{CYCOUNT}=j; //left-cycle H1 output j bit positions
			{NCYCOUNT}= not j
			WCompare({ALUA},LCyc(drive,j),5000+j,drive)
		]
	]

//PART 2: Test the MASKER and R_H3P_ALUOUT_ALUA.IN_ALUA

	for i = 0 to 15 do
	[
		let drive = 1 lshift i

		{Cycle0Feed'}=0
		{rbus}=#177777
		EClock() //H1_(rbus=#177777)

		{MASK} = not drive; //will pass only one H1 bit in "drive" position
		WCompare({ALUA},drive,5100+i) //check MASKER function

		EClock() //H3P_(ALUOUT=ALUA.IN=ALUA = (H1=#177777)&(MASK'=drive))
		{rbus}=###; //open rbus

		{Cycle0Feed'}=1; //rbus_(H3P=#177777&drive)
		WCompare({rbus},drive,5200+i) //check ALUOUT = "R" function
	]
]

//**************************************************************************************
//Test 6: Test the ALUB input to the ALU (Bmux and MASK inputs)
//        Check R_H3P_ALUOUT_(ALUB = (H2=Bmux) or the MASK) (uses ALUOUT = "T" code)
//        Check that J-TestResult'=H2.08 when the h19 mux address=3 (page 10)
 
and Test6() be
[
	SpeakTest(6) //set initial conditions (see notes at end of ALU.TST)

	{aluf}=0; //ALUOUT_ALUB ("T" code)
	{Cycle0Feed'}=1; //display H3P
	{JC.1}=0; {JC.2}=1; {JA.7}=1; //select H2.08' as J-TestResult' mux input

//PART 1: Check ALUB_H2_Bmux (EnableMask=0)

	for i = 0 to 255 do
	[
		{F1F2}=i
		{BSEL.1}=1; //up align F1F2
		ClockCycle0() //H2[0:7]_i, ALUF()_"ALUB"

		{BSEL.1}=0; //down-align F1F2
		ClockCycle0() //H3P_(ALUOUT=H2=i lshift 8), H2[8:15]_i
		WCompare({rbus},i lshift 8,6000,i) //F1,F2,0,0

		WCompare({H2},i,6001,i) //0,0,F1,F2
		WCompare({J-TestResult'},i rshift 7,6002,i) //J-TestResult'=H2.08=i[8] (rev. M)

		ClockCycle0() //H3P_(ALUOUT=H2=i)
		WCompare({rbus},i,6003,i) //0,0,F1,F2
	]

//PART 2: Check ALUB_MASK (EnableMask=1)

	{BBFA'}=0; //for EnableMask_1 (MA'=0 from SpeakTest)
	ClockCycle0() //EnableMask_1 (page 6)

	for i = 0 to 15 do
	[
		let a = 1 lshift i
		{MASK}=a
		ClockCycle0() //H3P_(ALUOUT=MASK=a)
		WCompare({rbus},a,6100+i)
	]
]

//**************************************************************************************
//Test 7: Test the T file write-read functions (pages 1-6,15)
//        Test the ALUB input to the ALU (T file)
//        Check R_H3P_ALUOUT_(ALUB = T file) (uses ALUOUT = "T" code)

and Test7() be
[
	SpeakTest(7) //set initial conditions (see notes at end of ALU.TST)

//Set up initial conditions

	{Cycle0Feed'}=1; //for TWrite and rbus_H3P
	{BSEL.0}=1; //for H2_T
	{aluf}=0; //for ALUOUT_ALUB

//Preliminary data path test (T address is constant: TA=0 from SpeakTest)

	for i = 0 to 15 do
	[
		{BBFA'}=0; //for ALUB_MASK
		ClockCycle0() //ALUF()_0 for ALUOUT_ALUB, EnableMask_1 for ALUB_MASK

		{MASK} = 1 lshift i
		ClockCycle0() //H3P_(ALUOUT=ALUB=MASK = 1 lshift i)
		RClock() //T_(rbus=H3P=b) (address =j)

		{BBFA'}=1; //for ALUB_H2
		ClockCycle0() //H2_(T = 1 lshift i) (address =j)
		              //EnableMask_0 for ALUB_H2
		ClockCycle0() //H3P_(ALUOUT=ALUB=H2 = 1 lshift i)
		WCompare({rbus},1 lshift i,7000+i) //(rbus=H3P = 1 lshift i)
	]


//Main T file test: involves storing both 1's and 0's in every cell of every address

	for i = 0 to 1 do
	[
		{BBFA'}=0; //for ALUB_MASK
		ClockCycle0() //ALUF()_0 for ALUOUT_ALUB, EnableMask_1 for ALUB_MASK

		for j = 0 to 15 do //Write test pattern
		[
			let a = (j*7) rshift 3 //"non-synchronous hex"
			let b = (a*#10421) xor (-i) //a in all hexes, inverted if i odd
			{TA}=j
			{MASK}=b
			ClockCycle0() //H3P_(ALUOUT=ALUB=MASK=b)
			RClock() //T_(rbus=H3P=b) (address =j)
		]

		{BBFA'}=1; //for ALUB_H2

		for j = 0 to 15 do //Read test pattern
		[
			let a = (j*7) rshift 3 //"non-synchronous hex"
			let b = (a*#10421) xor (-i) //a in all hexes, inverted if i odd
			{TA}=j
			ClockCycle0() //H2_(T=b) (address =j)
			              //EnableMask_0 for ALUB_H2
			ClockCycle0() //H3P_(ALUOUT=ALUB=H2=b)
			WCompare({rbus},b,7100+i,j) //(rbus=H3P=b)
		]
	]
]

//**************************************************************************************
//Test 8: Test some basic ALU functions before proceeding to more complex ALU tests

and Test8() be
[
	SpeakTest(8) //set initial conditions (see notes at end of ALU.TST)

	//Initialization (pages 10,15):
	//SpeakTest sets up conditions to enable clkH3P' and clkResult' during Cycle0,
	//also, Restore'=1 for SavALUCyOut_ALUCyOut when clkResult' is active

//PART 1: Test the EXCLUSIVE OR functions

	for i = 0 to 1 do
	[
		{aluf} = 4 % (3*i); //4 if i=0 ("R xor T"), 7 if i=7 ("R xor (not T)")

		for j = 0 to 15 do
		[
			let a = 1 lshift j

			{Cycle0Feed'}=0
			{rbus} = a
			EClock() //H1_(rbus = a) (ALUA input)
			         //H2_(Bmux = F1F2 = 0) (ALUB input)
			         //ALUF()_4 if i=0 ("R xor T"), 7 if i=7 ("R xor (not T)")
			EClock() //H3P_(ALUOUT = a xor 0 if i=0, a xor #177777 if i=1)
			{rbus}=###

			{Cycle0Feed'}=1; //rbus_H3P
			WCompare({rbus},a xor (-i),8000+i,j)
		]
	]


//PART 2: Test Carry propagation and generation using cases involving strings of 1's

	//Set up conditions for J-TestResult'_SavALUCyOut' (page 10)
	//(BranchShift'=1 from SpeakTest initialization)
	{JA.7}=1; //for h19 mux address inputs = 001 (JC.1 = JC.2 = 0 from SpeakTest)

	for i = 0 to 16 do
	[
		let a = 1 lshift i
		let b = #177777 lshift i //b = -a, while b' = a-1
		let c = i rshift 4 //i=16 for END CARRY WCompares

	//Test propagation of ALUCarryIn into each bit position

		{aluf}=10; //for "R+T+1" (R+0+1 since H2=0)
		{Cycle0Feed'}=0
		{rbus} = not b; //propagates ALUCarryIn into bit position "a"
		EClock() //H1_(rbus=b'=a-1), H2_0, ALUF()_"R+T+1"
		EClock() //H3P_(ALUOUT=(a-1)+0+1=a)
		         //clkResult': SavALUCyOut_ALUCyOut
		{rbus}=###

		{Cycle0Feed'}=1; //rbus_H3P
		WCompare({rbus},a,8100+i) //sum=a

		//Check END CARRY =0 until i=16 ((a-1=#177777)+0+1 = #200000)
		WCompare((not {J-TestResult'})&1,c,8150+i)

	//Test killing of ALUCarryIn by each bit position

		//{aluf} still =10; //for "R+T+1" (R+0+1 since H2=0)
		{Cycle0Feed'}=0
		{rbus} = not a; //kills ALUCarryIn at bit position "a"
		EClock() //H1_(rbus=a'), H2_0, ALUF()_"R+T+1"
		EClock() //H3P_(ALUOUT=a'+0+1=-a)
		         //clkResult': SavALUCyOut_ALUCyOut
		{rbus}=###

		{Cycle0Feed'}=1; //rbus_H3P
		WCompare({rbus},b,8200+i) //sum=-a

		//Check END CARRY =0 until i=16 (#177777+0+1 = #200000)
		WCompare((not {J-TestResult'})&1,c,8250+i)

	//Test generation of a carry by each bit position
	//and its propagation into the END CARRY position

		{aluf}=13; //for "R-T-1" (i.e. R+T') (R+#177777+0 since H2=0)
		{Cycle0Feed'}=0
		{rbus}=a; //generates Carry out of bit position "a"
		EClock() //H1_(rbus=a), H2_0, ALUF()_"R-T-1"
		EClock() //H3P_(ALUOUT=a+#177777+0=a-1)
		         //clkResult': SavALUCyOut_ALUCyOut
		{rbus}=###

		{Cycle0Feed'}=1; //rbus_H3P
		WCompare({rbus},a-1,8300+i) //sum=a-1

		//Check END CARRY =1 until i=16 (0+#177777+0 = #177777)
		WCompare({J-TestResult'},c,8350+i)
	]
]