//**************************************************************************************
//MISC3.TST
//By C. Thacker and M. Thomson  						February 15, 1979
//Modified by Frank Vest 6-12-80 to test rev. gb multiwire boards properly
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//{mirbus: MemInst/d',RMOD/d,  RSEL.0/d',RSEL.1/d',RSEL4and5/d}

//{promb19bus: ALUF.0,ALUF.1,  ALUF.2,ALUF.3,SRC/DEST=0'}

//**************************************************************************************
//Test 7: Partially check the b19 prom and the b18, b17 flip-flops (page 1)
//        (Only the edge-pin outputs are tested here; other outputs are tested later.)

let Test7() be
[
	SpeakTest(7) //set initial conditions (see notes at end of MISC.TEST)

	//{MC1/MC2outpins: MC1DQWRef',MC1QWRef',  MC2AllowWrite,MC2DQWRef',MC2QWRef'}

	let t7sb = table [ #37;#37;#37;#37;  #04;#04;#37;#37;
	                   #37;#37;#15;#15;  #04;#04;#37;#37;
	                   #33;#33;#11;#11;  #04;#04;#33;#33;
	                   #37;#37;#37;#37;  #04;#04;#37;#37 ]

	for i = 0 to 31 do
	[
		{promb19bus}=i
		ClockAd()  //b18 ff's ← b19 prom
		ClockMC2() //b17 ff's ← b18 ff's
		WCompare({MC1/MC2outpins},t7sb!i,7000,i)
	]

	//Check that clkAd' and clkMC2' are inactive when qualifiers are off

	{promb19bus}=4; //for b19 prom, pin 1 =0
	EClock() //LoadAd'=1, hence clkAd' is inactive
	WCompare({MC1DQWRef'},1,7001) //should stay =1

	ClockAd() //MC1DQWRef'←0
	EClock() //AdvancePipe'=1, hence clkMC2' is inactive
	WCompare({MC2DQWRef'},1,7002) //should stay =1

]

//**************************************************************************************
//Test 8: Test the PAbort logic (pages 1,2)

and Test8() be
[
	SpeakTest(8) //set initial conditions (see notes at end of MISC.TEST)

	{LoadMIR}=1; //all clocks except ClockCycle0 will load MIR

//Initial conditions from SpeakTest (partial list):

	//EmRef=0, BPC-Refill'=1, StartFault'=1, MC2Active'=1, MC1Active'=1
	//MC1Compa=0, MC1Compb=0, MC2Compa=0, MC2Compb=0, MemInst-a=0
	//Cycle0=0

	//Confirm that above terms result in all inputs to the a17 gate =1

	ClockCycle0() //PAbort←0
	WCompare({PAbort},0,8000)

//Test the pin 4,3,2 inputs to gate a17, check DC reset of PAbort (RUN=0)

	//{t8dr1: StartFault',  BPC-Refill',EmRef,NewInst'}

	let t8sb1 = table [ 0;0;0;1; 1;1;1;1; 1 ]

	for i = 0 to 8 do
	[
		{t8dr1} = i xor #15
		ClockCycle0() //PAbort←t8sb1!i
		WCompare({PAbort},t8sb1!i,8001,i)
	]

	{RUN}=0; //PAbort←0 (check DC reset)
	{RUN}=1; //restore to normal
	WCompare({PAbort},0,8002)

	{StartFault'}=1; //deactivate for future tests

//Test the pin 1,5,6 inputs to gate a17, (StkpInUse logic)

	//Test the StkpInUse signal by qualifying the a16a gate
	{MC1Active'}=0
	{RSEL.2/d}=1; //for StkpDown=1
	{mirbus}=#31; //StkpInUse configuration:
	              //MemInst=0, RMOD=1, RSEL=11 xx 11
	{promb19bus}=#12; //for prom b19, pin 7 =1
	ClockAd() //MC1StkPf2P←1 (b18 ff), (raises StkPf2P since MC1Active=1)
	          //Load MIR (e16 ff's): StkpInUse←1, StkpDown←1
	ClockCycle0() //PAbort←1 (a16a gate active)
	WCompare({PAbort},1,8010)

	//Check that clkMIR' is inactive unless Cycle0=0 and LoadMIR=1
	//{clkMIRbus: Cycle0Feed',LoadMIR}
	{RSEL4and5/d}=0; //a false clkMIR' would cause StkpInUse←0

	for i = 0 to 2 do
	[
		{clkMIRbus}=i
		EClock() //probe clkMIR' gate
		ClockCycle0() //should not change PAbort since StkpInUse should stay =1
		WCompare({PAbort},1,8012,i)
	]

	{LoadMIR}=1; //resume all clocks except ClockCycle0 will load MIR

	//Check that StkpInUse is =0 in all mirbus cases except #31 (using the a16a gate)

	for i = 0 to #36 do
	[
		{mirbus} = i xor 6
		EClock() //Load MIR (e16 ff's): StkpInUse←0, StkpDown←1
		ClockCycle0() //PAbort←0
		WCompare({PAbort},0,8020,i)
	]

	//Check that StkpInUse properly qualifies gate a16b

	{promb19bus}=#22; //for prom b19, pin 9 =1
	{RSEL.2/d}=0; //for StkpUp=1
	ClockAd() //MC1StkPsP←1, MC1StkPf2P←0, StkpUp←1, StkpDown←0
	          //b16d gate becomes active, b16b gate becomes inactive
	ClockCycle0() //PAbort←0 since StkpInUse=0
	WCompare({PAbort},0,8021)

	{RSEL4and5/d}=1; //for mirbus=#31
	EClock() //StkpInUse←1
	ClockCycle0() //PAbort←1
	WCompare({PAbort},1,8022)

	//With StkpInUse=1, check all input values of signals to gates a16a and a16b

	//{t8dr2: MC1Active',MC2Active',  RSEL.2/d,ALUF.0,ALUF.1}

	let t8sb2 = table [ 0;0;0;0;0;0;0;0; 0;0;0;1;0;0;1;0; 0;0;1;0;0;1;0;0 ]

	//note: promb19bus=#22. Counting ALUF[0:1], then ClockAd, results in:
		//ALUF[0:1]=1 => prom b19 addr =#12 => MC1StkPf2P←1 (otherwise ←0)
		//ALUF[0:1]=2 => prom b19 addr =#22 => MC1StkPsP ←1 (otherwise ←0)

	for i = 0 to 23 do
	[
		{t8dr2} = i xor #30
		ClockAd()  //load b18 ff's, load MIR (StkpDown←i[13])
		ClockCycle0() //PAbort←t8sb2!i
		WCompare({PAbort},t8sb2!i,8030,i)
		ClockMC2() //load b17 ff's (placed here so b17's lag b18's for WCompare)
	]

	//check that all prom b19 addresses yield proper pin 7,9 outputs
	//using b16b and b16d gates (MC1Active=1 and StkpInUse=1 from above logic)

	let t8sb3 = table [
		0;0;0;0;0;0;0;0; 0;0;0;0;0;0;0;0; 1;0;1;0;0;0;0;0; 0;0;0;0;0;0;0;0;
		0;0;0;0;0;0;0;0; 0;0;1;0;0;0;0;0; 0;0;0;0;0;0;0;0; 0;0;0;0;0;0;0;0 ]

	for i = 0 to 63 do
	[
		{RSEL.2/d} = i rshift 5; //for StkpDown←i[10]
		{promb19bus} = i; //i[11:15]
		ClockAd() //load b18 ff's, load MIR: StkpDown←i[10]
		ClockCycle0() //PAbort←t8sb3!i
		WCompare({PAbort},t8sb3!i,8040,i)	
	]

	{RSEL4and5/d}=0
	EClock() //load MIR: StkpInUse←0 (for future tests)

//Test the pin 11,12 inputs to gate a17 (InstReadingR and InstWritingR logic)

	//{MC1/MC2Comp: MC1Compa,  MC1Compb,MC2Compa,MC2Compb}

	//{t8dr4: MC1Active',MC2Active',  MemInst-a,ALUF.0,ALUF.1}

	let t8sb4 = table [ 0;0;0;0;0;0;0;0; 0;0;1;1;0;0;1;0; 0;1;1;0;0;1;0;0; 0;1 ]

	{promb19bus}=3; //Counting ALUF[0:1], then ClockAd, results in:
		//ALUF[0:1]=1 => prom b19 addr =#13 => MC1PfP←1 (otherwise ←0)
		//ALUF[0:1]=2 => prom b19 addr =#23 => MC1PsP←1 (otherwise ←0)

	{MC1/MC2Comp}=#17; //enable gates f16a and f16b
	{LR}=1
	//note: ALUF[0:3]#0 (since ALUF.3=1, until changed later)

	for i = 0 to 25 do
	[
		{t8dr4} = i xor #30
		ClockAd()  //load b18 ff's
		ClockCycle0() //PAbort←t8sb4!i
		WCompare({PAbort},t8sb4!i,8050,i)
		ClockMC2() //load b17 ff's (placed here so b17's lag b18's for WCompare)
	]

	//Test the MC1/MC2Comp qualifiers
	//Status: MC1Actve=1, MC2Active=1, MC1PfP=1, MC2PfP=1'
	//        MemInst-a=0, ALUF[0:3]#0, (hence a16c, a15b gates are active)

	let t8sb5 = table [ 0;0;0;1; 0;0;0;1; 0;0;0;1; 1;1;1;1 ]

	for i = 0 to 15 do
	[
		{MC1/MC2Comp} = i
		ClockCycle0() //PAbort←t8sb5!i
		WCompare({PAbort},t8sb5!i,8060,i)
	]

	//Test the a13a gate (ALUF[0:3]=0 disqualifies InstReadingR)

	let t8sb6 = table [ 0;1;1;1; 1;1;1;1; 1 ]

	for i = 0 to 8 do
	[
		{promb19bus} = i lshift 1; //ALUF[0:3]←i[12:15]
		ClockCycle0() //PAbort←t8sb6!i
		WCompare({PAbort},t8sb6!i,8070,i)
	]

	//Check that LR=0 disqualifies InstWritingR

	{promb19bus}=#23
	ClockAd()  //MC1PsP←1, MC1PfP←0
	ClockMC2() //MC2PsP←1, MC2PfP←0
	ClockCycle0() //PAbort←1
	WCompare({PAbort},1,8080)

	{LR}=0
	ClockCycle0() //PAbort←0
	WCompare({PAbort},0,8081)

	//Check that all prom b19 addresses yield proper pin 3,8 outputs
	//using the a15b and a15c gates (MemInst-a still =0)

	let t8sb7 = table [
		0;0;0;0;0;0;0;0; 0;0;0;0;0;0;0;0; 1;1;1;1;1;1;1;1; 0;0;0;0;1;1;0;0;
		0;0;0;0;1;1;0;0; 1;1;1;1;1;1;1;1; 0;0;0;0;0;0;0;0; 0;0;0;0;1;1;0;0 ]

	{MC2Active'}=1; //only MC1Active remains =1

	for i = 0 to 63 do
	[
		{promb19bus} = i; //prom b19 addr.←i[11:15]
		ClockAd() //load b18 ff's (MC1PfP, MC1PsP)

		{promb19bus} = 0; //for ALUF[0:3]=0
		{LR} = not (i rshift 5); //check MC1PsP when i[10]=0
		{ALUF.3} =  i rshift 5 ; //check MC1PfP when i[10]=1

		ClockCycle0() //PAbort←t8sb7!i
		WCompare({PAbort},t8sb7!i,8090,i)
	]

//Test the InstReadingStack logic (page 2) (rev. J)

	//Check that with StkpInUse=1, InstReadingStack=InstReadingR

	{mirbus}=#31; //StkpInUse configuration:
	              //MemInst=0, RMOD=1, RSEL=11 xx 11
	EClock() //clkMIR': StkpInUse←1

	//{t8dr8: MemInst-a,ALUF.0,  ALUF.1,ALUF.2,ALUF.3}

	for i = 0 to 16 do
	[
		{t8dr8}=i
		WCompare({InstReadingStack},(#177776 rshift i)&1,8100,i) 
	]

	//Check that StkpInUse=0 disqualifies InstReadingStack

	{MemInst-a}=0; //for InstReadingR←1
	{RMOD/d}=0; // for StkpInUse←0
	EClock() //clkMIR': StkpInUse←0
	WCompare({InstReadingStack},0,8101)
]

//**************************************************************************************
//Test 9: Test the R parity logic (page 1)
//        Test the IOStrobe logic (page 8) (revision E-1 and E-3 boards)
//        Test the Odata.16 logic (page 1) (revision E-1 boards)

and Test9() be
[
	SpeakTest(9) //set initial conditions (see notes at end of MISC.TEST)


//PART 1: Test the R parity logic (page 1)

	//Test the RPByte0In and RPByte1In parity generators:

	for i = 0 to 255 do
	[
		let a = i % (i lshift 8) //R bytes are equal
		let par = i<<w.b8  xor i<<w.b9  xor i<<w.b10 xor i<<w.b11 xor
		          i<<w.b12 xor i<<w.b13 xor i<<w.b14 xor i<<w.b15
		{rbus} = a
		EClock()
		WCompare({RPByte0In},par,9000,i)
		WCompare({RPByte1In},par,9001,i)
	]


	//Test the RParityError' logic (gate e11c - page 1)

	//{t9dr1: EnableRDlyd2,R.00,  R.08,RPByte0,RPByte1}

	let t9sb1 = table [
		1;1;1;1;1;1;1;1;  1;1;1;1;1;1;1;1;  1;0;0;1;0;1;1;0;  0;1;1;0;1;0;0;1 ]

	{rbus}=0; //initialize so R.00 and R.08 can control RPByte0In and RPByte1In

	for i = 0 to 31 do 
	[
		{t9dr1}=i
		EClock() //RPByte0In←i[12], RPByte1In←i[13]
		EClock() //h18b ff ← 0 if i[12]=i[13], else 1
		WCompare({RParityError'},t9sb1!i,9100,i)
	]


//PART 2: Test the IOStrobe logic (page 8) (revision E-1 and E-3 boards)

	//Test to see if the IOStrobe signal is connected to Edge pin 47 and is =0 (F1=0)
	WCompare({IOStrobe},0,9199) //fails if rev. E-1 not installed

	let notrevE1 = {IOStrobe} //for preventing 62 stops on next loop in unmodified boards

	for i = 0 to 63 do
	[
		{Cycle0Feed'} = i rshift 5; //GoCycle1←i[10] (for E-3 boards)
		{F2}=i; //F2ok←i[11], F2[0:3]←i[12:15]

		WCompare({IOStrobe},((i eq #63)&1) % notrevE1,9200,i)
		//unmodified rev. E boards will not stop (due to notrevE1 term)
		//modified rev. E boards with E-1 but not E-3 change should stop when i=#23
		//modified rev. E boards with both E-1 and E-3 changes should not stop
	]


//PART 3: Test the Odata.16 logic (page 1) (revision E-1 boards)

	//{t9dr3: GateALUParity,RPByte0,RPByte1}

	let t9sb3 = table [ 1;1;1;1;  1;0;0;1 ]

	//Set old signal MC2EnableRP' to 1 for predictable failure on unmodified rev. E boards
	ClockAd()  //b18,pin12 ff ←1 (prom b19 address =0 from SpeakTest initialization)
	ClockMC2() //b17,pin12 ff (MC2EnableRP') ← (b18,pin12 ff =1)

	for i = 0 to 7 do
	[
		{t9dr3}=i
		WCompare({Odata.16},t9sb3!i,9300+i)
		//unmodified rev. E boards will stop when i=5,6
	]
]