//**************************************************************************************
//MISC1.TST
//By C. Thacker and M. Thomson January 19, 1979
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"
//Edge pin signal busses used by all MISC test modules:
//{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15}
//{F1: F2ok,F1ok,F1.0, F1.1,F1.2,F1.3}
//{F2: F1ok,F2ok,F2.0, F2.1,F2.2,F2.3}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:
//(none)
//**************************************************************************************
//Test 1: Check initial conditions established by SpeakTest
let Test1() be
[
SpeakTest(1) //set initial conditions (see notes at end of MISC.TEST)
//The following busses correspond to "miscbus1-5" used in the SpeakTest portion of MISC.TST
//{t1bus1: ALUF.0, ALUF.1,ALUF.2,ALUF.3, CTask.0,CTask.1,CTask.2, CTask.3,H2.08,H2.09, H2.10,H2.11,H2.12, H2.13,H2.14,H2.15} 16 bits
//{t1bus2: BSEL.0, BSEL.1,F1ok,F1.0, F1.1,F1.2,F1.3, F2ok,F2.0,F2.1, F2.2,F2.3,LR, LT,RPByte0,RPByte1} 16 bits
//{t1bus3: EmRef, EnableRDlyd2,GateALUParity,IOInst, LoadMIR,MC1Compa,MC1Compb, MC2Compa,MC2Compb,MemInst-a, Plus24,RMOD/d,RSEL.2/d, RSEL4and5/d,SRC/DEST=0',Suspend-a} 16 bits
//{t1bus4: Abort', AdvancePipe',BPC-Refill',Cycle0Feed', LoadAd',MC1Active',MC2Active', MemInst/d',NewInst',Phase1Next', RSEL.0/d',RSEL.1/d',StartFault'} 13 bits
//{t1bus5: EdgeClockFeed',RamClockFeed',RUN, R←DBSB',R←NBR',R←PCXF'} 6 bits
//Check that the busses initialized by SpeakTest are in the proper states:
WCompare({ALUA},0,1000)
WCompare({t1bus1},0,1001)
WCompare({t1bus2},0,1002)
WCompare({t1bus3},0,1003) //16-bit bus
WCompare({t1bus4},#17777,1004) //13-bit bus
WCompare({t1bus5},#77,1005) //6-bit bus
//Manipulate the busses to detect possible shorts:
//first move a single "1" through a field of "0"'s
//then, move a single "0" through a field of "1"'s
for i = 0 to 1 do
[
{ALUA} = -i
{t1bus1} = -i
{t1bus2} = -i
{t1bus3} = -i
{t1bus4} = -i
for j = 0 to 16 do
[
let a = (1 lshift j) xor -i
{rbus}=###; //disconnect tester drivers from rbus
{t1bus5}=a
WCompare({t1bus5},a & #77,1100+i,j) //6-bit bus
{t1bus5} = -i % 7; //disable MISC module rbus sources with "% 7"
{rbus}=a
WCompare({rbus},a,1200+i,j)
{ALUA}=a
WCompare({ALUA},a,1300+i,j)
{t1bus1}=a
WCompare({t1bus1},a,1400+i,j)
{t1bus2}=a
WCompare({t1bus2},a,1500+i,j)
{t1bus3}=a
WCompare({t1bus3},a & #177777,1600+i,j) //16-bit bus
{t1bus4}=a
WCompare({t1bus4},a & #17777,1700+i,j) //13-bit bus
]
]
]
//**************************************************************************************
//Test 2: Test the function decoder outputs available on edge pins (page 8)
// (except for IOStrobe, which is checked in Test 9)
let Test2() be
[
SpeakTest(2) //set initial conditions (see notes at end of MISC.TEST)
//The following 10-bit bus contains all the function decodes that appear on edge pins (inactive state = #1677):
//{ExtFns: BBFA', NextInst',Stkp←ALUA',FreezeResult, StackShift',SpareF2',BranchShift', SALUF←H2',ResetMemErrs',UseCoutAsCin'}
//Table of contributions to ExtFns
let t2table = table [
0;0;0;0; 0;0;0;0; 0;0;0;0; 0;0;0;0;
0;#200;#100;#40; 0;0;0;#20; #10;4;0;0; 0;2;1;0;
#1000;0;0;0; 0;0;0;0; 0;0;0;0; 0;0;#400;0;
#1000;#200;#100;#40; 0;0;0;#20; #10;4;0;0; 0;2;#401;0 ]
for i = 0 to 63 do
[
{F1}=i; //for F1[0:3]←i[12:15]
{F2}=i; //F1ok←i[10], F2ok←i[11], F2[0:3]←i[12:15]
let sb = #1677 xor (t2table!i)
WCompare({ExtFns},sb,2000,i)
{NewInst'} = not i
WCompare({NewInst},i&1,2001,i)
]
]
//**************************************************************************************
//Test 3: Test the printer interface (page 10)
and Test3() be
[
SpeakTest(3) //set initial conditions (see notes at end of MISC.TEST)
//This test requires a 37-pin male D-shell connector
//plugged into the PRINTER interface socket.
//The connector is wired as follows:
// 21 -> 9 (PO.0' -> PI.0)
// 23 -> 10 (PO.1' -> PI.1)
// 25 -> 11 (PO.2' -> PI.2)
// 27 -> 12 (PO.3' -> PI.3)
// 29 -> 13 (PO.4' -> PI.4)
// 20 ->470 ohms -> 1 (PO.0 pulls up/down PD.0)
// 22 ->470 ohms -> 2 (PO.1 pulls up/down PD.1)
// 24 ->470 ohms -> 3 (PO.2 pulls up/down PD.2)
// 26 ->470 ohms -> 4 (PO.3 pulls up/down PD.3)
// 28 ->470 ohms -> 5 (PO.4 pulls up/down PD.4)
// 30 ->470 ohms -> 6 (PO.5 pulls up/down PD.5)
// 32 ->470 ohms -> 7 (PO.6 pulls up/down PD.6)
// 32 ->470 ohms -> 8 (PO.6 pulls up/down PD.7)
// 31 -> pin 1 of "x" (see below) (PO.5')
// 33 -> pin 2 of "x" (see below) (PO.6')
// 35 -> pin 3 of "x" (see below) (PO.7')
// 34 -> pin 4 of "x" (see below) (DriveOutput')
// "x" is a 16-pin Augat plug.
// Connecting wires should be 20 inches long.
// The plug is for Tester socket "E".
//initialize
{R←PCXF'}=0; //enable c1 and d1 rbus gates when F2=#20
//Check that ALUA[0:7] can be transmitted to PO[0:7]' and associated logic (page 10)
for i = 0 to 7 do
[
{ALUA} = #400 lshift i
ClockP() //load printer output register (c3 and d2 flip-flops)
//The test connector wires the PO[0:4]' drivers to the PI[0:4] lines, while
//PO[5:7]' and DriveOutput' are wired from the test connector to tester socker "E"
//{t3bus1: R.00,R.01, R.02,R.03,R.04, PO.5',PO.6',PO.7'}
WCompare({t3bus1},(1 lshift i) xor #377,3000+i) //(ALUA[0:7]')
WCompare({DriveOutput'},1 rshift i,3050+i) //(ALUA.07)
WCompare({PI.2},(#337 rshift i)&1,3100+i) //(ALUA.02') - check edge pin 049
]
//Check that the output register can drive the PD[0:7] lines high and low
//in the presence of 470 ohm pullup/down resistors of the opposite sense
//tied from PD[0:5] to PO[0:5] and PD[6:7] to PO.6 via the test connector.
//***** THE R-PACK IN LOCATION b2(u158) MUST BE REMOVED FOR THIS TEST TO FUNCTION! *****
for i = 0 to 7 do
[
let drive = 1 lshift i
//pull down PD lines with PO[0:3]=0, enable PD drivers with DriveOutput'=0
{ALUA} = drive
ClockP() //load printer output register
WCompare({rbus}Ź,drive,3200+i)
//pull down PD lines with PO[0:3]=0, disable PD drivers with DriveOutput'=1
{ALUA} = drive % #400
ClockP() //load printer output register
WCompare({rbus}Ź,0,3300+i) //if stop, make sure b2(u158) R-PACK has been removed
//pull up PD lines with PO[0:3]=1, enable PD drivers with DriveOutput'=0
{ALUA} = drive % #177000
ClockP() //load printer output register
WCompare({rbus}Ź,drive,3400+i)
//pull up PD lines with PO[0:3]=1, disable PD drivers with DriveOutput'=1
{ALUA} = drive % #177400
ClockP() //load printer output register
WCompare({rbus}Ź,#377,3500+i)
]
//Check the voltage monitors (r[5:7], page 10)
WCompare({R.05},1,3601) //c1.15 should = +2.6v (logic high) (VDD monitor)
WCompare({R.06},0,3602) //c1.13 should = 0v (Plus24 monitor - ground from tester)
WCompare({R.07},0,3603) //c1.11 should = 0v (VEE monitor)
]
//Generate a clkPrinter' pulse to load the c3 and d2 flip flops (page 10)
and ClockP() be
[
{F2}=#37; //for Printer←ALUA =1
{EdgeClockFeed'}=0; //GoCycle0 =1 from SpeakTest, clkPrinter' now =0
{EdgeClockFeed'}=1; //c3 ff's ← ALUA[0:7], d2 ff's ← ALUA[8:15]
{F2}=#20; //for Rshift=1 to enable c1 and d1 rbus gates
]