//**************************************************************************************
//MEMB.TST
//By B. Rosen and M. Thomson April 24, 1979
//Main Test Program for UTFP Controller Module
//**************************************************************************************
//NOTES: 1) This test is for rev. M S/W or Etch #1 boards and rev. B Etch #2 boards.
// (See MEMA.TST for prom revisions.)
// (If MC2 Sequencer proms are not rev. E or D, only the final test (Test 4) will fail.)
// 2) Run the MEMA test first
// 3) Remove test cable #4 from socket "E" to f14(u94/u60), d2(u12/u15), and e4(u43/u44).
// 4) Transfer the test clip from location b5(u40/u45) to location g2(u32/u42)
// 5) Remove the test clip from location b9(u54/u135) and let it dangle
// 6) Install test cable #5 from socket "E" to the locations listed below
//**************************************************************************************
//DUMP FILES in ifs-2 under <Thomson>:
//See MEMA.TST. The dump files listed contain MEMA, MEMB, and MEMC tests
//**************************************************************************************
//INSTALL THE FOLLOWING TEST CONNECTORS:
//CABLE #1: Tester socket "B" to the following
// 20-pin clip to c4 (u41/u46)
// DisableMC1: c4.1,1
// R←Pipe': c4.2,2
// MC1Pipe.1: c4.5,3
// MC1Pipe.2: c4.6,4
// MC1Pipe.3: c4.9,5
// LoadPipe: c4.12,6
// MC1Ref': c4.15,7
// MC1Store': c4.16,8
// 14-pin clip to e9 (u98/u100)
// MC2SetFault: e9.5,9
// LDisableMC1': e9.13,10
// 16-pin clip to h2 (u46/u26)
// Disableh2: h2.14,11
// ChkPhase0': h2.12,12
// 20-pin clip to e2 (u35/u70)
// Disablee2: e2.1,13
// Odata←Cdat': e2.9,14
// R←H3U': e2.15,15
// R←H3C': e2.16,16
//CABLE #2: Tester socket "C" to the following
// 20-pin clip to g14 (u112/u140)
// R←H3I': g14.1,1
// 16-pin clip to b3 (u26/u30)
// MC1Next.4: b3.3,2
// MC1Next.5: b3.2,3
// 20-pin clip to b6 (u29/u47)
// preMC1Next.6: b6.6,4
// preMC1Next.7: b6.9,5
// MC1TestH4Par: b6.12,6
// MC1TestFault: b6.15,7
// MC1SetFault: b6.16,8
// PreloadMC1': b6.19,9
// 20-pin clip to h3 (u30/u73)
// DisableMC2: h3.1,10
// LoadSyndrome: h3.5,11
// preLoadOdata': h3.6,12
// MC2Hold': h3.12,13
// MC2WriteCdat: h3.15,14
// MC2NeedsR': h3.16,15
// MC2NeedsRIfSNE0: h3.19,16
//CABLE #3: Tester socket "D" to the following
// 20-pin clip to g2 (u32/u42)
// MC2Next.4: g2.2,1
// MC2Next.5: g2.5,2
// MC2Next.6: g2.6,3
// preMC2Next.7: g2.9,4
// MC2TestSE: g2.12,5
// MC2TestDE: g2.15,6
// 16-pin clip to c2 (u10/u13)
// MC1Next.7': c2.15,7
// 20-pin clip to d4 (u42/u48)
// MC1SXport: d4.5,8
// MC1WriteMem: d4.12,9
// MC1StartMC2: d4.15,10
// MC1ClkOutput: d4.16,11
// PreRowAd': d4.19,12
// 20-pin clip labelled b9 (u54/u135) is clipped nowhere (dangles)
//CABLE #5: Tester socket "E" to the following
// 20-pin clip to b9 (u54/u135)
// Disableb9: b9.1,1
// MC1Ftype.0: b9.2,2
// MC1Ftype.1: b9.5,3
// NewPipe: b9.6,4
// MC1Pipe.0: b9.9,5
// Refresh'b: b9.15,6
// PStore12': b9.16,7
// EnInputParChk: b9.19,8
// 16-pin clip to i2 (u45/u10)
// MC2Next.0: i2.5,9
// MC2Next.1: i2.6,10
// MC2Next.2: i2.7,11
// MC2Next.3: i2.4,12
// MC2Next.7': i2.15,13
// 16-pin clip to f14 (u94/u60)
// Disablef14: f14.14,14
// MC2SE: f14.12,15
// MC2DE: f14.11,16
//**************************************************************************************
get "memb.d"
static
[
mc2 //vector for mc2 prom pattern
pass = 0
otime = 0
exectime = 0
]
//Edge pin and test connector signal busses available to this sub-test:
//{Idata: Idata.00, Idata.01,Idata.02,Idata.03, Idata.04,Idata.05,Idata.06, Idata.07,Idata.08,Idata.09, Idata.10,Idata.11,Idata.12, Idata.13,Idata.14,Idata.15}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//{StorDin: StorDin.00, StorDin.01,StorDin.02,StorDin.03, StorDin.04,StorDin.05,StorDin.06, StorDin.07,StorDin.08,StorDin.09, StorDin.10,StorDin.11,StorDin.12, StorDin.13,StorDin.14,StorDin.15}
//**************************************************************************************
//main program for MEMB module test
let main() be
[
//first, allocate space for the mc2 prom tables and read them from the .mb files (which must be on your disk)
let v = vec 256*4
mc2 = v
readmc12("D0mem2-D.mb",mc2,1)
//now do the tests forever
[
pass = pass+1
Test1()
Test2()
Test3()
Test4()
] repeat
]
//**************************************************************************************
//Routines available for MEMB module tests
//Wait-Comparison routine
and WCompare(was,sb,testno,drive; numargs na) be
[
if was eq sb then return
Ws(FORMATN("*nTest <D>: Was = <B>, Should be = <B>",testno,was,sb))
if na gr 3 then Ws(FORMATN(", drive = <B>",drive))
while Endofs(keys) do [ ]
Gets(keys)
Ws("*nRunning...")
]
//**************************************************************************************
//Clocking routines defined on page 14
and EClock() be //EdgeClockFeed' is normally high
[
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
]
and RClock() be //RamClockFeed' is normally high
[
{RamClockFeed'}=0
{RamClockFeed'}=1
]
//**************************************************************************************
and SpeakTest(testno) be
[
//Calculate the execution time for each test
let tv=vec 2
Timer(tv)
exectime = tv!1 - otime
otime = tv!1
Ws(FORMATN("*nExection Time for this test is <D> msec.",exectime))
//Set up title display
Ws("*n")
Ws("*n")
Ws(FORMATN("*nMEMB TEST (rev. M): Pass <D>, Test <D>...",pass,testno))
//SET UP MISCELLANEOUS INITIAL CONDITIONS:
//Disconnect tester output drivers from the R bus:
{rbus}=###
//Disconnect tester output drivers from various tri-state sources:
//{membus1: Odata←Cdat', R←H3C',R←H3U',StorA0, StorA1,StorA2,StorA3, StorA4,StorA5,StorA6}
{membus1}=###
//Enable tri-state source e2 and disable souces b9,f14,h2,MC1,MC2:
//{membus2: Disablee2,Disableb9,Disablef14, Disableh2,DisableMC1,DisableMC2}
{membus2}=#37
//Clear existing busses in general use:
{Idata}=0
{StorDin}=0
//Clear combined edge-pin input busses:
//{membus3: ALUF.0, ALUF.1,ALUF.2,ALUF.3, CTask.0,CTask.1,CTask.2, CTask.3,StorEcIn.0,StorEcIn.1, StorEcIn.2,StorEcIn.3,StorEcIn.4, StorEcIn.5,StorEcIn.6,StorEcIn.7}
{membus3}=0
//Set up individual edge-pin inputs:
//{membus4: Cycle0Feed', MC1XferWord,MC2XferWord,MemInst-a, MOBounds,PAbort,QWO, RamClockFeed',ReadSyn',ResetMemErrs'}
{membus4}=#107
//Tester-controllable signals to be set to 1 (from disabled tri-state sources):
//{membus5: LoadSyndrome, MC1StartMC2,MC2Hold',MC2NeedsR', PreRowAd',R←H3I',R←Pipe'}
{membus5}=#177777
//Tester-controllable signals to be set to 0 (from disabled tri-state sources):
//{membus6: ChkPhase0',MC1TestH4Par,MC2HoldIfSNE0, MC2NeedsRIfSNE0,PreloadMC1',preLoadOdata'}
{membus6}=0
//Generate 8 EClocks to flush the system and initialize EdgeClockFeed'=1:
//{Clock: EdgeClockFeed', EdgeClockFeed',EdgeClockFeed',EdgeClockFeed', EdgeClockFeed',EdgeClockFeed',EdgeClockFeed', EdgeClockFeed',EdgeClockFeed',EdgeClockFeed', EdgeClockFeed',EdgeClockFeed',EdgeClockFeed', EdgeClockFeed',EdgeClockFeed',EdgeClockFeed'}
{Clock}=#125252
]
//NOTES: The action above results in the following secondary effects
//Partial list of gate outputs:
// AdvancePipe' =0 (page 18)
// ChkSyn[0:7] =0 (pages 2,6)
// CorrectThisWord' =1 (page 3)
// H4SelIMux =1 (page 18)
// LDisableMC1' =1 (page 18)
// LoadAd' =0 (page 18)
// LoadType' =0 (page 18)
// MC2DisableMC1' =1 (page 18)
// MC2DisableMC1t' =1 (page 18)
// MC2NotReady =0 (page 18)
// MC2SynReady =1 (page 18)
// MC2WillGetR =0 (page 20)
// SNE0 =0 (page 18)
//Partial list of flip-flops:
// CrctSyn[0:7] ←(ChkSyn[0:7] =0) (page 19)
// CW2'←CW1'←CW0' ←(ChkPhase0' =0) (page 6)
// EnColAd' ←(EnRowAd' =1) (page 13)
// EnRowAd' ←(PreRowAd' =1) (page 13)
// GateALUParity ←0 since Odata←Cdat' =0 (page 10)
// h14c←h14b←h14i←h14h ←(LoadSyndrome =1) (page 3)
// i16 ff's,,b15 ff's ←(StorEcIn[0:7] =0) (pages 2,6)
// MC2HasR' ←1 since MC2WillGetR =0 (page 18)
// MC2XferingWord' ←1 since MC2XferWord =0 (page 18)
// Odata←Cdat' ←0 since preLoadOdata' =0 (page 20)
// R←H3C' ←1 since MC2XferWord =0 (page 20)
// R←H3U' ←1 since MC2XferWord =0 (page 20)
// TypeLoaded' ←0 since LoadType' =0 (page 18)
// Udat[0:15] ←(StorDin[0:15] =0) (pages 4,5)