//**************************************************************************************
//MEMA6.TST
//By B. Rosen and M. Thomson November 9, 1978
//Sub Test Program for D0 MEM Module
//**************************************************************************************
//Test 9102 and 9200 was modified to run on rev. Gb multiwireboards by Frank Vest August 14, 1980
//**************************************************************************************
get "mema.d"
//Edge pin and test connector signal busses available to this sub-test:
//{MC1bus1: MC1NeedsR, MC1StartMC2,MC1TestFault,MC1TestH4Par, MC2Hold',MemInst-a,PAbort, PreloadMC1',ALUF.0,ALUF.1, ALUF.2,ALUF.3,MC1Next.4, MC1Next.5,preMC1Next.6,preMC1Next.7}
//{MC1Next: MC1Next.0,MC1Next.1, MC1Next.2,MC1Next.3,MC1Next.4, MC1Next.5,MC1Next.6',MC1Next.7'}
//{MC1out1: MC1Next.0,MC1Next.1, MC1Next.2,MC1Next.3,MC1Next.4, MC1Next.5,preMC1Next.6,preMC1Next.7}
//{MC1out2: MC1TestH4Par,MC1TestFault, MC1SetFault,PreloadMC1',GenPhase0, IMux←Cdat,H4←IMux,MapRAS'}
//{MC1out3: MapCAS',MapWrite', IValid',R←H3I',R←Pipe', MC1Pipe.1,MC1Pipe.2,MC1Pipe.3}
//{MC1out4: LoadPipe,MC1Ref', MC1Store',StorRAS',StorCAS', MC1SXport,SXLoadD',SXLoadW'}
//{MC1out5: MC1WriteMem,MC1StartMC2, MC1ClkOutput,PreRowAd',MC1TestQWO, LoadH3I,MC1NeedsR,MC1WriteR}
//**************************************************************************************
//Test 9: Test the MC1 Control Memory clocking and addressing logic (pages 14,16,18)
let Test9() be
[
SpeakTest(9) //set initial conditions (see notes at end of MEMA.TEST)
//PART 1: Check the MC1 address bit data paths (pages 16,18)
for i = 0 to 255 do
[
//set up MC1 address control functions:
//MC2Hold'←0 for MC2NotReady←1
//MC1TestH4Par←0 to kill gate a of MC1Next.6' and gate c of LDisableMC1'
//MC1NeedsR←0, MC1TestFault←0 to kill gates a and d of MC1Next.7'
//(QWO=0 from SpeakTest kills gate c of MC1Next.7')
//MC1StartMC2←0 for MC2DisableMC1'←1 and MC2DisableMC1t'←1
// and to kill gate a of LDisableMC1'
//PAbort←0 to kill gate b of LDisableMC1'
//MemInst-a←1, PreloadMC1'←0 for LoadType'←0 (gates MC1Next[0:3]←ALUF[0:3])
//(Other LoadType' input terms are high from SpeakTest)
//ALUF[0:3]←i[8:11] for MC1Next[0:3]←i[8:11] on next EClock
//MC1Next[4:5]←i[12:13]
//preMC1Next[6:7]←i[14:15]' for MC1Next[6:7]'←i[14:15]
{MC1bus1} = i xor #2003; //set up functions noted above
EClock() //clkMC1t': MC1Next[0:3]←(ALUF[0:3]=i[8:11] since LoadType'=0)
//Check the MC1 address
WCompare({MC1Next},i,9000,i)
//Check that MC1Next[0:3] loads with 0's when LoadType'=1 and LDisableMC1=1
{MemInst-a}=0; //for LoadType'←1
{MC1StartMC2}=1; //for LDisableMC1←1
EClock() //clkMC1t': MC1Next[0:3]←(a7 S241's=0)
WCompare({MC1Next}Ũ,0,9001,i)
]
//PART 2: Check the MC2DisableMC1t' gate and clkMC1t' via MC1Next.3 (pages 14,16,18)
{MemInst-a}=1; //restore to normal from above test (for LoadType' control)
{PAbort}=1; //for LDisableMC1'←0 when TypeLoaded=1
let t9102sb = table [ 0;0;0;0;0;0;0;0;]
for i = 0 to 7 do
[
//Load MC1Next.3 with 1
{PreloadMC1'}=0; //for LoadType'←0 and MC2DisableMC1t'←1
{ALUF.3}=1; //for MC1Next.3←1
EClock() //TypeLoaded←1 since LoadType'=0 (for LDisableMC1←1)
//clkMC1t': MC1Next.3←(ALUF.3=1)
WCompare({MC1Next.3},1,9100,i) //make sure MC1Next.3 got set
WCompare({LDisableMC1'},0,9101,i) //make sure LDisableMC1=1
//Establish both MC1Next.3 input set terms =0
//LDisableMC1=1 since TypeLoaded=1 and PAbort=1
// hence, MC1Next.3 pin 13 input =0 (for LoadType'=1 cases when i<4)
{ALUF.3}=0; //for MC1Next.3 pin 14 input =0 (for LoadType'=0 cases when i>3)
//Check that MC2DisableMC1t' contols clkMC1t' by its effect on MC1Next.3
//{t9bus1: PreloadMC1',MC1StartMC2,MC2Hold'}
{t9bus1} = i xor 4; //for MC2DisableMC1t'←0 when i=2
//PreloadMC1'←i[13]'
//MC1StartMC2←i[14]
//MC2NotReady←i[15]' (since MC2Hold'←i[15])
EClock() //clkMC1t' is active except when i=2
//MC1Next.3←0 when clkMC1t' is active
WCompare({MC1Next.3},t9102sb!i,9102,i) //remains =1 when i=2
]
//PART 3: Check the clkMC1' logic (pages 14,18)
//{t9bus2: PreloadMC1', MC1StartMC2,MC2Hold',PAbort}
let t9200sb = table [ 0;1;0;1;0;1;0;0; ]
for i = 0 to 7 do
[
{t9bus2} = i xor 3
//PreloadMC1'←(i[12]=0) for LoadType'←0
//MC1StartMC2 ←i[13]
//MC2NotReady ←i[14] (since MC2Hold'←i[14]')
//PAbort←i[15]' for LDisableMC1'←i[15] when TypeLoaded=1 and PreloadMC1'=1
EClock() //TypeLoaded←1 (since LoadType'=0)
{PreloadMC1'}=1; //kill gate a of LDisableMC1' so gate b has control
WCompare({LDisableMC1'},t9200sb!i,9200,i) //make sure LDisableMC1'=i[15]
//MC2DisableMC1' will =0 when i=6,7
{EdgeClockFeed'}=0; //for EdgeClockb←1
WCompare({clkMC1'},(#325 rshift i)&1,9201,i)
{EdgeClockFeed'}=1; //for EdgeClockb←0 (restore to normal)
WCompare({clkMC1'},1,9202,i)
]
]
//**************************************************************************************
//Test 10: Test the MC1 Control Memory prom code (pages 16,17,18)
and Test10() be
[
SpeakTest(10) //set initial conditions (see notes at end of MEMA.TEST)
Ws("*nTesting MC1 Control Memory - proms MUST HAVE rev. E code!!")
//Disconnect the tester output drivers from MC1 output signals
//which are not used as inputs to this test
{MC1out2}=###
{MC1out3}=###
{MC1out4}=###
{MC1out5}=###
for i = 0 to 255 do
[
//set up MC1 address control functions:
//MC2Hold'←0 for MC2NotReady←1
//MC1TestH4Par←0 to kill gate a of MC1Next.6' and gate c of LDisableMC1'
//MC1NeedsR←0, MC1TestFault←0 to kill gates a and d of MC1Next.7'
//(QWO=0 from SpeakTest kills gate c of MC1Next.7')
//MC1StartMC2←0 for MC2DisableMC1'←1 and MC2DisableMC1t'←1
// and to kill gate a of LDisableMC1'
//PAbort←0 to kill gate b of LDisableMC1'
//MemInst-a←1, PreloadMC1'←0 for LoadType'←0 (gates MC1Next[0:3]←ALUF[0:3])
//(Other LoadType' input terms are high from SpeakTest)
//ALUF[0:3]←i[8:11] for MC1Next[0:3]←i[8:11] on next EClock
//MC1Next[4:5]←i[12:13]
//preMC1Next[6:7]←i[14:15]' for MC1Next[6:7]'←i[14:15]
//[ //test loop
{MC1bus1} = i xor #2003; //set up functions noted above
EClock() //clkMC1t': MC1Next[0:3]←(ALUF[0:3]=i[8:11] since LoadType'=0)
//Check the MC1 address
//WCompare({MC1Next},77,1,i)//test loop only
WCompare({MC1Next},i,10000,i)
{DisableMC1}=1; //Disable MC1 flip-flop outputs
//WCompare({MC1Next},77,2,i)//test loop only
//Set up LoadType'←1 and LDisableMC1←0 for MC1Next[0:3] input control
{PreloadMC1'}=1; //for LoadType'←1, LDisableMC1←0
//WCompare({MC1Next},77,3,i)//test loop only
EClock() //clkMC1t': MC1Next[0:3]←prom a4 outputs (page 16)
//clkMC1' : Load MC1 output flip-flops (bits [4:9])
//WCompare({MC1Next},77,4,i)//test loop only
{MC1bus1}=###; //Disconnect tester output drivers from MC1 flip-flop outputs
//WCompare({MC1Next},77,5,i)//test loop only
{DisableMC1}=0; //Enable MC1 flip-flop outputs
//Check the MC1 output flip-flops
//Check bits [0:7] of MC1 (proms a4 and a3 - page 16)
WCompare({MC1out1},MC1sb1(i),10001,i)
//] repeat // test loop
//Check bits [8:15] of MC1 (proms a2 and b3 - page 16)
WCompare({MC1out2},MC1sb2(i),10002,i)
//Check bits [16:23] of MC1 (proms b4 and c2 - pages 16,17)
//IValid' = inverted IValid (page 13)
WCompare({MC1out3} xor #40,MC1sb3(i),10003,i)
//Check bits [24:31] of MC1 (proms c2 and d2 - page 17)
//StorRAS' = inverted StorRAS (page 13)
//StorCAS' = inverted StorCAS when Refresh'=1 (page 13)
//SXLoadD' = inverted MC1LoadD (page 13)
//SXLoadW' = inverted MC1LoadW (page 13)
let a = MC1sb4(i)
{Refresh'}=1; //for StorCAS' and StorCASA' = inverted StorCAS (page 13)
WCompare({MC1out4} xor #33,a,10004,i)
WCompare({StorCASA'} xor 1,a<<w.b12,10005,i)
{Refresh'}=0; //for StorCAS' and StorCASA' =1
WCompare({StorCAS'},1,10006,i)
WCompare({StorCASA'},1,10007,i)
//Check bits [32:39] of MC1 (proms d3 and e3 - page 17)
WCompare({MC1out5},MC1sb5(i),10008,i)
{DisableMC1}=1; //Disable MC1 flip-flop outputs for next pass
]
]
and MC1sb1(i) = valof
[
let locp = mc1+(4*i) //look at "defined" bit
if ((locp!3)& 1) eq 0 then resultis #377
resultis locp>>mcblock.firstbyte //left half of first word
]
and MC1sb2(i) = valof
[
let locp = mc1+(4*i) //look at "defined" bit
if ((locp!3)& 1) eq 0 then resultis #377
resultis locp>>mcblock.secondbyte //right half of first word
]
and MC1sb3(i) = valof
[
let locp = mc1+(4*i) //look at "defined" bit
if ((locp!3)& 1) eq 0 then resultis #377
resultis locp>>mcblock.thirdbyte //left half of second word
]
and MC1sb4(i) = valof
[
let locp = mc1+(4*i) //look at "defined" bit
if ((locp!3)& 1) eq 0 then resultis #377
resultis locp>>mcblock.fourthbyte //right half of second word
]
and MC1sb5(i) = valof
[
let locp = mc1+(4*i) //look at "defined" bit
if ((locp!3)& 1) eq 0 then resultis #377
resultis locp>>mcblock.fifthbyte //left byte of third word
]