//**************************************************************************************
//MEMA4.TST
//By B. Rosen and M. Thomson October 18, 1978
//Sub Test Program for D0 MEM Module
// Test 6001 was changed to correct for errors caused by rev.-Gb multiwire boards August 14,1080
// Test 6001 used to fail when drive was = 7,17, or 27
// Test 6007 was changed to correct for errors caused by rev.-Gb multiwire boards August 14,1080
// Test 6007 used to fail when the drive was = 2
//**************************************************************************************
get "mema.d"
//Edge pin and test connector signal busses available to this sub-test:
//{CrctSyn: CrctSyn0,CrctSyn1, CrctSyn2,CrctSyn3,CrctSyn4, CrctSyn5,CrctSyn6,CrctSyn7}
//{StorEcIn: StorEcIn.0,StorEcIn.1, StorEcIn.2,StorEcIn.3,StorEcIn.4, StorEcIn.5,StorEcIn.6,StorEcIn.7}
//**************************************************************************************
//Test 6: Test most of the combinational logic that supports MC1
// Test most of the logic on page 18
// Test MC2WillGetR logic on page 20
// Test MC1Next.7' logic on page 16
let Test6() be
[
SpeakTest(6) //set initial conditions (see notes at end of MEMA.TEST)
//NOTE: SpeakTest initialized the following edge-pin and test-clip signals used in this test:
// Signals set to logic 1
// MC1StartMC2,MC2Hold',MC2NeedsR',MemInst-a
// Signals set to logic 0
// Cycle0Feed',MC1TestH4Par,MC2HoldIfSNE0,MC2NeedsRIfSNE0,PAbort,PreloadMC1'
// Intermediate signals derived from the above:
// LDisableMC1'=1, LoadType'=0, MC2HasR'=1, MC2NotReady=0, MC2SynReady=1,
// MC2WillGetR=0, SNE0=0, TypeLoaded=1
//Each sub-test restores the signals it uses to their initial states, except where noted
//Check states of observable control signals set up by SpeakTest
//{t6bus1: AdvancePipe',LoadAd', MC2WillGetR,Abort',LDisableMC1'}
WCompare({t6bus1},3,6000) //see notes above for input signals
//Check the LoadType' logic via TypeLoaded and gate a of LoadAd' (pages 18,20)
//Gate c of LoadAd' is disqualified by MC1StartMC2'=0
//Gate a terms of LoadAd' (other than TypeLoad) remain =1
//{t6bus2: MC2NeedsR', PreloadMC1',MemInst-a,Cycle0Feed'}
let t6001sb = table [
1;1;1;1;1;1;1;0; 1;1;1;1;1;1;1;0; 1;1;1;1;1;1;1;0; 1;1;1;1;1;1;1;0; ]
for i = 0 to 30 do //check all cases where LoadType'=1
[
{MC2NeedsR'} = i<<w.b11; //MC2WillGetR'←i[11] since gate f1a output =1 (page 20)
EClock() //MC2HasR'←(MC2WillGetR'=i[11])
{t6bus2} = i xor 5; //MC2WillGetR',PreloadMC1,MemInst-a,Cycle0 ←i[12:15]
EClock() //TypeLoaded'←(LoadType'=1), (MC2HasR'←i[12] - don't care)
WCompare({LoadAd'},t6001sb!i,6001,i) //gate a with TypeLoaded=0
]
{Cycle0Feed'}=0; //Cycle0←1
EClock() //TypeLoaded'←(LoadType'=0)
WCompare({LoadAd'},0,6002) //gate a with TypeLoaded=1
//Check gates b and d of Abort' and gate b of LDisableMC1' (page 20)
//Gates a and c of Abort' are disqualified by MC2HoldIfSNE0=0 and MC2Hold'=1
//Gates a and c of LDisableMC1' are disqualified by MC2NotReady=0 and MC1TestH4Par=0
for i = 0 to 3 do
[
{MemInst-a} = i<<w.b14
EClock() //TypeLoaded←(MemInst-a =i[14])
//PAbort=0 from prior logic, disqualifies gate d of Abort' (to test gate b)
{MemInst-a}=i; //MemInst-a ←i[15]
WCompare({Abort'},(#15 rshift i)&1,6003,i) //gate b active when i=1
{MemInst-a}=0; //disqualifies gate b of Abort' (to test gate d)
{PAbort}=i; //PAbort←i[15]
WCompare({Abort'},(not i)&1,6004,i) //gate d active when i=0,2
WCompare({LDisableMC1'},(7 rshift i)&1,6005,i) //gate b active when i=3
{PAbort}=0
]
//MemInst-a is not restored to 1 since the next test controls it
//Check the gate c of Abort' and gate a of LDisableMC1' (page 18)
//Gates a,b,c of Abort' are disqualified by MC2HoldIfSNE0=0, TypeLoaded'=0, PAbort=0
//Gates b and c of LDisableMC1' are disqualified by PAbort=0 and MC1TestH4Par=0
//{t6bus3: MC2Hold',MC1StartMC2,MemInst-a}
for i = 0 to 7 do
[
{t6bus3}=i; //MC2Hold'←i[13], MC1StartMC2←i[14], MemInst-a←i[15]
//MC2NotReady←i[13]' since MC2Hold'←i[13]' and MC2SynReady=1
WCompare({Abort'},(#367 rshift i)&1,6006,i) //gate b active when i=3
{PreloadMC1'}= not i; //PreloadMC1←i[15]
WCompare({LDisableMC1'},(#363 rshift i)&1,6007,i) //gate a active when i=3
]
//Check the gate c of LoadAd' (page 18)
{MC2Hold'}=0; //disqualify gate a of LoadAd'
//{t6bus4: PreloadMC1',PAbort,MC1StartMC2}
for i = 0 to 7 do
[
{t6bus4} = i xor 6; //PreloadMC1←i[13], PAbort←i[14]', MC1StartMC2←i[15]
EClock() //TypeLoaded←(PreloadMC1=i[13])
{PreloadMC1'}=1; //for PreloadMC1←0 to disqualify gate a of LDisableMC1'
//Gate c of LDisableMC1' is disqualified by MC1TestH4Par=0
//LDisableMC1' will =0 if i=4,5 (gate b control)
WCompare({LoadAd'},(#277 rshift i)&1,6008,i) //gate c active when i=6
]
{MC2Hold'}=1; {PreloadMC1'}=0; //restore to normal
//Check the SNE0 logic (page 81) via MC2WillGetR (page 20)
{MC2NeedsRIfSNE0}=1; //for gate f1a (page 20)
//ChkPhase0'=0 and CW[0:2]'=0 from SpeakTest to control ChkSyn logic
for i = 0 to 8 do
[
let a = #200 rshift i
{StorEcIn}=a
EClock() //i16 ff's (page 2),,b15 ff's (page 6)←(StorEcIn[0:7]=a)
//path established by ChkPhase0'=0
EClock() //clkSyndrome' is active since LoadSyndrome=1 from SpeakTest:
//CrctSyn[0:7]←(ChkSyn[0:7]=a (since CW[0:2]'=0))
WCompare({CrctSyn},a,6009,i)
//MC2WillGetR will = SNE0 since MC2NeedsRIfSNE0=1 and MC2NeedsR'=1
WCompare({MC2WillGetR},(#377 rshift i)&1,6010,i) //high until i=8
]
{MC2NeedsRIfSNE0}=0; //restore to normal for MC2WillGetR=0
//Check gates which are controlled by SNE0 (pages 18,20)
for i = 0 to 3 do //render SNE0 =1 when i=2,3
//render MC2HoldIfSNE0 =1 when i=0,2
//render MC2SynReady =0 when i=2
//render TypeLoaded =0
[
{StorEcIn.7} = i<<w.b14; //for SNE0←i[14]
EClock() //i16,,b15 ff's ←0, except Partial.7←(StorEcIn.7=i[14])
//MC2HasR'←(MC2WillGetR'=1)
EClock() //SNE0←i[14] since CrctSyn[0:7]←(ChkSyn[0:7]=0,0,0,0,0,0,0,i[14])
//TypeLoaded'←(LoadType'=0)
{MC2HoldIfSNE0} = not i; //MC2HoldIfSNE0←i[15]'
for j = 0 to 3 do
[
let k = (i lshift 2)%j //k = 4i+j
//Check the MC2WillGetR logic (page 20)
{MC2NeedsR'} = j<<w.b14
{MC2NeedsRIfSNE0} = not j; //MC2NeedsRIfSNE0←j[15]'
WCompare({MC2WillGetR},(#73463 rshift k)&1,6011,k)
//Check gate a of Abort' (page 18)
{MC2Hold'}=1; //disqualify gate c of Abort'
//Gate b of Abort' is diqualified by TypeLoaded'=0
{MC1StartMC2} = j<<w.b14
{MemInst-a}=j; //MemInst-a←i[15]
WCompare({Abort'},(#173777 rshift k)&1,6012,k) //gate a
//Check AdvancePipe' and the MC2SynReady signal (page 18)
//MC1StartMC2 still = j[14]
{MC2Hold'}=j; //MC2Hold'←j[15]
//MC2SynReady should =0 when k = #10-#13
WCompare({AdvancePipe'},(#77567 rshift k)&1,6013,k)
//Check the MC2NotReady signal via gate a of LDisableMC1' (page 18)
//gates b and c are disqualified by PAbort=0 and MC1TestH4Par=0
{MC1StartMC2}=1
//PreloadMC1=1 since PreloadMC1'=0 from SpeakTest
//MC2NotReady should =1 when k is even or = #11,#13
// since MC2Hold' =0 when k is even
// and MC2SynReady =0 when k = #10-#13
WCompare({LDisableMC1'},(#120252 rshift k)&1,6014,k) //gate a
]
]
//Check gate a of LoadAd' (page 18)
//Gate c of LoadAd' is disqualified by MC1StartMC2=1
//{t6bus6: PreloadMC1', PAbort,MC2Hold',MC2HoldIfSNE0}
for i = 0 to 15 do
[
{t6bus6} = i xor #10
EClock() //TypeLoaded←(PreloadMC1=i[12])
{PreloadMC1'}=1; //disable gate a of LDisableMC1', yielding contol to gate b
//LDisableMC1' should =0 when i>#13
//MC2SynReady should = i[15]'
WCompare({LoadAd'},(#175777 rshift i)&1,6015,i) //gate a
]
{PAbort}=0; {MC2HoldIfSNE0}=0; //restore to normal
//Check gates a and c of MC1Next.7' (page 16)
//{t6bus7: MC1TestFault,preMC1Next.7,MC1NeedsR, MC2NeedsR',MC1TestQWO,QWO}
for i = 0 to 14 do
[
{t6bus7}=i; //MC1TestFault←(i[10]=0) to disqualify gate d
//preMC1Next.7←(i[11]=0) to disqualify gate b
//MC1NeedsR←i[12]
//MC2WillGetR←i[13]' (controlled by MC2NeedsR' - page 20)
//MC1TestQWO←i[14]
//QWO←i[15] (emerges =0 from loop)
WCompare({MC1Next.7'},(#70167 rshift i)&1,6016,i) //gates a and c
]
]