//**************************************************************************************
//D0CS02.TST
//By B. Rosen and M. Thomson February 7, 1979
//Sub Test Program for D0 CS Module
//**************************************************************************************
get "d0cs.d"
external [ AnnounceFirstWrite ]
//Edge pin and test connector signal busses available to this sub-test:
//{CS-A': TrmCS-A.00'a,TrmCS-A.01'a,TrmCS-A.02'a, TrmCS-A.03'a,TrmCS-A.04'a,TrmCS-A.05'a, TrmCS-A.06'a,TrmCS-A.07'a,TrmCS-A.08'a, TrmCS-A.09'a,TrmCS-A.10'a,CS-A.11'}
//{R: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//**************************************************************************************
//Test 2: Test of Boot logic
let Test2() be
[
SpeakTest(2) //set initial conditions (see notes at end of D0CS.TST)
//J-TestResult'=1 from SpeakTest to force no branch
normalize() //bring clock up to beginning of cycle
for i = 0 to 1000 do if {BootOk} eq 1 then break; //wait out any leftover boot
CheckBoot("BootOk",{BootOk},1,"before I did anything",2000)
for i = 0 to 2 do ExtClock()
//EdgeClk should be 0, Cycle0, with ExtClock ready to cause lo to hi
{TesterBoot'} = 0; //Start the boot
{BootOkxxx} = 0
ExtClock() //give Boot 1shot a clock, clock BootOkxxx into Boot
CheckBoot("BootOk",{BootOk},0,"with TesterBoot'",2001)
//prom d4, pin 6 should go down because rom state is 0
// LoadBootROM() //loads the tester prom simulator
{TesterBoot'} = 1; //release boot button
{BootOkxxx} = 1; //let go of boot
EClock() //back to cycle 0, clear the boot
CheckBoot("Run",{RUN},0,"after Boot",2002) //EClock makes RUN go low
CheckBoot("F1ok",{F1ok},0,"after Boot",2003) //jam cleared off (erased by run/b=0)
//WaitForKey("State 0") //use this to see if rom starts out ok
TwoEClocks() //Boot Prom now at state #10
RxAPC()
//APC should be cleared by state 0
CheckBoot("APC",{R}ṡ,0,"after state #10",2004)
//Control Store Address sb APC (=0) by using Run' to jam force
//JC to return (=6), see page 6:7 for jam force, page 2 for select
CheckBoot("CS-A'",{CS-A'},#7777,"after state #10",2005)
//WaitForKey("State 10")
TwoEClocks() //State #12
//Fault is cleared by ResetErrors which is gated with run on page 10
CheckBoot("DelayedFault'",{DelayedFault'},1,"after Boot",2006)
//WaitForKey("State 12")
TwoEClocks() //State #14
//WaitForKey("State 14")
TwoEClocks() //State #16
if AnnounceFirstWrite then WaitForKey("*nJust before write high")
CheckBoot("WE-CS-High",{WE-CS-High},1,"in state #16",2007)
// for writing bits [0:15, 32:35]
for i = 0 to 3 do TwoEClocks() //advance to state #26
if AnnounceFirstWrite then WaitForKey("*nJust before write low (state #26)")
CheckBoot("WE-CS-Low",{WE-CS-Low},1,"in state #26",2008)
// for writing bits [16:31]
TwoEClocks() //State #10 hopefully
//APC should be incremented by BootWriteLowCS
CheckBoot("APC",{R}ṡ,1,"first time thru state #26",2009)
CheckBoot("CS-A'",{CS-A'},#7776,"first time thru state #26",2010)
//now that we got through the first round, do the others without most of the checking
for i = 1 to 1023 do //there are now 1024 instructions in the prom
[
let sb = ((iڤ) lshift 2) % (iM) //account for 16 pages of 64 words
//verify that address is correct in both APC and CS-A
CheckBoot("APC",{R}ṡ,sb,"in boot loop",2011,i)
CheckBoot("CS-A'",{CS-A'},sb xor #7777,"in boot loop",2012,i)
for j = 0 to 7 do TwoEClocks() //execute store cycle
]
//WaitForKey("TestPoint")
TwoEClocks() //Hopefully state #36
CheckBoot("APC",{R}ṡ,0,"after state #11",2013)
CheckBoot("Run",{RUN},0,"in state #36",2014) //one more clock required to raise RUN
CheckBoot("CS-A'",{CS-A'},#7777,"after state #11",2015)
]
and CheckBoot(ini,was,sb,fin,testno,drive; numargs na) be
[
if was eq sb then return
Ws(FORMATN("*nTest <D>: <S> was <B> should be <B> <S>",testno,ini,was,sb,fin))
if na gr 5 then Ws(FORMATN(", drive=<B>",drive))
Ws("*nWaiting... i-nitialize, s-cope loop, <sp>-return, c-lock")
let i = 64
let char = 0
looping = false
[
while Endofs(keys) do
if looping then
[
if i eq 64 then
[
StartBoot()
i = 0
]
TwoEClocks()
i = i + 1
]
char = Gets(keys)
switchon char into
[
case $c: looping = false;TwoEClocks();endcase
case $i: StartBoot();endcase
case $*s: looping = false;Ws("*nRunning...");return
case $s: looping = true;endcase
case $t: looping = false;ExtClock();endcase
]
] repeat
]
and StartBoot() be
[
normalize()
{TesterBoot'} = 0
{BootOkxxx} = 0
EClock()
{BootOkxxx} = 1
{TesterBoot'} = 1
EClock()
]