//**************************************************************************************
//ALU7.TST
//By F. Itami and M. Thomson October 6, l978
//Sub Test Program for D0 ALU Module
//**************************************************************************************
get "alu.d"
//Edge pin signal busses used by ALU module:
//{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15}
//{aluf: ALUF.0, ALUF.1,ALUF.2,ALUF.3}
//{clkbus: LT,LR, Abort',LoadMIR,Cycle0Feed'}
//{CTask: CTask.0, CTask.1,CTask.2,CTask.3}
//{F1F2: F1.0,F1.1, F1.2,F1.3,F2.0, F2.1,F2.2,F2.3}
//{H2: H2.08,H2.09, H2.10,H2.11,H2.12, H2.13,H2.14,H2.15}
//{MASK: MASK.00, MASK.01,MASK.02,MASK.03, MASK.04,MASK.05,MASK.06, MASK.07,MASK.08,MASK.09, MASK.10,MASK.11,MASK.12, MASK.13,MASK.14,MASK.15}
//{MC1SA: BSEL.0,BSEL.1, F1.0,F1.1,F1.2, F1.3,LR,LT}
//{mcbus: MC1WriteR, MC2AllowWrite,MC1NeedsR,MC2WillGetR}
//{mirbus: MemInst/d,MemInst/d', RMOD/d,RMOD/d',RSEL.0/d', RSEL.1/d',RSEL.2/d,RSEL.3/d, RSEL.4/d,RSEL4and5/d,RSEL.5/d}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//{TA: TA.0, TA.1,TA.2,TA.3}
//**************************************************************************************
//Test 18: Check the SALUF functions (pages 9,10,15)
// Check the R and T bypass logic (pages 5,6)
let Test18() be
[
SpeakTest(18) //set initial conditions (see notes at end of ALU.TST)
//{jbus: JC.1,JC.2,JA.7}
//{clkResultbus: FreezeResult, Breakpoint',Abort',DelayedFault'}
{Stkp←ALUA'}=1; //keep Stkp=0 during test for RA=0 when RSA,B=3,3
//Test the clkResult' signal qualifying terms (page 15)
//(they initially qualify clkResult' due to SpeakTest initialization)
EClock() //clkResult' sets SavALUOUT.00 since ALUOUT=#177777 from SpeakTest
{jbus}=2; //for J-TestResult'←SavALUOUT.00'
WCompare({J-TestResult'},0,18000) //SavALUOUT.00 =1
{MASK}=#177777; //for ALUOUT=(ALUA=0)
for i = 0 to 14 do //disqualify clkResult'
[
{clkResultbus} = i xor #10
ClockCycle1() //clkXCycle1' for d4 flip-flop (page 15)
EClock() //should be blocked from clkResult'
WCompare({J-TestResult'},0,18001,i) //SavALUOUT.00 stays=1
]
{DelayedFault'}=1; //qualify clkResult
ClockCycle1() //check that Cycle1 does not yield clkResult'
WCompare({J-TestResult'},0,18002) //SavALUOUT.00 stays=1
EClock() //clkResult: SavALUOUT.00←(ALUOUT.00=0)
WCompare({J-TestResult'},1,18003) //SavALUOUT.00 =0
//Check that the SALUF's (MA',MB,SALUF[0:5]) load and display correctly (pages 9,15)
{mirbus}=#1557; //MemInst=1, RMOD=1, RSEL=00 01 00
ClockMIR() //Load MIR: R←SALUF'←0
{SALUF←H2'}=0; //load SALUF's from H2[8:15] on Cycle1 clocks
{jbus}=7; //for J-TestResult'←MB'
for i = 0 to 8 do
[
let a = #200 rshift i
{F1F2}=a
EClock() //H2[8:15]←(F1F2=a)
ClockCycle1() //SALUF←(H2[8:15]=F1F2=a)
WCompare((not {rbus})Ź,a,18100+i) //rbus[8:15]←(MA',MB,SALUF[0:5])'
WCompare({J-TestResult'},(#775 rshift i)&1,18120+i) //J-TestResult'←(MB' =0 when i=1)
]
//note: SALUF's emerge =0 after above loop
//Check the Restore =1 path (R[0:3] ← i14 ff's ← ALUOUT[0:3]) (page 10)
{Restore'}=0; //for i14 ff's ← ALUOUT[0:3]
ClockCycle1() //d4h ff ← 0 (page 10) (i.e. Restore←1)
{BBFA'}=0; //for ALUB←MASK
{aluf}=0; //for ALUOUT←ALUB
EClock() //ALUF()←"T", set EnableMask, (i.e. ALUOUT←ALUB←MASK)
for i = 0 to 4 do
[
let a = #10000 lshift i
{MASK}=a
EClock() //clkResult': i14 ff's ← (ALUOUT[0:3] = 1 lshift i), H3P←(ALUOUT=a)
WCompare((not {rbus})𩠐,a,18200+i) //ALUOUT[0:3] via i14 ff's
]
//Load T and R files for SALUF tests
{clkbus}=#37; //LT=1, LR=1, Abort'=1, LoadMIR=1, Cycle0=0
{mirbus}=#1540; //MemInst=1, RMOD=1, RSEL=00 00 00
//for RSA,B←1,0: RA=(CTask[0:3]=0,,RSEL[2:3]=0,,PCF[1:2]=0)=0
//Write 0's into R and T files, address=0 (H3P=0 from previous loop)
EClock() //Load MIR, set TComing, TWPending, RComing, RWPending
//RSA,B←1,0: RA=(CTask[0:3]=0,,RSEL[2:3]=0,,PCF[1:2]=0)=0
RClock() //R(RA=0),T(TA=0 from SpeakTest) ← (R=H3P=0)
//Set up write data = -1
{MASK}=#177777
ClockCycle0() //H3P←(ALUOUT=ALUB=MASK= -1)
//Write -1 into R and T files, address = 1
{PCF.2}=1; //for RA=1
{TA.3}=1; //for TA=1
EClock() //RSA,B: RA=(CTask[0:3]=0,,RSEL[2:3]=0,,PCF[1:2]=1)=1
RClock() //R(RA=1),T(TA=1) ← (R=H3P=-1)
//Set up SALUF control of ALU
{clkbus}=#25; //LT=1, LR=0, Abort'=1, LoadMIR=0, Cycle0=0
{aluf}=15; //for ALUF()←SALUF
{MASK}=0; //for ALUA←(H1=R)
{BBFA'}=1; //for reset EnableMask (i.e. ALUB←H2)
//Test SALUF functions with ALUA=-1 and ALUB=-1 (i.e. H2'=0)
for i = 0 to 62 by 2 do
[
let sb = valof
[
if (not i<<w.b10)&1 xor i<<w.b12 then resultis -1
if (not i<<w.b10) & i<<w.b12 then resultis -2
resultis 0
]
{F1F2}=i
{BSEL.0}=0; //for H2←F1F2
ClockCycle0() //H2←F1F2, reset EnableMask
EClock() //SALUF←H2, RSA,B←1,0 (for RA←1), Restore←0
{BSEL.0}=1; //for H2←T
ClockCycle0() //H1←R(RA=1), H2←T(TA=1), ALUF()←SALUF
ClockCycle0() //H3P←(ALUOUT=sb)
WCompare({rbus},sb,18300,i) //H3P
]
//Test SALUF functions with ALUA=-1 and ALUB=0 (H2'=-1)
{TA.3}=0; //for TA=0
for i = 0 to 62 by 2 do
[
let sb = valof
[
if (not i<<w.b10)&1 xor i<<w.b11 then resultis -1
if (not i<<w.b10) & i<<w.b11 then resultis -2
resultis 0
]
{F1F2}=i
{BSEL.0}=0; //for H2←F1F2
ClockCycle0() //H2←F1F2
EClock() //SALUF←H2, RSA,B←1,0 (for RA←1)
{BSEL.0}=1; //for H2←T
ClockCycle0() //H1←R(RA=1), H2←T(TA=0), ALUF()←SALUF
ClockCycle0() //H3P←(ALUOUT=sb)
WCompare({rbus},sb,18310,i) //H3P
]
//Test SALUF functions with ALUA=0 and ALUB=-1 (H2'=0)
{TA.3}=1; //for TA=1
{PCF.2}=0; //for RA=0
for i = 0 to 62 by 2 do
[
let sb = valof
[
if i<<w.b10 xor i<<w.b13 then resultis -1
resultis 0
]
{F1F2}=i
{BSEL.0}=0; //for H2←F1F2
ClockCycle0() //H2←F1F2
EClock() //SALUF←H2, RSA,B←1,0 (for RA←0)
{BSEL.0}=1; //for H2←T
ClockCycle0() //H1←R(RA=0), H2←T(TA=1), ALUF()←SALUF
ClockCycle0() //H3P←(ALUOUT=sb)
WCompare({rbus},sb,18320,i) //H3P
]
//Test SALUF functions with ALUA=0 and ALUB=0 (H2'=-1)
{TA.3}=0; //for TA=0
for i = 0 to 62 by 2 do
[
let sb = valof
[
if i<<w.b10 xor i<<w.b14 then resultis -1
resultis 0
]
{F1F2}=i
{BSEL.0}=0; //for H2←F1F2
ClockCycle0() //H2←F1F2
EClock() //SALUF←H2, RSA,B←1,0 (for RA←0)
{BSEL.0}=1; //for H2←T
ClockCycle0() //H1←R(RA=0), H2←T(TA=0), ALUF()←SALUF
ClockCycle0() //H3P←(ALUOUT=sb)
WCompare({rbus},sb,18330,i) //H3P
]
//Test SALUF display, including Overflow, etc. (Restore=0) (pages 9,10)
//Test the R and T bypass logic (pages 5,6)
//Test the J-TestResult' mux inputs not tested elsewhere (page 10)
{clkbus}=#36; //LT=1, LR=1, Abort'=1, LoadMIR=1, Cycle0=1
{Restore'}=1; //for Restore=0 inputs to i14 ff's (page 10)
{SALUF←H2'}=1; //keep SALUF's=#076 for WCompares
ClockCycle1() //set TComing, TWPending, RComing, RWPending,
//d4h ff ← 1 (page 10) (i.e. Restore←0)
{aluf}=10; //for "R+T+1" (for first add only)
EClock() //ALUF()←"R+T+1", H1←(R=0), H2←(T=0)
{aluf}=9; //for "R+T" (for after first add, instead of "R+T+1")
//R and T bypass logic (H1←ALUOUT, H2←ALUOUT):
//R bypass: RA=WA since RA's have been =0 from all sources
{CTD=CTask}=1; //activate T bypass
for i = 0 to 14 do //walk a "1" from ALUOUT.15 to ALUOUT.01
[
{mirbus}=#1540; //for EnableR and R bypass logic
ClockCycle1() //load MIR, RSA,B←1,0
EClock() //H1,H2,H3P ← H1+H2+(Cin=1 on first pass only), RSA,B←2,5, clkResult'
//ALUF()←"R+T"
let a = 1 lshift i
WCompare({ALUA},a,18400+i) //H1[0:15]
WCompare({H2},aŹ,18420+i) //H2[8:15] only (partial check)
{Cycle0Feed'}=1; //rbus←H3P
WCompare({rbus},a,18440+i) //H3P[0:15] (if stop, probe H2[0:7])
{mirbus}=#1557; //for R←SALUF'
EClock() //load MIR, RSA,B←3,3
{Cycle0Feed'}=0; //rbus←SALUF
//rbus' = ALUOUT.00=0,ALUCyOut=0,ALUOUT=0'=1,ALU(OVER)'=1,,0,0,0,0,,SALUF's=#076
WCompare(not {rbus},#30076,18460+i)
]
{mirbus}=#1540; //for EnableR and R bypass logic
ClockCycle1() //load MIR and RSA,B←1,0
EClock() //H1,H2,H3P ← H1+H2, RSA,B←2,5, clkResult' (#40000+#40000=#100000)
WCompare({ALUA},#100000,18500) //H1[0:15]
{Cycle0Feed'}=1; //rbus←H3P
WCompare({rbus},#100000,18501) //H3P[0:15] (if stop, probe H2[0:7])
{mirbus}=#1557; //for R←SALUF
EClock() //load MIR, RSA,B←3,3
{Cycle0Feed'}=0; //rbus←SALUF'
//rbus' = ALUOUT.00=1,ALUCyOut=0,ALUOUT=0'=1,ALU(OVER)'=0,,0,0,0,0,,SALUF's=#076
WCompare(not {rbus},#120076,18502)
{jbus}=0
WCompare({J-TestResult'},0,18503) //SavALUOUT=0' =1 (ALUOUT#0)
{jbus}=4
WCompare({J-TestResult'},0,18504) //H1.00 =1
{mirbus}=#1540; //for EnableR and R bypass logic
ClockCycle1() //load MIR and RSA,B←1,0
EClock() //H1,H2,H3P ← H1+H2, RSA,B←2,5, clkResult' (#100000+#100000=0)
{mirbus}=#1557; //for R←SALUF
{IOAttn'}=1
ClockCycle1() //load MIR, c16g ff ← (IOAttn'=1) (page 10)
//rbus' = ALUOUT.00=0,ALUCyOut=1,ALUOUT=0'=0,ALU(OVER)'=0,,0,0,0,0,,SALUF's=#076
WCompare(not {rbus},#40076,18510)
{jbus}=0
WCompare({J-TestResult'},1,18511) //SavALUOUT=0' =0 (ALUOUT=0)
{jbus}=4
WCompare({J-TestResult'},1,18512) //H1.00 =0
{jbus}=5
WCompare({J-TestResult'},1,18513) //H1.15 =0
{jbus}=6
WCompare({J-TestResult'},0,18514) //IOAttn =0
{IOAttn'}=0
EClock(); //H1.15←(R.15=SALUF.5'=1), c16g ff ← (IOAttn'=0) (page 10)
{jbus}=5
WCompare({J-TestResult'},0,18520) //H1.15 =1
{jbus}=6
WCompare({J-TestResult'},1,18521) //IOAttn =1
]