//**************************************************************************************
//ALU6.TST
//By F. Itami and M. Thomson January 23, 1979
//Sub Test Program for D0 ALU Module
//**************************************************************************************
get "alu.d"
//Edge pin signal busses used by ALU module:
//{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15}
//{aluf: ALUF.0, ALUF.1,ALUF.2,ALUF.3}
//{clkbus: LT,LR, Abort',LoadMIR,Cycle0Feed'}
//{CTask: CTask.0, CTask.1,CTask.2,CTask.3}
//{F1F2: F1.0,F1.1, F1.2,F1.3,F2.0, F2.1,F2.2,F2.3}
//{H2: H2.08,H2.09, H2.10,H2.11,H2.12, H2.13,H2.14,H2.15}
//{MASK: MASK.00, MASK.01,MASK.02,MASK.03, MASK.04,MASK.05,MASK.06, MASK.07,MASK.08,MASK.09, MASK.10,MASK.11,MASK.12, MASK.13,MASK.14,MASK.15}
//{MC1SA: BSEL.0,BSEL.1, F1.0,F1.1,F1.2, F1.3,LR,LT}
//{mcbus: MC1WriteR, MC2AllowWrite,MC1NeedsR,MC2WillGetR}
//{mirbus: MemInst/d,MemInst/d', RMOD/d,RMOD/d',RSEL.0/d', RSEL.1/d',RSEL.2/d,RSEL.3/d, RSEL.4/d,RSEL4and5/d,RSEL.5/d}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//{TA: TA.0, TA.1,TA.2,TA.3}
//**************************************************************************************
//Test 17: Check the R file addressing logic (pages 13,14)
// Check the MC1Ad←Stkp logic (pages 11,20)
// Check that MC2XferWord=0 blocks RSA.1←1 and RSB.2←1 when MC2WillGetR=1 (page 13)
let Test17() be
[
SpeakTest(17) //set initial conditions (see notes at end of ALU.TST)
//Write all R locations with their own addresses as data
{ALUF.2}=1; //for prom f2 address = xxxx x1x0 and output = 1111 (page 16)
//to keep MC1XferWord=1, and MC2XferWord=1 for Suspend control
{Stkp←ALUA'}=1; //keep Stkp=0
{MemInst/d}=1; //enable b13 prom (page 11) for MC1Ad←Stkp+0 when SRC/DEST=0 (i.e. when i=0)
{mcbus}=#12; //write into R (address from MC1Ad)
ClockMIR() //MemInst←1, Suspend←1, RSA,B←4,6
for i = 0 to 255 do
[
{MC1SA}=i
{rbus}=i
ClockAd() //MC1Ad←i
RClock()
EClock() //clear EnMapRow (avoid StorA bus conflict)
]
{rbus}=###
{MC1WriteR}=0
//Test MC1Ad (RSA,B=4,6) and MC2Ad (RSA,B=6,7) inputs to RA's
//Stkp, RASAVE, and WA remain = 0 since Suspend = 1
{MC1SA}=0
ClockAd() //MC1Ad←0's
ClockMC2() //MC2Ad←(MC1Ad=0)
for i = 0 to 8 do
[
let a = #200 rshift i
let b = #400 rshift i
{MC1SA}=a
ClockAd() //RSA,B←4,6(MC1Ad), MC1Ad←a
WCompare({rbus},a,17000+i) //rbus=RA=MC1Ad
{MC2WillGetR}=1
EClock() //RSA,B←6,7(MC2Ad)
//MC1Ad[4:7] increments since MC1HasR=1
WCompare({rbus},bŹ,17020+i) //rbus=RA=MC2Ad
{MC2WillGetR}=0
ClockAd() //restore MC1Ad=a
ClockMC2() //MC2Ad←(MC1Ad=a)
//the sequence above assures MC1Ad not = MC2Ad when tested
]
//Test Stkp (RSA,B=3,3) and WA (RSA,B=2,5) inputs to RA's
//MC1Ad=MC2Ad=Stkp=RASAVE=WA=0 from previous steps
{mcbus}=0; //initialize memory control
EClock() //reset Suspend
for i = 0 to 8 do
[
let a = #1200 rshift i
let b = #2400 rshift i
{mirbus}=#1537; //MemInst=0, RMOD=1, RSEL=01 11 11
{Stkp←ALUA'}=1
ClockMIR() //RSA,B←3,3(Stkp), open rbus, don't Stkp←ALUA
{Stkp←ALUA'}=0
{rbus}=a
EClock() //H1←(rbus=a), RASAVE←(RA=Stkp)
{rbus}=###
{mirbus}=#1407; //MemInst=0, RMOD=1, RSEL=11 00 11
ClockMIR() //RSA,B←3,3(Stkp), rbus←R, Stkp←(ALUA=a),
//WA←(RASAVE = prior Stkp)
WCompare({rbus},aŹ,17040+i) //rbus=RA=Stkp
EClock() //RSA,B←2,5(WA)
WCompare({rbus},bŹ,17060+i) //rbus=RA=WA
]
{Stkp←ALUA'}=1; //keep Stkp=2 for later in test
//Test RSA,B=0,0 (when i = 2,3) and RSA,B=1,0 (when i not = 2,3)
//{racon1: CTask.0,CTask.1, RSEL.0/d',RSEL.1/d',RSEL.2/d, RSEL.3/d,PCF.1,PCF.2}
{mirbus}=#1540; //MemInst=0, RMOD=1, RSEL=00 00 00
for i = 0 to 8 do
[
let a = #200 rshift i
{racon1} = a xor #60
ClockMIR() //RSEL[0:3]←RSEL[0:3]/d, RSA←0 or 1, RSB←1, rbus←R
WCompare({rbus},a,17080+i) //rbus=RA={racon1}
]
//Test RSA,B=1,1
//{racon2: CTask.0,CTask.1, CTask.2,CTask.3,RSEL.2/d, RSEL.3/d,SBX.0,SBX.1}
{mirbus}=#1541; //MemInst=0, RMOD=1, RSEL=00 00 01
for i = 0 to 8 do
[
let a = #200 rshift i
{racon2}=a
ClockMIR() //RSEL[2:3]←RSEL[2:3]/d, RSA,B←1,1, rbus←R
WCompare({rbus},a,17100+i) //rbus=RA={racon2}
]
//Test RSA,B=1,2
//{racon3: RSEL.2/d, RSEL.3/d,DBX.0,DBX.1}
{mirbus}=#1544; //MemInst=0, RMOD=1, RSEL=00 00 10
for i = 0 to 4 do
[
let a = #10 rshift i
{racon3}=a
ClockMIR() //RSEL[2:3]←RSEL[2:3]/d, RSA,B←1,2, rbus←R
WCompare({rbus},a,17120+i) //rbus=RA = (CTask[0:3]=0),,{racon3}
]
//Test RSA,B=1,4
//{racon4: RSEL.2/d, RSEL.3/d,RSEL.4/d,RSEL.5/d}
{mirbus}=#1340; //MemInst=0, RMOD=0, RSEL=00 00 00
for i = 0 to 4 do
[
let a = #10 rshift i
{racon4}=a
ClockMIR() //RSEL[2:5]←RSEL[2:5]/d, RSA,B←1,4, rbus←R
WCompare({rbus},a,17140+i) //rbus=RA = (CTask[0:3]=0),,{racon4}
]
//Test RSA,B=0,4 using MemInst=1
{mirbus}=#2537; //MemInst=1, RMOD=1, RSEL=01 11 11
ClockMIR() //RSEL[0:5]←(RSEL[0:5]/d=#37), RSA,B←0,4, rbus←R
WCompare({rbus},#37,17200) //rbus=RA=(CTask[0:1]=0),,(RSEL[0:4]=#17),,(RAD7= RSEL.5 =1)
{mirbus}=#2440; //MemInst=1, RMOD=1, RSEL=10 00 00
ClockMIR() //RSEL[0:5]←(RSEL[0:5]/d=#40)
EClock() //set the i1 flip-flop (page 14), RSA,B←0,4, rbus←R
WCompare({rbus},#41,17201) //rbus=RA=(CTask[0:1]=0),,(RSEL[0:4]=#20),,(RAD7= i1 ff =1)
//Test the MC1Ad←(Stkp+count) logic controlled by the b13 prom (page 11)
//Prior logic established: MemInst=1, SRC/DEST=0, Stkp=2, MC1XferWord=1
let t17aval = table [ 2;2;2;2; 3;3;2;3; 2;1;2;2; 2;2;2;2 ]
{MC1NeedsR}=1; //for RA←MC1Ad
for i = 0 to 15 do
[
{aluf}=i; //b13 prom address (count control)
ClockAd() //MC1Ad←(Stkp+count), RSA,B←4,6(RA←MC1Ad), Suspend←1
//can MC1XferWord←0 when ALUF.2 not =1
WCompare({rbus},t17aval!i,17300+i) //rbus=MC1Ad; prom b13 changed by rev. E
EClock() //EnMapRow←0 (avoid StorA bus conflict)
//Restore MC1XferWord to 1 for Suspend←(MC1NeedsR=1)
{ALUF.2}=1; //for prom f2 address = xxxx x1x0 and output = 1111 (page 16)
ClockAd() //MC1XferWord←1
EClock() //EnMapRow←0 (avoid StorA bus conflict)
]
//Test the MC1Ad←Stkp path (SRC/DEST=0) (page 20)
//Check that all values of Stkp[0:3] load MC1Ad[0:3] correctly
//Check that the b11 ALU (page 20) loads MC1Ad[4:7] properly,
//Using all values of Stkp[4:7] counted by 0, then +1, then -1 (controlled by prom b13)
//Prior logic established: MemInst=1, SRC/DEST=0, (Stkp=2)
let t17bval = table [ 0;4; 9 ]
let t17cval = table [ 0;1;-1 ]
{MC1NeedsR}=0
{mirbus}=#1537; //MemInst=0, RMOD=1, RSEL=01 11 11
ClockMIR() //load MIR, open rbus, Suspend←0
{Stkp←ALUA'}=0
//SRC/DEST=0' =0 since {MC1SA} still =0
for i = 0 to 2 do
[
for j = 0 to 15 do
[
let a = j lshift 4; //bits [0:3] of result and Stkp[0:3] input
let b = (j + t17cval!i) //bits [4:7] of result
{ALUF.2}=1; //for prom f2 address = xxxx x1x0 and output = 1111 (page 16)
{rbus} = a % j
ClockAd() //H1←(rbus=a % j), MC1XferWord←1 (for Suspend control)
{rbus}=###
{MemInst/d}=1; //for enable prom b13 (page 11)
ClockMIR() //MemInst←1, Stkp←(ALUA=H1 = a % j)
//EnMapRow←0 (avoid StorA bus conflict)
{aluf}=t17bval!i; //prom b13 address (count control)
{MC1NeedsR}=1; //for Suspend←1 (MC1XferWord=1)
ClockAd() //MC1Ad←(Stkp+count, i.e. a % b), RSA,B←4,6(RA←MC1Ad)
//Suspend←1, (MC1XferWord can reset since {aluf} = 0;4;9)
WCompare({rbus},a % b,17400+i,j) //rbus=RA=MC1Ad
{MemInst/d}=0
{MC1NeedsR}=0
ClockMIR() //MemInst←0, Suspend←0, open rbus
//EnMapRow←0 (avoid StorA bus conflict)
//Stkp stays = a % j since Suspend=0 (for next test)
]
]
//Check that MC2XferWord=0 blocks RSA.1←1 and RSB.2←1 when MC2WillGetR=1 (page 13)
//Set up prom f2 address = 1100 0000 for output = 0001 (page 16)
{rbus}=#177777
EClock() //H1←(rbus=#177777). H2←(F1F2=0)
{aluf}=0
//SRC/DEST=0' =0 since {MC1SA} still =0
//Set up MC2XferWord=0 for control; set up MC2Ad=#377 for failure data
ClockAd() //MC1XferWord←0 (since prom f2 output = 0001)
//MC1Ad←((Stkp+0)=#377 - from prior logic)
ClockMC2() //MC2XferWord←MC1XferWord=0)
//MC2Ad←(MC1Ad=#377)
WCompare({MC2XferWord},0,17500)
//Set up Stkp=#45 for failure data
{MASK}=#332
{rbus}=###
ClockCycle1() //Stkp←(ALUA=(H1 & MASK')=#45)
//Set up RSA,B=1,2 for RA = (CTask[0:3]=0),,(RSEL[2:3]=0),,(DBX[0:1]=0)
//CTask[0:3]=0 and DBX[0:1]=0 from prior logic
{mirbus}=#1544; //MemInst=0, RMOD=1, RSEL=00 00 10
{MC2WillGetR}=1; //should have no effect unless faults exist
ClockMIR() //RSEL[2:3]←(RSEL[2:3]=0), rbus←R
//RSA,B←1,2 unless these faults exist:
// (1) RSA,B←3,x if pin c15.3 (page 13) is not blocking RSA.1/d
// hence, RA[0:3]←(Stkp[0:3]=2) (#4x in display)
// (2) RSA,B←x,3 if pin d11.6 (page 13) is not blocking RSB.2/d
// hence, RA[4:7]←(Stkp[4:7]=5) (#x5 in display)
// (3) RSA,B←6,7 if J revision is not installed
// hence, RA[0:7]←(MC2Ad[0:7]=#377)
WCompare({rbus},0,17501) //see notes (1), (2), (3) above
]