//**************************************************************************************
//ALU4.TST
//By F. Itami and M. Thomson January 23, 1979
//By Frank Vest February 17, 1981
// To run A-2 rev. g proms---- test 12000 and 12001 will fail with rev. h proms.
//Sub Test Program for D0 ALU Module
//**************************************************************************************
get "alu.d"
//Edge pin signal busses used by ALU module:
//{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15}
//{aluf: ALUF.0, ALUF.1,ALUF.2,ALUF.3}
//{clkbus: LT,LR, Abort',LoadMIR,Cycle0Feed'}
//{CTask: CTask.0, CTask.1,CTask.2,CTask.3}
//{F1F2: F1.0,F1.1, F1.2,F1.3,F2.0, F2.1,F2.2,F2.3}
//{H2: H2.08,H2.09, H2.10,H2.11,H2.12, H2.13,H2.14,H2.15}
//{MASK: MASK.00, MASK.01,MASK.02,MASK.03, MASK.04,MASK.05,MASK.06, MASK.07,MASK.08,MASK.09, MASK.10,MASK.11,MASK.12, MASK.13,MASK.14,MASK.15}
//{MC1SA: BSEL.0,BSEL.1, F1.0,F1.1,F1.2, F1.3,LR,LT}
//{mcbus: MC1WriteR, MC2AllowWrite,MC1NeedsR,MC2WillGetR}
//{mirbus: MemInst/d,MemInst/d', RMOD/d,RMOD/d',RSEL.0/d', RSEL.1/d',RSEL.2/d,RSEL.3/d, RSEL.4/d,RSEL4and5/d,RSEL.5/d}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//{TA: TA.0, TA.1,TA.2,TA.3}
//**************************************************************************************
//Test 12: Test the Stkp and SStkp load logic (page 11)
// Test the Stkp decode prom (a2 - page 11)
// Test the RA=WA comparators (page 12)
let Test12() be
[
SpeakTest(12) //set initial conditions (see notes at end of ALU.TST)
//H1=#177777 from SpeakTest (Cycle1 clocks do not change it)
//PART 1: Check SStkp←Stkp←ALUA←MASKER←CYCLER←H1, rbus←SStkp,,Stkp', and the Stkp decode prom
//Set up rbus←SStkp,,Stkp' display and cause RSA,B←3,3 (Stkp) on Cycle1 clocks
{mirbus}=#1547; //MemInst=0, RMOD=1, RSEL=00 00 11
ClockMIR() //rbus←SStkp,,Stkp'
for i = 0 to 255 do
[
{MASK} = not i
ClockCycle1() //Stkp←(ALUA=((H1=#177777)&MASK')=i)
ClockCycle1() //SStkp←(Stkp=i)
WCompare({rbus} xor #377,(i lshift 8) % i,12000,i) //SStkp=i,,Stkp'=i'
//Check the Stkp decode prom (a2 - page 11) - installed by rev. M
WCompare({StackEmpty},(#100001 rshift i)&1,12001,i)
WCompare({StackBadNow'},(not (#100000 rshift i))&1,12002,i)
]
//PART 2: Check the RA=WA comparators
//{ra=wa: RA=WAb,RA=WAa} //RA=WAa compares bits [4:7]
//SpeakTest initialized the following: WA=RASAVE=0
//PART 1 leaves the following: H1=#177777, mirbus=#1547
{MASK}=#177777
ClockCycle1() //Stkp←(ALUA=0), WA←(RASAVE=0), RSA,B←3,3 (Stkp)
WCompare({ra=wa},3,12100) //check equality: 0's=0's
for i = 0 to 3 do //single "1" in field of 0's (in each hex digit)
[
{MASK}=#7567 rshift i
ClockCycle1() //Stkp←(#210 rshift i), WA←(RASAVE=0), RSA,B←3,3 (Stkp)
WCompare({ra=wa},0,12110+i) //check inequality
]
//Change WA to #377
{MASK}=0
{mirbus}=#1537; //MemInst=0, RMOD=1, RSEL=01 11 11)
ClockMIR() //Stkp←(ALUA=H1=#177777), RSA,B←3,3 (Stkp), open rbus
{rbus}=#177777
EClock() //RASAVE←(RA=Stkp=#377), H1←(rbus=#177777), (RSA,B←2,5 - don't care)
{rbus}=###
ClockCycle1() //WA←(RASAVE=#377), RSA,B←3,3 (Stkp)
WCompare({ra=wa},3,12200) //check equality: #377=#377
for i = 0 to 3 do //single "0" in field of 1's (in each hex digit)
[
{MASK}=#210 rshift i
ClockCycle1() //Stkp←not(#210 rshift i), WA←(RASAVE=#377)
WCompare({ra=wa},0,12210+i) //check inequality
]
]
//**************************************************************************************
//Test 13: Check the Stkp counting logic controlled by the b14 prom (page 11,12)
and Test13() be
[
SpeakTest(13) //set initial conditions (see notes at end of ALU.TST)
//Stackpointer Modification Table (when MemInst=0, RMOD=1, RSEL=11 xx 11)
// RSEL.2,3 StackShift'=1 StackShift'=0
// 0 0 +2
// 1 +1 +3
// 2 -1 0
// 3 -2 -3
//Set up initial conditions, check clkSStkp' and ClkXCycle1'
{mirbus}=#1547; //MemInst=0, RMOD=1, RSEL=00 00 11
ClockMIR() //rbus←SStkp,,Stkp', RSA,B←3,3(Stkp)
//SStkp←(Stkp=0 from SpeakTest)
//Stkp←(ALUA=#177777 from SpeakTest)
//Set up RASAVE=#377 for remainder of test (for RA=WAa checks)
//Check that a Cycle0 clock does not change SStkp or Stkp
{MASK}=#177777; //for ALUA=0
EClock() //RASAVE←(RA=Stkp=#377) (stays =#377 since no more Cycle0 clocks)
//don't SStkp←(Stkp=#377) (clkSStkp' is inactive if rev. K is installed)
//don't Stkp←(ALUA=0) (clkXCycle1' is inactive)
WCompare({rbus},0,13000) //SStkp=0,,Stkp'=0 (fails if rev. K not installed)
//Set up SStkp=#377 for remainder of test, initialize Stkp=0
ClockCycle1() //SStkp←(Stkp=#377), Stkp←(ALUA=0)
{NewInst}=0; //keep SStkp=#377 for rbus display convenience
{Stkp←ALUA'}=1; //switch to count logic
//Check mirbus=#1547 case before proceding with test
//Check that NewInst=0 inhibits clkSStkp'
ClockCycle1() //WA←(RASAVE=#377), RSA,B←3,3 (Stkp)
//don't SStkp←(Stkp=0) (Stays =#377 since NewInst=0)
//Stkp←(Stkp=0)+0 (counting logic is active)
WCompare(not {rbus},0,13001) //SStkp'=0,,Stkp=0 (note {rbus} inversion)
WCompare({RA=WAa},0,13002) //Stkp[4:7] not = WA[4:7]
//Test the 248 cases where Stkp←Stkp+0; WA←RASAVE since signal WA←preStkp =0
//{promb14bus: RMOD/d',RSEL.0/d', RSEL.1/d',RSEL.4/d,RSEL.5/d, RSEL.2/d,RSEL.3/d,StackShift'}
for i = 0 to 247 do
[
{promb14bus} = i xor #340
ClockMIR() //(Stkp←Stkp+0 from mirbus=#1547)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+0 from promb14bus=i
//WA←(RASAVE=#377), RSA,B←3,3(Stkp)
WCompare(not {rbus},0,13010,i) //Stkp=0
WCompare({RA=WAa},0,13011,i) //Stkp[4:7] not = WA[4:7]
]
//repeat
//Test the 2 cases where Stkp←Stkp+0; WA[4:7]←Stkp[4:7]/d since signal WA←preStkp =1
{StackShift'}=0
{mirbus}=#1427; //RSEL.2,3 = 2
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+0, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},0,13020)
WCompare({RA=WAa},1,13021)
{StackShift'}=1
{mirbus}=#1407; //RSEL.2,3 = 0
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+0, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},0,13030)
WCompare({RA=WAa},1,13031)
//Test the 6 cases where Stkp counts; WA[4:7]←Stkp[4:7]/d since signal WA←preStkp =1)
//Check Stkp +1
//{StackShift'}=1
for i = 1 to 16 do
[
{mirbus}=#1417; //RSEL.2,3 = 1
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+1, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},i,13100,i)
WCompare({RA=WAa},1,13101,i)
]
//Check Stkp -1
//{StackShift'}=1
for i = 1 to 16 do
[
{mirbus}=#1427; //RSEL.2,3 = 2
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp-1, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},16-i,13110,i)
WCompare({RA=WAa},1,13111,i)
]
//Check Stkp +2
{StackShift'}=0
for i = 1 to 8 do
[
{mirbus}=#1407; //RSEL.2,3 = 0
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+2, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},(2*i),13120,i)
WCompare({RA=WAa},1,13121,i)
]
//Check Stkp -2
{StackShift'}=1
for i = 1 to 8 do
[
{mirbus}=#1437; //RSEL.2,3 = 3
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp-2, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},16-2*i,13130,i)
WCompare({RA=WAa},1,13131,i)
]
//Check Stkp +3
{StackShift'}=0
for i = 1 to 5 do
[
{mirbus}=#1417; //RSEL.2,3 = 1
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp+3, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},3*i,13140,i)
WCompare({RA=WAa},1,13141,i)
]
//Check Stkp -3
//{StackShift'}=0
for i = 1 to 5 do
[
{mirbus}=#1437; //RSEL.2,3 = 3
ClockMIR(); //(Stkp←Stkp+0)
{mirbus}=#1547; //R←SStkp,Stkp'
ClockMIR(); //Stkp←Stkp-3, WA[4:7]←Stkp[4:7]/d
WCompare(not {rbus},15-3*i,13150,i)
WCompare({RA=WAa},1,13151,i)
]
]