//**************************************************************************************
//ALU.TST
//By F. Itami and M. Thomson April 24, 1979
//Main Test Program for UTFP Controller Module
//**************************************************************************************
//NOTE: This test is for rev. M S/W or Etch #1 boards and rev. B Etch #2 boards.
// (See below for prom revisions.)
//**************************************************************************************
//CURRENT PROM REVISION: key: StitchWeld(Etch#1/Etch#2)
// Rev. F: a2(u"SP3"/u162)
// Rev. F or E: b2(u122/u84), b13(u84/u113)
// Rev. F or E or D: b14(u129/u114), d5(u69/u50), f2(u86/u7)
//**************************************************************************************
//DUMP FILES in ifs-2 under <Thomson>:
//D0ALU-M.DMTESTS contains
// alu*.tst, alu.d, alu.bp, alu.run, alu*.cm, aluall.cm1, aluall.cm2
//The next two dump files permit modification of the tests
//ALUTESTAUX-M.DM contains
// alu*.br, alu*.bt, alu.bs, alu.syms
//TEST.DM contains
// BCPL.RUN, BLDR.RUN, TC.RUN, format.br, testfns,br, SYS.BK, STREAMS.D
// (tester.d and testdefs.d are not used; alu.d contains their information)
//**************************************************************************************
//INSTALL THE FOLLOWING TEST CLIPS:
//Tester socket "B" to the following (STITCH-WELD boards only)
// 14-pin clip to b6
// EnableR: b6.6,1
// 14-pin clip to d7
// clkH3P': d7.12,2
// 14-pin clip to c7
// RWriteStrobe': c7.11,3
// TWriteStrobe': c7.6,4
// 14-pin clip to d10
// RA=WAa: d10.12,5
// RA=WAb: d10.10,6
//Tester socket "B" to the following (ETCH #1 boards only)
// 14-pin clip to u95
// EnableR: u95.2,1
// 14-pin clip to u63
// clkH3P': u63.6,2
// 14-pin clip to u76
// RWriteStrobe': u76.8,3
// TWriteStrobe': u76.11,4
// 14-pin clip to u7
// RA=WAa: u7.4,5
// RA=WAb: u7.2,6
//Tester socket "B" to the following (ETCH #2 boards only)
// 14-pin clip to u19
// EnableR: u19.8,1
// 14-pin clip to u66
// clkH3P': u66.6,2
// 14-pin clip to u79
// RWriteStrobe': u79.6,3
// TWriteStrobe': u79.3,4
// 14-pin clip to u54
// RA=WAa: u54.1,5
// RA=WAb: u54.2,6
//**************************************************************************************
get "alu.d"
static
[
pass = 0
otime = 0
exectime = 0
]
//Edge pin signal busses used by ALU module:
//{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15}
//{aluf: ALUF.0, ALUF.1,ALUF.2,ALUF.3}
//{clkbus: LT,LR, Abort',LoadMIR,Cycle0Feed'}
//{CTask: CTask.0, CTask.1,CTask.2,CTask.3}
//{F1F2: F1.0,F1.1, F1.2,F1.3,F2.0, F2.1,F2.2,F2.3}
//{H2: H2.08,H2.09, H2.10,H2.11,H2.12, H2.13,H2.14,H2.15}
//{MASK: MASK.00, MASK.01,MASK.02,MASK.03, MASK.04,MASK.05,MASK.06, MASK.07,MASK.08,MASK.09, MASK.10,MASK.11,MASK.12, MASK.13,MASK.14,MASK.15}
//{MC1SA: BSEL.0,BSEL.1, F1.0,F1.1,F1.2, F1.3,LR,LT}
//{mcbus: MC1WriteR, MC2AllowWrite,MC1NeedsR,MC2WillGetR}
//{mirbus: MemInst/d,MemInst/d', RMOD/d,RMOD/d',RSEL.0/d', RSEL.1/d',RSEL.2/d,RSEL.3/d, RSEL.4/d,RSEL4and5/d,RSEL.5/d}
//{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15}
//{TA: TA.0, TA.1,TA.2,TA.3}
//**************************************************************************************
//Main program for ALU module test
let main() be
[
pass = pass+1
Test1()
Test2()
Test3()
Test4()
Test5()
Test6()
Test7()
Test8()
Test9()
Test10()
Test11()
Test12()
Test13()
Test14()
Test15()
Test16()
Test17()
Test18()
Test19()
Test20()
Test21()
Test22()
Test23()
Test24()
] repeat
//**************************************************************************************
//Routines available for ALU module tests
//16-bit Left-Cyclic-Shift routine
and LCyc(wrd,amount)= valof
[
resultis((wrd lshift amount)%(wrd rshift (16-amount)))
]
//Wait-Comparison routine
and WCompare(was,sb,testno,drive; numargs na) be
[
if was eq sb then return
Ws(FORMATN("*nTest <D>: Was = <B>, Should be = <B>",testno,was,sb))
if na gr 3 then Ws(FORMATN(", drive = <B>",drive))
while Endofs(keys) do [ ]
Gets(keys)
Ws("*nRunning...")
]
//**************************************************************************************
//Clocking routines defined on page 15
and ClockAd() be
[
let a = {LoadAd'}
{LoadAd'}=0
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
{LoadAd'}=a
]
and ClockCycle0() be
[
let a = {Cycle0Feed'}
{Cycle0Feed'}=0
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
{Cycle0Feed'}=a
]
and ClockCycle1() be
[
let a = {Cycle0Feed'}
{Cycle0Feed'}=1
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
{Cycle0Feed'}=a
]
and ClockMC2() be
[
let a = {AdvancePipe'}
{AdvancePipe'}=0
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
{AdvancePipe'}=a
]
and ClockMIR() be
[
let a = {clkbus}
{LoadMIR}=1
{Cycle0Feed'}=1
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
{clkbus}=a
]
and EClock() be //EdgeClockFeed' is normally high
[
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1
]
and RClock() be //RamClockFeed' is normally high
[
{RamClockFeed'}=0
{RamClockFeed'}=1
]
//**************************************************************************************
and SpeakTest(testno) be
[
//Calculate the execution time for each test
let tv=vec 2
Timer(tv)
exectime = tv!1 - otime
otime = tv!1
Ws(FORMATN("*nExection Time for this test is <D> msec.",exectime))
//Set up the title display
Ws("*n")
Ws("*n")
Ws(FORMATN("*nALU TEST (rev. M): Pass <D>, Test <D>...",pass,testno))
//Set up initial clock condition
{RamClockFeed'}=1
{EdgeClockFeed'}=1
{RUN}=1
//Set up misc. initial conditions
{rbus}=###
//{miscbus0: CTD=CTask, DBX.0,DBX.1,FreezeResult, JA.7,JC.1,JC.2, MC2HoldIfSNE0,PCF.1,PCF.2, Refresh',RPByte0In,RPByte1In, SBX.0,SBX.1,Stkp←ALUA'}
{miscbus0}=0
//{CYCOUNT: CYCOUNT.0, CYCOUNT.1,CYCOUNT.2,CYCOUNT.3}
{CYCOUNT}=0
//{NCYCOUNT: CYCOUNT.0', CYCOUNT.1',CYCOUNT.2',CYCOUNT.3'}
{NCYCOUNT}=#17
{BSEL.0}=0
{BSEL.1}=0; //H2←F1F2 (down-aligned)
{CTask}=0
{F1F2}=0
{mcbus}=0
{mirbus}=#1537
{TA}=0; //T file address = 0
{clkbus}=#27; //LT=1, LR=0, Abort'=1, LoadMIR=1, Cycle0=0
{aluf}=3; //for prom f2 address = xxxx x1x0 and outputs = 1111 (page 16)
{LoadAd'}=0; //for MC1XferWord←1, MC1XWdly←1
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1; //load MIR with MemInst=0, RMOD=1, RSEL=01 11 11 for R←NBR (i.e. open Cycle0 R bus sources), Suspend←0, AbortDly'←1, MC1XferWord←1, MC1XWdly←1
{clkbus}=#24; //LT=1, LR=0, Abort'=1, LoadMIR=0, Cycle0=1
{ALUF.2}=0; //makes {aluf}=1 for ALUOUT←ALUA.IN
{LoadAd'}=1; //de-activate
{AdvancePipe'}=0; //for MC2XferWord←1, MC2XWdly←1
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1; //reset cycler/masker bypass flip-flop, H2←(F1F2=0) (i.e. H2'←#177777), ALUF()←1 for ALUOUT←(ALUA.IN=ALUA), MC2XferWord←1, MC2XWdly←1
//{miscbus1: AdvancePipe', BBFA',BranchShift',Breakpoint', DelayedFault',EnColAd',IOAttn', LoadAd',MC1DQWRef',MC1QWRef', MC2DQWRef',MC2QWRef',NewInst, Restore',StackShift',UseCoutAsCin'}
{miscbus1}=#177777
{Cycle0Feed'}=1; //Cycle0=0
{MASK}=#177777; //ALUA←0's
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1; //Stkp←(ALUA=0), RSA,B←3,3(Stkp), TComing←1, TWPending←1, RComing←0, RWPending←0
{Cycle0Feed'}=0; //Cycle0=1
{rbus}=#177777
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1; //H1←(rbus=#177777), H3P←(ALUOUT=ALUA.IN=ALUA=0), RASAVE←RA←(Stkp=0), reset EnableMask (i.e. route ALUB←H2)
{rbus}=###
{Cycle0Feed'}=1; //Cycle0=0
{SALUF←H2'}=0
{EdgeClockFeed'}=0
{EdgeClockFeed'}=1; //SALUF←(H2[8:15]=0) (includes MA',MB), WA←(RASAVE=0), RSA,B←3,3(Stkp), SStkp←(Stkp=0)
{Cycle0Feed'}=0; //Cycle0=1
{SALUF←H2'}=1; //keep SALUF=0
{MASK}=0; //ALUA←(H1=#177777)
//Summary of initial conditions established by SpeakTest:
//R bus and StorA bus are in the high impedance state
//all input edge pins (other than R bus) are off high impedance
//ALUOUT=ALUA=H1=#177777, H3P=0, CYCOUNT=0, MASK=0
//ALUB=H2=BMUX=F1F2(down-aligned)=0, (SALUF,MA',MB)=0
//WA=RASAVE=RA=Stkp=0, SStkp=0, RSA,B=3,3(Stkp)
//MIR=mirbus=#1537: MemInst=0, RMOD=1, RSEL=01 11 11 (R←NBR)
//MC1XferWord=1, MC1XWdly=1, MC2XferWord=1, MC2XWdly=1
//TComing=1 and TWPending=1 for convenient clkH3P and TWriteStrobe
//key signals: Abort'=1, Suspend=0, Cycle0=1
//other signals can be determined by checking SpeakTest entries
]