-- File: [Cherry]<Thyme>Spice>SampleInverter.thy
-- Last edited:
-- SChen,  February 13, 1984  2:53 AM

library[MosModels];
library[Level2Model];
library[StdFunctions];

circuit[Lambda_ 2.0u, Temp _ 27]={

! ThymeBasics.thy
! Level2Mosfet.thy
! NSil3-WorstCase.thy

in:node; out:node; Vdd:node; 
powerSupply: voltage[Vdd, Gnd]= 5.0;
?:capacitor[out,Gnd] = 0.1pF;
?:DEP2[out, out, Vdd, Gnd];
?:ENH[in, Gnd, out, Gnd];
?:RectWave[in|period_ 200us, width _ 110us, tRise _ 10us, tFall _ 10us, tDelay _ 90us];
};

print[in, out];
plot["Nsil3 Inverter, worst case", :4us, -1, 6, in, out];
run[tMax _ 400us];