-- File: [Cherry]ProcessDefs>NMos4.0u50.thy -- Last edited: -- SChen, October 24, 1984 7:05:59 pm PDT, -- corrected calculations for Ps and Pd using sdExtension. -- by Barth, July 8, 1983 4:17 PM -- by SChen June 11, 1983 5:17 PM -- dc parameters cf. Doganis memo of May 17, 83 -- for run 65, wafer 9, location 125-127. -- The following things ought to be done some day. -- Characterize transistor and parasitic parameters over process variations. -- Account for edge effects. -- Check that temperature model is correct. -- Compare Thyme output to actual circuit performance. -- Provide gate and overlap capacitance measurements. -- Account for variation in wire capacitance due to layers underneath, -- requires extractor enhancement. ETran: circuit[gate, source, drain| L_ 2, W_ 4, sourceExtension _ 1, drainExtension _ 1]= { fet: MosFet[gate, source, drain, Gnd| Lm_ L*Lambda, Wm_ W*Lambda, As_ sourceExtension*W*Lambda*Lambda, Ad_ drainExtension*W*Lambda*Lambda, Ps_ (2*sourceExtension+W)*Lambda, Pd_ (2*drainExtension+W)*Lambda, Vfb_ -2.286541E-02, Na_ 8.849108E+14, Tox_ 700, Lk1_ -1.00014, Wk1_ 0.386899, K20_ -2.722338E-02, Lk2_ -0.778330, Wk2_ 1.95771, Etao_ -3.151041E-02, nEta_ 4.23137, Un_ 602.865, Vo_ 32.1859, Lu_ 0.742874, Ecrit_ 1.47651, Lv_ 8.69080, dL_ 0.487116, dW_ -2.42256, TDegC_ Temp, Cj_ 8.84E-17, Cjm_ 2.24E-16, Pb_ 0.88 ] }; DTran: circuit[gate, source, drain| L_ 4, W_ 2, sourceExtension _ 1, drainExtension _ 1]= { fet: MosFet[gate, source, drain, Gnd| Lm_ L*Lambda, Wm_ W*Lambda, As_ sourceExtension*W*Lambda*Lambda, Ad_ drainExtension*W*Lambda*Lambda, Ps_ (2*sourceExtension+W)*Lambda, Pd_ (2*drainExtension+W)*Lambda, Vfb_ -4.21750, Na_ 9.721774E+14, Tox_ 700, Lk1_ -1.09394, Wk1_ 2.84402, K20_ -1.311438E-02, Lk2_ 6.30416, Wk2_ -0.566979, Etao_ 2.725814E-02, nEta_ 3.86192, Un_ 741.846, Vo_ 31.2362, Lu_ -0.223700, Ecrit_ 1.12810, Lv_ 23.7731, dL_ 0.550266, dW_ -2.41600, TDegC_ Temp, Cj_ 8.84E-17, Cjm_ 2.24E-16, Pb_ 0.88 ] }; WireCap: circuit[n| -- l=length, w=width, a=area, p=perimeter l2M_ 0, w2M_ 3, a2M_ 0, p2M_ 0, -- 2nd layer metal lM_ 0, wM_ 3, aM_ 0, pM_ 0, -- 1rst layer metal lP_ 0, wP_ 2, aP_ 0, pP_ 0, -- poly a2MC_ 1.3E-5pF, p2MC_ 0, -- /(uM)^2, /uM, 2nd layer metal to bulk aMC_ 2.6E-5pF, pMC_ 0, -- 1rst layer metal to bulk aPC_ 4.0E-5pF, pPC_ 0 -- poly to bulk ] = { C: capacitor[n, Gnd] = Lambda* (Lambda*((a2M+l2M*w2M)*a2MC+(aM+lM*wM)*aMC+(aP+lP*wP)*aPC)+ (p2M+2*l2M+2*w2M)*p2MC+(pM+2*lM+2*wM)*pMC+(pP+2*lP)*pPC) }; DifCap: circuit[n| lD_ 0, wD_ 0, aD _ 0, pD _ 0]= { dc: Diffusion[n, Gnd | a_ (lD*wD+aD)*Lambda*Lambda, p_ (2*(lD+wD)+pD)*Lambda, Cj_ 8.90E-17, Cjm_ 2.25E-16, Pb_ 0.87, TDegC_ Temp] }; WireRes: circuit[nodeA, nodeB| l2M_ 0, w2M_ 3, lM_ 0, wM_ 3, lP_ 0, wP_ 2, lD_ 0, wD_ 2, s2MR_ 0.06, -- ohms/square sMR_ 0.06, sPR_ 40, sDR_ 30] = { R: resistor[nodeA, nodeB] = l2M/w2M*s2MR + lM/wM*sMR + lP/wP*sPR + lD/wD*sDR }; ConRes: circuit[nodeA, nodeB| n2MM_ 0, -- number of parallel 2nd layer metal to 1rst layer metal vias nMP_ 0, -- number of parallel 1rst layer metal to poly contacts nMD_ 0, -- number of parallel 1rst layer metal to diffusion contacts nPD_ 0, -- number of parallel poly to diffusion contacts, butting c2MMR_ 40, -- ohms/via, 2nd layer metal to 1rst layer cMPR_ 40, -- ohms/contact, metal-poly cMDR_ 25, -- ohms/contact, metal-diffusion cPDR_ 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact ] = { R: resistor[nodeA, nodeB] = 1/(n2MM/c2MMR + nMP/cMPR + nMD/cMDR + nPD/cPDR) }; Stray: circuit[n | a2M _ 0, p2M _ 0, aM _ 0, pM _ 0, aP _ 0, pP _ 0, aD _ 0, pD _ 0 ] = { wireCap: WireCap [n | a2M _ a2M, p2M _ p2M, aM _ aM, pM _ pM, aP _ aP, pP _ pP]; difCap: DifCap [n | aD _ aD, pD _ pD]; };