-- File: [Cherry]<Thyme>ProcessDefs>CMos2.0u25.thy
-- Last edited:
-- SChen, October 24, 1984 7:02:35 pm PDT,
--   corrected calculations for Ps and Pd using sdExtension.
-- Ted Williams June 22, 1984  2:08 PM to add new extracted
--   data from Akis Doganis for CSIM model.
--   (CMOS36) Run 120, Wafer 10, DIE=128-127.
-- McCreight, October 18, 1983  5:27 PM  to add simulated depletion NMOS
-- McCreight, September 15, 1983  to add Stray capacitances
--    from I. Bol's Xerox (ED) CMOS Spec of Feb 83

NETran: circuit[gate, source, drain, bulk|
  l_ 2, w_ 8, as_ 240, ad_ 240, ps_ 80, pd_ 80]= {

  fet: MosFet[gate, source, drain, bulk|
    Lm_ l*Lambda, 
    Wm_ w*Lambda,
    As_ as*Lambda*Lambda, 
    Ad_ ad*Lambda*Lambda,
    Ps_ ps*Lambda, 
    Pd_ pd*Lambda,
    Vfb_ -1.22980,
    Na_ 9.885124E+16,
    Tox_ 295,
    Lk1_ -5.339235E-02,
    Wk1_ -7.352594E-02,
    K20_ 0.280243,
    Lk2_ 26.254938E-02,
    Wk2_ -0.524566,
    Etao_ 4.584877E-03,
    nEta_ 2.66516,
    Un_ 558.453,
    Vo_ 105.205,
    Lu_ 13.4530,
    Ecrit_ 4.09776,
    Lv_ 3.05445,
    dL_ -0.201643,
    dW_ -1.60051,
    Xj2_ 0.4,
    TDegC_ 25,
    Cj_ 8.73E-17,
    Cjm_ 1.10E-16,
    Pb_ 0.90
    ]
  };

-- sdExtend is added by Ted Williams on July 7, 1983  11:48 AM
-- It is a guessed value to calculate source and drain capacitance,
-- as suggested by Mccreight and SChen.   Nobody really has a better way.

  ETran:  circuit[gate, source, drain | L _ 2, W _ 4, sdExtend _ 2] = {
    nt:  NETran[gate, source, drain, Gnd |
	  l _ L,
	  w _ W,	
	  as _ W*sdExtend,
	  ad _ W*sdExtend,
	  ps  _ 2*sdExtend+W,
	  pd _ 2*sdExtend+W]};
    -- n-channel enhancement-mode transistor


PETran: circuit[gate, source, drain, bulk|
  l_ 2, w_ 24, as_ 720, ad_ 720, ps_ 110, pd_ 110]= {

  fet: MosFet[gate, source, drain, bulk|
    Lm_ l*Lambda, 
    Wm_ w*Lambda,
    As_ as*Lambda*Lambda, 
    Ad_ ad*Lambda*Lambda,
    Ps_ ps*Lambda, 
    Pd_ pd*Lambda,
    Vfb_ -0.563522,
    Na_ 1.335061E+16,
    Tox_ 295,
    Lk1_ -0.977357,
    Wk1_ -5.709164E-02,
    K20_ -2.316437E-02,
    Lk2_ 2.57879,
    Wk2_ 3.92364,
    Etao_ 2.882671E-02,
    nEta_ 2.29445,
    Un_ 185.816,
    Vo_ 19.0121,
    Lu_ 1.56999,
    Ecrit_ 8.600,
    Lv_ 3.53001,
    dL_ -7.001376E-02,
    dW_ -1.54116,
    TDegC_ 25,
    Xj2_ 0.4,
    Type_ -1,
    Cj_ 2.33E-16,
    Cjm_ 2.95E-16,
    Pb_ 0.94
    ]
  };

  CTran:  circuit[gate, source, drain | L _ 2, W _ 4, sdExtend _ 2] = {
    pt:  PETran[gate, source, drain, Vdd |
  	  l _ L,
	  w _ W,
	  as _ W*sdExtend,
	  ad _ W*sdExtend,
	  ps  _ 2*sdExtend+W,
	  pd _ 2*sdExtend+W]};
    -- p-channel enhancement-mode transistor

NDTran: circuit[gate, source, drain|  -- from NMos4.0u25.thy
  L_ 4, W_ 2, sourceExtension _ 1, drainExtension _ 1]= {

  fet: MosFet[gate, source, drain, Gnd|
    Lm_ L*Lambda, 
    Wm_ W*Lambda,
    As_ sourceExtension*W*Lambda*Lambda, 
    Ad_ drainExtension*W*Lambda*Lambda,
    Ps_ (2*sourceExtension+W)*Lambda, 
    Pd_ (2*drainExtension+W)*Lambda,
    Vfb_ -4.24520,
    Na_ 9.721774E+14,
    Tox_ 700,
    Lk1_ -1.05228,
    Wk1_ 2.83468,
    K20_ -1.200934E-02,
    Lk2_ 6.95809,
    Wk2_ -0.802315,
    Etao_ 2.570121E-02,
    nEta_ 3.67642,
    Un_ 848.461,
    Vo_ 31.6363,
    Lu_ -0.141426,
    Ecrit_ 1.05208,
    Lv_ 26.6670,
    dL_ 0.550266,
    dW_ -2.41600,
    TDegC_ Temp,
    Cj_ 8.73E-17,
    Cjm_ 2.21E-16,
    Pb_ 0.90
    ]
  };

WireCap:  circuit[n|  -- l=length, w=width, a=area, p=perimeter
  lM2_ 0, wM2_ 3, aM2_ 0, pM2_ 0, -- 2nd layer metal
  lM_ 0, wM_ 3, aM_ 0, pM_ 0,  -- 1rst layer metal
  lP_ 0, wP_ 2, aP_ 0, pP_ 0,  -- poly
  aG_ 0, pG _ 0, -- poly over thin oxide (if transistor unsimulated)
  aM2C_ 1.3E-5pF, pM2C_ 0, -- /(uM)^2, /uM, 2nd layer metal to bulk
  aMC_ 2.6E-5pF, pMC_ 0,  -- 1rst layer metal to bulk
  aPC_ 4.0E-5pF, pPC_ 0,  -- poly to bulk
  aGC _ 11.8e-4pF -- poly over thin oxide
  ] = {

  C: capacitor[n, Gnd] = Lambda*
    (Lambda*((aM2+lM2*wM2)*aM2C+(aM+lM*wM)*aMC+(aP+lP*wP)*aPC +aG*aGC)+
    (pM2+2*lM2+2*wM2)*pM2C+(pM+2*lM+2*wM)*pMC+(pP+2*lP)*pPC)
  };

DifCap: circuit[n| lnD_ 0, wnD_ 0, anD _ 0, pnD _ 0, lpD_ 0, wpD_ 0, apD _ 0, ppD _ 0]= {

-- The figures for area capacitance agree fairly well with the
-- measured figures by Ted Williams (July 1983), but there is no
--  verification of the figures for edge capacitance.

  ndc: Diffusion[n, Gnd |
    a_ (lnD*wnD+anD)*Lambda*Lambda, 
    p_ (2*(lnD+wnD)+pnD)*Lambda, 
    Cj_ 8.73E-17, -- These figures calculated by SChen 
    Cjm_ 1.10E-16, -- June 11, 1983
    Pb_ 0.87,
    TDegC_ Temp];
  pdc: Diffusion[n, Gnd |
    a_ (lpD*wpD+apD)*Lambda*Lambda, 
    p_ (2*(lpD+wpD)+ppD)*Lambda, 
    Cj_ 2.33E-16, -- These figures calculated by SChen 
    Cjm_ 2.95E-16, -- June 11, 1983
    Pb_ 0.87,
    TDegC_ Temp]
  };

WireRes: circuit[nodeA, nodeB|
  lM2_ 0, wM2_ 3,
  lM_ 0, wM_ 3, 
  lP_ 0, wP_ 2, 
  lD_ 0, wD_ 2,

  sM2R_ 0.06,  -- ohms/square
  sMR_ 0.06,
  sPR_ 40,
  sDR_ 30] = {

  R: resistor[nodeA, nodeB] = lM2/wM2*sM2R + lM/wM*sMR + lP/wP*sPR + lD/wD*sDR
  };

ConRes: circuit[nodeA, nodeB|
  nM2M_ 0,  -- number of parallel 2nd layer metal to 1rst layer metal vias
  nMP_ 0,   -- number of parallel 1rst layer metal to poly contacts
  nMD_ 0,   -- number of parallel 1rst layer metal to diffusion contacts
  nPD_ 0,   -- number of parallel poly to diffusion contacts, butting

  cM2MR_ 40, -- ohms/via, 2nd layer metal to 1rst layer
  cMPR_ 40,  -- ohms/contact, metal-poly
  cMDR_ 25, -- ohms/contact, metal-diffusion
  cPDR_ 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact
  ] = {

  R: resistor[nodeA, nodeB] = 1/(nM2M/cM2MR + nMP/cMPR + nMD/cMDR + nPD/cPDR)
  };

  Stray:  circuit[n |
    aM2 _ 0, pM2 _ 0,
    aM _ 0, pM _ 0,
    aP _ 0, pP _ 0,
    anD _ 0, pnD _ 0,
    apD _ 0, ppD _ 0,
    aG _ 0, pG _ 0
    ] = {
      wireCap: WireCap [n |
        aM2 _ aM2, pM2 _ pM2,
        aM _ aM, pM _ pM,
        aP _ aP, pP _ pP,
        aG _ aG, pG _ pG];
      difCap: DifCap [n | anD _ anD, pnD _ pnD, apD _ apD, ppD _ ppD];
      };