-- File: [Cherry]<Thyme>ProcessDefs>CMos2.0u25.thy
-- Last edited:
-- SChen, October 24, 1984 7:02:35 pm PDT,
-- corrected calculations for Ps and Pd using sdExtension.
-- Ted Williams June 22, 1984 2:08 PM to add new extracted
-- data from Akis Doganis for CSIM model.
-- (CMOS36) Run 120, Wafer 10, DIE=128-127.
-- McCreight, October 18, 1983 5:27 PM to add simulated depletion NMOS
-- McCreight, September 15, 1983 to add Stray capacitances
-- from I. Bol's Xerox (ED) CMOS Spec of Feb 83
NETran: circuit[gate, source, drain, bulk|
l← 2, w← 8, as← 240, ad← 240, ps← 80, pd← 80]= {
fet: MosFet[gate, source, drain, bulk|
Lm← l*Lambda,
Wm← w*Lambda,
As← as*Lambda*Lambda,
Ad← ad*Lambda*Lambda,
Ps← ps*Lambda,
Pd← pd*Lambda,
Vfb← -1.22980,
Na← 9.885124E+16,
Tox← 295,
Lk1← -5.339235E-02,
Wk1← -7.352594E-02,
K20← 0.280243,
Lk2← 26.254938E-02,
Wk2← -0.524566,
Etao← 4.584877E-03,
nEta← 2.66516,
Un← 558.453,
Vo← 105.205,
Lu← 13.4530,
Ecrit← 4.09776,
Lv← 3.05445,
dL← -0.201643,
dW← -1.60051,
Xj2← 0.4,
TDegC← 25,
Cj← 8.73E-17,
Cjm← 1.10E-16,
Pb← 0.90
]
};
-- sdExtend is added by Ted Williams on July 7, 1983 11:48 AM
-- It is a guessed value to calculate source and drain capacitance,
-- as suggested by Mccreight and SChen. Nobody really has a better way.
ETran: circuit[gate, source, drain | L ← 2, W ← 4, sdExtend ← 2] = {
nt: NETran[gate, source, drain, Gnd |
l ← L,
w ← W,
as ← W*sdExtend,
ad ← W*sdExtend,
ps ← 2*sdExtend+W,
pd ← 2*sdExtend+W]};
-- n-channel enhancement-mode transistor
PETran: circuit[gate, source, drain, bulk|
l← 2, w← 24, as← 720, ad← 720, ps← 110, pd← 110]= {
fet: MosFet[gate, source, drain, bulk|
Lm← l*Lambda,
Wm← w*Lambda,
As← as*Lambda*Lambda,
Ad← ad*Lambda*Lambda,
Ps← ps*Lambda,
Pd← pd*Lambda,
Vfb← -0.563522,
Na← 1.335061E+16,
Tox← 295,
Lk1← -0.977357,
Wk1← -5.709164E-02,
K20← -2.316437E-02,
Lk2← 2.57879,
Wk2← 3.92364,
Etao← 2.882671E-02,
nEta← 2.29445,
Un← 185.816,
Vo← 19.0121,
Lu← 1.56999,
Ecrit← 8.600,
Lv← 3.53001,
dL← -7.001376E-02,
dW← -1.54116,
TDegC← 25,
Xj2← 0.4,
Type← -1,
Cj← 2.33E-16,
Cjm← 2.95E-16,
Pb← 0.94
]
};
CTran: circuit[gate, source, drain | L ← 2, W ← 4, sdExtend ← 2] = {
pt: PETran[gate, source, drain, Vdd |
l ← L,
w ← W,
as ← W*sdExtend,
ad ← W*sdExtend,
ps ← 2*sdExtend+W,
pd ← 2*sdExtend+W]};
-- p-channel enhancement-mode transistor
NDTran: circuit[gate, source, drain| -- from NMos4.0u25.thy
L← 4, W← 2, sourceExtension ← 1, drainExtension ← 1]= {
fet: MosFet[gate, source, drain, Gnd|
Lm← L*Lambda,
Wm← W*Lambda,
As← sourceExtension*W*Lambda*Lambda,
Ad← drainExtension*W*Lambda*Lambda,
Ps← (2*sourceExtension+W)*Lambda,
Pd← (2*drainExtension+W)*Lambda,
Vfb← -4.24520,
Na← 9.721774E+14,
Tox← 700,
Lk1← -1.05228,
Wk1← 2.83468,
K20← -1.200934E-02,
Lk2← 6.95809,
Wk2← -0.802315,
Etao← 2.570121E-02,
nEta← 3.67642,
Un← 848.461,
Vo← 31.6363,
Lu← -0.141426,
Ecrit← 1.05208,
Lv← 26.6670,
dL← 0.550266,
dW← -2.41600,
TDegC← Temp,
Cj← 8.73E-17,
Cjm← 2.21E-16,
Pb← 0.90
]
};
WireCap: circuit[n| -- l=length, w=width, a=area, p=perimeter
lM2← 0, wM2← 3, aM2← 0, pM2← 0, -- 2nd layer metal
lM← 0, wM← 3, aM← 0, pM← 0, -- 1rst layer metal
lP← 0, wP← 2, aP← 0, pP← 0, -- poly
aG← 0, pG ← 0, -- poly over thin oxide (if transistor unsimulated)
aM2C← 1.3E-5pF, pM2C← 0, -- /(uM)↑2, /uM, 2nd layer metal to bulk
aMC← 2.6E-5pF, pMC← 0, -- 1rst layer metal to bulk
aPC← 4.0E-5pF, pPC← 0, -- poly to bulk
aGC ← 11.8e-4pF -- poly over thin oxide
] = {
C: capacitor[n, Gnd] = Lambda*
(Lambda*((aM2+lM2*wM2)*aM2C+(aM+lM*wM)*aMC+(aP+lP*wP)*aPC +aG*aGC)+
(pM2+2*lM2+2*wM2)*pM2C+(pM+2*lM+2*wM)*pMC+(pP+2*lP)*pPC)
};
DifCap: circuit[n| lnD← 0, wnD← 0, anD ← 0, pnD ← 0, lpD← 0, wpD← 0, apD ← 0, ppD ← 0]= {
-- The figures for area capacitance agree fairly well with the
-- measured figures by Ted Williams (July 1983), but there is no
-- verification of the figures for edge capacitance.
ndc: Diffusion[n, Gnd |
a← (lnD*wnD+anD)*Lambda*Lambda,
p← (2*(lnD+wnD)+pnD)*Lambda,
Cj← 8.73E-17, -- These figures calculated by SChen
Cjm← 1.10E-16, -- June 11, 1983
Pb← 0.87,
TDegC← Temp];
pdc: Diffusion[n, Gnd |
a← (lpD*wpD+apD)*Lambda*Lambda,
p← (2*(lpD+wpD)+ppD)*Lambda,
Cj← 2.33E-16, -- These figures calculated by SChen
Cjm← 2.95E-16, -- June 11, 1983
Pb← 0.87,
TDegC← Temp]
};
WireRes: circuit[nodeA, nodeB|
lM2← 0, wM2← 3,
lM← 0, wM← 3,
lP← 0, wP← 2,
lD← 0, wD← 2,
sM2R← 0.06, -- ohms/square
sMR← 0.06,
sPR← 40,
sDR← 30] = {
R: resistor[nodeA, nodeB] = lM2/wM2*sM2R + lM/wM*sMR + lP/wP*sPR + lD/wD*sDR
};
ConRes: circuit[nodeA, nodeB|
nM2M← 0, -- number of parallel 2nd layer metal to 1rst layer metal vias
nMP← 0, -- number of parallel 1rst layer metal to poly contacts
nMD← 0, -- number of parallel 1rst layer metal to diffusion contacts
nPD← 0, -- number of parallel poly to diffusion contacts, butting
cM2MR← 40, -- ohms/via, 2nd layer metal to 1rst layer
cMPR← 40, -- ohms/contact, metal-poly
cMDR← 25, -- ohms/contact, metal-diffusion
cPDR← 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact
] = {
R: resistor[nodeA, nodeB] = 1/(nM2M/cM2MR + nMP/cMPR + nMD/cMDR + nPD/cPDR)
};
Stray: circuit[n |
aM2 ← 0, pM2 ← 0,
aM ← 0, pM ← 0,
aP ← 0, pP ← 0,
anD ← 0, pnD ← 0,
apD ← 0, ppD ← 0,
aG ← 0, pG ← 0
] = {
wireCap: WireCap [n |
aM2 ← aM2, pM2 ← pM2,
aM ← aM, pM ← pM,
aP ← aP, pP ← pP,
aG ← aG, pG ← pG];
difCap: DifCap [n | anD ← anD, pnD ← pnD, apD ← apD, ppD ← ppD];
};