File: [Cherry]<Thyme>Cedar5.2>ProcessDefs>NMos4.0u50C.thy
Last Edited by: SChen, October 24, 1984 6:29:24 pm PDT
ETran: circuit[gate, source, drain |
L ← 2, W ← 4, sourceExtension ← 1, drainExtension ← 1]= {
fet: MosFet[gate, source, drain, Gnd |
Lm ← L*Lambda,
Wm ← W*Lambda,
As ← sourceExtension*W*Lambda*Lambda,
Ad ← drainExtension*W*Lambda*Lambda,
Ps ← (2*sourceExtension+W)*Lambda,
Pd ← (2*drainExtension+W)*Lambda,
Vfb ← -2.286541E-02,
Na ← 8.849108E+14,
Tox ← 700,
Lk1 ← -1.00014,
Wk1 ← 0.386899,
K20 ← -2.722338E-02,
Lk2 ← -0.778330,
Wk2 ← 1.95771,
Etao ← -3.151041E-02,
nEta ← 4.23137,
Un ← 602.865,
Vo ← 32.1859,
Lu ← 0.742874,
Ecrit ← 1.47651,
Lv ← 8.69080,
dL ← 0.487116,
dW ← -2.42256,
TDegC ← Temp,
Cj ← 8.84E-17,
Cjm ← 2.24E-16,
Pb ← 0.88
]
}; -- ETran
DTran: circuit[gate, source, drain |
L ← 4, W ← 2, sourceExtension ← 1, drainExtension ← 1]= {
fet: MosFet[gate, source, drain, Gnd |
Lm ← L*Lambda,
Wm ← W*Lambda,
As ← sourceExtension*W*Lambda*Lambda,
Ad ← drainExtension*W*Lambda*Lambda,
Ps ← (2*sourceExtension+W)*Lambda,
Pd ← (2*drainExtension+W)*Lambda,
Vfb ← -4.21750,
Na ← 9.721774E+14,
Tox ← 700,
Lk1 ← -1.09394,
Wk1 ← 2.84402,
K20 ← -1.311438E-02,
Lk2 ← 6.30416,
Wk2 ← -0.566979,
Etao ← 2.725814E-02,
nEta ← 3.86192,
Un ← 741.846,
Vo ← 31.2362,
Lu ← -0.223700,
Ecrit ← 1.12810,
Lv ← 23.7731,
dL ← 0.550266,
dW ← -2.41600,
TDegC ← Temp,
Cj ← 8.84E-17,
Cjm ← 2.24E-16,
Pb ← 0.88
]
}; -- DTran
WireCap: circuit[n |
-- l=length, w=width, a=area, p=perimeter
l2M ← 0, w2M ← 3, a2M ← 0, p2M ← 0, -- 2nd layer metal
lM ← 0, wM ← 3, aM ← 0, pM ← 0, -- 1rst layer metal
lP ← 0, wP ← 2, aP ← 0, pP ← 0, -- poly
a2MC ← 1.3E-5pF, p2MC ← 0, -- /(uM)^2, /uM, 2nd layer metal to bulk
aMC ← 2.6E-5pF, pMC ← 0, -- 1rst layer metal to bulk
aPC ← 4.0E-5pF, pPC ← 0 -- poly to bulk
] = {
C: capacitor[n, Gnd] = Lambda*
(Lambda*((a2M+l2M*w2M)*a2MC+(aM+lM*wM)*aMC+(aP+lP*wP)*aPC)+
(p2M+2*l2M+2*w2M)*p2MC+(pM+2*lM+2*wM)*pMC+(pP+2*lP)*pPC)
}; -- WireCap
DifCap: circuit[n | lD ← 0, wD ← 0, aD ← 0, pD ← 0]= {
dc: Diffusion[n, Gnd |
a ← (lD*wD+aD)*Lambda*Lambda,
p ← (2*(lD+wD)+pD)*Lambda,
Cj ← 8.90E-17,
Cjm ← 2.25E-16,
Pb ← 0.87,
TDegC ← Temp]
}; -- DifCap
WireRes: circuit[nodeA, nodeB |
l2M ← 0, w2M ← 3,
lM ← 0, wM ← 3,
lP ← 0, wP ← 2,
lD ← 0, wD ← 2,
s2MR ← 0.06, -- ohms/square
sMR ← 0.06,
sPR ← 40,
sDR ← 30] = {
R: resistor[nodeA, nodeB] = l2M/w2M*s2MR + lM/wM*sMR + lP/wP*sPR + lD/wD*sDR
}; -- WireRes
ConRes: circuit[nodeA, nodeB |
n2MM ← 0, -- number of parallel 2nd layer metal to 1rst layer metal vias
nMP ← 0, -- number of parallel 1rst layer metal to poly contacts
nMD ← 0, -- number of parallel 1rst layer metal to diffusion contacts
nPD ← 0, -- number of parallel poly to diffusion contacts, butting
c2MMR ← 40, -- ohms/via, 2nd layer metal to 1rst layer
cMPR ← 40, -- ohms/contact, metal-poly
cMDR ← 25, -- ohms/contact, metal-diffusion
cPDR ← 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact
] = {
R: resistor[nodeA, nodeB] = 1/(n2MM/c2MMR + nMP/cMPR + nMD/cMDR + nPD/cPDR)
}; -- ConRes
Stray: circuit[n |
a2M ← 0, p2M ← 0,
aM ← 0, pM ← 0,
aP ← 0, pP ← 0,
aD ← 0, pD ← 0
] = {
wireCap: WireCap[n |
a2M ← a2M, p2M ← p2M,
aM ← aM, pM ← pM,
aP ← aP, pP ← pP];
difCap: DifCap[n | aD ← aD, pD ← pD];
}; -- Stray
Change Log.
Barth, July 8, 1983 4:17 PM
SChen June 11, 1983 5:17 PM
dc parameters cf. Doganis memo of May 17, 83 for run 65, wafer 9, location 125-127.
SChen, October 24, 1984 6:18:37 pm PDT, corrected calculations for Ps/Pd using sdExtension.
The following things ought to be done some day.
Characterize transistor and parasitic parameters over process variations.
Account for edge effects.
Check that temperature model is correct.
Compare Thyme output to actual circuit performance.
Provide gate and overlap capacitance measurements.
Account for variation in wire capacitance due to layers underneath, requires extractor enhancement.