
<<BSimCurves25.thy>>
<<simple simulations>>

<<Last Edited by: McCreight, April 25, 1985 9:34:59 am PST>>

CIRCUIT[Lambda _ 1.0, TDegC _ 25, polyRho _ 4, -- with silicide
tScale _ 1000, n _ 1] = {
! SignalGenerators
Vdd: node;
! BSIM


powerSupply: voltage[Vdd, Gnd] = 5.0V;

ramp: node;
RampGen: OneShot[ramp | OffLevel _ 0V, OnLevel _ 5V,
width _ tScale*2ns, tRise _ tScale*1ns, tFall _ 1ns,
tDelay _ tScale*0.1ns];

Line: circuit[| bias _ 0, etype _ 2, ctype _ -3] = {
nGate, nOut: node;
?: voltage[nGate, Gnd] = bias;
QN: ETran[nGate, Gnd, nOut | L _ 2, W _ 20, sdExtend _ 2, type _ etype];
RN: voltage[ramp, nOut] = 0;
pGate, pOut: node;
?: voltage[pGate, Vdd] = -bias;
QP: CTran[pGate, Vdd, pOut | L _ 2, W _ 20, sdExtend _ 2, type _ ctype];
RP: voltage[pOut, ramp] = 0
};

line0: Line[| bias _ 0];
line1: Line[| bias _ 1];
line2: Line[| bias _ 2];
line3: Line[| bias _ 3];
line4: Line[| bias _ 4];
line5: Line[| bias _ 5];
line5a: Line[| bias _ 5, etype _ 21, ctype _ -31];

p: node;
out: node; ?: capacitor[out, Gnd] = 100pF;
?: ETran[p, out, Gnd |  L _ 2, W _ 20, sdExtend _ 2];
?: CTran[p, out, Vdd |  L _ 2, W _ 50, sdExtend _ 2];
pulse: OneShot[p | OnLevel _ 5V,
width _ tScale*0.6ns,
tRise _ 1ns, tFall _ 1ns, tDelay _ tScale*0.1ns];
};

IC[0.0, Vdd _ 5V, out _ 5V];

PRINT[ramp, line5a/RN^, line5/RN^, line5a/RP^, line5/RP^, out];
PRINT[ramp, line5/RN^, line4/RN^, line3/RN^, line2/RN^, line1/RN^];
PRINT[ramp, line5/RP^, line4/RP^, line3/RP^, line2/RP^, line1/RP^];

PLOT["20/2 (W/L) um, 25 deg CMOS BSim Curves",
:1ns, -1, 7,
ramp,
line5a/RN^: 1mA,
line5/RN^: 1mA,
line4/RN^: 1mA,
line3/RN^: 1mA,
line2/RN^: 1mA,
line1/RN^: 1mA,
line5a/RP^: 1mA,
line5/RP^: 1mA,
line4/RP^: 1mA,
line3/RP^: 1mA,
line2/RP^: 1mA,
line1/RP^: 1mA,
out
];

RUN[tMax _ 1200ns, -- tScale*1.2ns
];
dump