File: [Cherry]<Thyme>Cedar5.2>BSim.thy
Last Edited by: McCreight, April 8, 1985 10:31:56 am PST
BSimMOS:
CIRCUIT [gate, source, drain, bulk |
L ← 2,
W ← 20, Cox ← 11.8E-4pF
--/um^2--, type ← 2 ] =
{
bsimModel: model ← BSimFromFile[gate, source, drain, bulk |
BSIM extraction, lot 205, wafer 5, device (125,127), 26 Mar 85 by Oki
L, -- Length (microns), later VFB (volts)
W, -- Width (microns), later twoPhiF (volts)
10, -- dutZRatio (W/L), later k1 (volts^0.5)
0, -- k2 ()
0, -- eta ()
0, -- beta0 (farads/(volt*second))
0, -- u0 (1/volts)
0, -- u1 (1/volts)
0, -- x2beta0
0, -- x2eta
0, -- x3eta
0, -- x2u0
0, -- x2u1
0, -- beta0sat
0, -- x2beta0sat
0, -- x2beta0sat
0, -- x3u1
0, -- n0 ... I don't know in what order these last three go...
0, -- x2nb
0, -- x3nd
0, -- vdd (volts)
273.15+TDegC, -- temp (Kelvins)
Cox*L*W, -- MCgbo (farads) (?)
Cox*L*W*2.0/3.0, -- Cgbo23rds (farads)
0, -- maxFwdBias (Vbs excess over twoPhiF) (volts)
0, -- noCap (0 => compute capacitances, 1 => don't)
type -- type (>0 => nChannel, <0 => pChannel, ABS[type]>1 selects process file "BSIMProcess-n.process")
];
i: current[drain, source] ← bsimModel[0];
cgb: capacitor[gate, bulk] ← bsimModel[1];
cgs: capacitor[gate, source] ← bsimModel[2];
cgd: capacitor[gate, drain] ← bsimModel[3];
}; -- BSimMOS
BasicDifCap:
CIRCUIT [cathode, anode |
Co ← 0 -- farads --,
PhiZero ← 0.9 -- junction built-in potential, volts --,
Vt ← .026 -- kT/q, volts --,
Io ← -5pA -- reverse current, amps --,
VMax ← 0.6 -- volts --] =
{
sdCapModel: model ← SDDiode[cathode, anode |
Co,
1/PhiZero,
1/Vt,
Io,
VMax];
?: capacitor[cathode, anode] ← sdCapModel[0];
?: current[cathode, anode] ← sdCapModel[1];
NMOSDifCap:
CIRCUIT [dif, bulk | perim ← 0
--um--, area ← 0
--um^2-- ] =
{
?:BasicDifCap[dif, bulk |
Co ← 1.5E-4pF*area,
PhiZero ← 0.90, --?--
Vt ← 1/(8.617E-5*(TDegC+273.16)),
Io ← -5pA*area
];
?:BasicDifCap[dif, bulk |
Co ← 3.0E-4pF*perim,
PhiZero ← 0.90, --?--
Vt ← 1/(8.617E-5*(TDegC+273.16)),
Io ← -5pA*perim
];
PMOSDifCap:
CIRCUIT [dif, bulk | perim ← 0
--um--, area ← 0
--um^2-- ] =
{
?:BasicDifCap[bulk, dif |
Co ← 3.1E-4pF*area,
PhiZero ← 0.94, --?--
Vt ← 1/(8.617E-5*(TDegC+273.16)),
Io ← -5pA*area
];
?:BasicDifCap[bulk, dif |
Co ← 3.0E-4pF*perim,
PhiZero ← 0.94, --?--
Vt ← 1/(8.617E-5*(TDegC+273.16)),
Io ← -5pA*perim
];
ETran:
CIRCUIT [gate, source, drain |
L ← 2,
W ← 4, sdExtend ← 0, dWFact ← 1] = {
nt: BSimMOS[gate, source, drain, Gnd | L ← L, W ← W, type ← 2];
dCap: NMOSDifCap[drain, Gnd |
perim ← (sdExtend#0)*(2*sdExtend+W), area ← sdExtend*W ];
sCap: NMOSDifCap[source, Gnd |
perim ← (sdExtend#0)*(2*sdExtend+W), area ← sdExtend*W];
}; -- ETran
CTran:
CIRCUIT [gate, source, drain |
L ← 2,
W ← 4, sdExtend ← 0, dWFact ← 1] = {
pt: BSimMOS[gate, source, drain, Vdd | L ← L, W ← W, type ← -3];
dCap: PMOSDifCap[drain, Vdd |
perim ← (sdExtend#0)*(2*sdExtend+W), area ← sdExtend*W ];
sCap: PMOSDifCap[source, Vdd |
perim ← (sdExtend#0)*(2*sdExtend+W), area ← sdExtend*W];
}; -- CTran
WireCap: circuit[n |
-- l=length, w=width, a=area, p=perimeter
lM2 ← 0, wM2 ← 4, aM2 ← 0, pM2 ← 0, -- 2nd layer metal
lM ← 0, wM ← 3, aM ← 0, pM ← 0, -- 1rst layer metal
lP ← 0, wP ← 2, aP ← 0, pP ← 0, -- poly
aG← 0, pG ← 0, -- poly over thin oxide (if transistor unsimulated)
aM2C ← .197E-4pF, pM2C ← .486E-4pF, -- /(uM)^2, /uM, 2nd layer metal to bulk
aMC ← .276E-4pF, pMC ← .496E-4pF, -- 1rst layer metal to bulk
aPC ← .628E-4pF, pPC ← .577E-4pF, -- poly to bulk
aGC ← 11.8e-4pF -- poly over thin oxide
] = {
C: capacitor[n, Gnd] = Lambda*(Lambda*((aM2 + lM2*wM2)*aM2C + (aM + lM*wM)*aMC + (aP + lP*wP)*aPC + aG*aGC) + (pM2 + 2*lM2 + 2*wM2)*pM2C + (pM + 2*lM + 2*wM)*pMC + (pP + 2*lP)*pPC)
}; -- WireCap
Stray: circuit[n |
aM2 ← 0, pM2 ← 0,
aM ← 0, pM ← 0,
aP ← 0, pP ← 0,
anD ← 0, pnD ← 0,
apD ← 0, ppD ← 0,
aG ← 0, pG ← 0
] = {
wireCap: WireCap [n |
aM2 ← aM2, pM2 ← pM2,
aM ← aM, pM ← pM,
aP ← aP, pP ← pP,
aG ← aG, pG ← pG];
nCap: NMOSDifCap [n, Gnd | area ← Lambda*Lambda*anD, perim ← Lambda*pnD];
pCap: PMOSDifCap [n, Vdd | area ← Lambda*Lambda*apD, perim ← Lambda*ppD];
}; -- Stray