BSimCurves25.thy
simple simulations
Last Edited by: McCreight, April 25, 1985 9:34:59 am PST
CIRCUIT[Lambda ← 1.0, TDegC ← 25, polyRho ← 4, -- with silicide
tScale ← 1000, n ← 1] = {
! SignalGenerators
Vdd: node;
! BSIM
powerSupply: voltage[Vdd, Gnd] = 5.0V;
ramp: node;
RampGen: OneShot[ramp | OffLevel ← 0V, OnLevel ← 5V,
width ← tScale*2ns, tRise ← tScale*1ns, tFall ← 1ns,
tDelay ← tScale*0.1ns];
Line: circuit[| bias ← 0, etype ← 2, ctype ← -3] = {
nGate, nOut: node;
?: voltage[nGate, Gnd] = bias;
QN: ETran[nGate, Gnd, nOut | L ← 2, W ← 20, sdExtend ← 2, type ← etype];
RN: voltage[ramp, nOut] = 0;
pGate, pOut: node;
?: voltage[pGate, Vdd] = -bias;
QP: CTran[pGate, Vdd, pOut | L ← 2, W ← 20, sdExtend ← 2, type ← ctype];
RP: voltage[pOut, ramp] = 0
};
line0: Line[| bias ← 0];
line1: Line[| bias ← 1];
line2: Line[| bias ← 2];
line3: Line[| bias ← 3];
line4: Line[| bias ← 4];
line5: Line[| bias ← 5];
line5a: Line[| bias ← 5, etype ← 21, ctype ← -31];
p: node;
out: node; ?: capacitor[out, Gnd] = 100pF;
?: ETran[p, out, Gnd | L ← 2, W ← 20, sdExtend ← 2];
?: CTran[p, out, Vdd | L ← 2, W ← 50, sdExtend ← 2];
pulse: OneShot[p | OnLevel ← 5V,
width ← tScale*0.6ns,
tRise ← 1ns, tFall ← 1ns, tDelay ← tScale*0.1ns];
};
IC[0.0, Vdd ← 5V, out ← 5V];
PRINT[ramp, line5a/RN^, line5/RN^, line5a/RP^, line5/RP^, out];
PRINT[ramp, line5/RN^, line4/RN^, line3/RN^, line2/RN^, line1/RN^];
PRINT[ramp, line5/RP^, line4/RP^, line3/RP^, line2/RP^, line1/RP^];
PLOT["20/2 (W/L) um, 25 deg CMOS BSim Curves",
:1ns, -1, 7,
ramp,
line5a/RN^: 1mA,
line5/RN^: 1mA,
line4/RN^: 1mA,
line3/RN^: 1mA,
line2/RN^: 1mA,
line1/RN^: 1mA,
line5a/RP^: 1mA,
line5/RP^: 1mA,
line4/RP^: 1mA,
line3/RP^: 1mA,
line2/RP^: 1mA,
line1/RP^: 1mA,
out
];
RUN[tMax ← 1200ns, -- tScale*1.2ns
];
dump