DIRECTORY TargetArchitecture; RS6000Architecture: CEDAR DEFINITIONS ~ { RS6000Address: TYPE[SIZE[CARD32]]; nullRS6000Address: RS6000Address ~ LOOPHOLE[FIRST[CARD32]]; RS6000Contents: TYPE[SIZE[CARD32]]; RS6000Instruction: TYPE[SIZE[CARD32]]; nullRS6000Instruction: RS6000Instruction ~ LOOPHOLE[CARD32[0]]; Format3rArith: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, r (0:16..20): Register _, oe (0:21..21): OVException _, subOp (0:22..30): SubOpFor31withOE _, rc (0:31..31): Record _ ]; Format2rsi: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, si (0:16..31): SI _ ]; Format2rui: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, ui (0:16..31): UI _ ]; Format2rd: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, d (0:16..31): Disp16 _ ]; Format2rArith: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, dummy (0:16..20): Dummy5 _ 0, oe (0:21..21): OVException _, subOp (0:22..30): SubOpFor31withOE _, rc (0:31..31): Record _ ]; Format3rS: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, rb (0:16..20): Register _, subOp2 (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatBranch: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, limsb (0:6..6): BOOLEAN _, li (0:7..29): Disp23 _, aa (0:30..30): Absolute _, lk (0:31..31): Link _ ]; FormatBOnCond: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bo (0:6..10): BranchOption _, bi (0:11..15): CCBitPosition _, bdmsb (0:16..16): BOOLEAN _, bd (0:17..29): Disp13 _, aa (0:30..30): Absolute _, lk (0:31..31): Link _]; FormatBOnCondCount: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bo (0:6..10): BranchOption _, bi (0:11..15): CCBitPosition _, dummy (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor19 _, lk (0:31..31): Link _ ]; FormatCmp: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy (0:9..10): Dummy2 _ 0, ra (0:11..15): Register _, rb (0:16..20): Register _, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatCmpi: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy (0:9..10): Dummy2 _ 0, ra (0:11..15): Register _, si (0:16..31): SI _ ]; FormatCmpui: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy (0:9..10): Dummy2 _ 0, ra (0:11..15): Register _, ui (0:16..31): UI _ ]; FormatCount: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rs (0:6..10): Register _, ra (0:11..15): Register _, dummy (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatCondRegAnd: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bt (0:6..10): CCBitPosition _, ba (0:11..15): CCBitPosition _, bb (0:16..20): CCBitPosition _, subOp (0:21..30): SubOpFor19 _, lk (0:31..31): Link _ ]; FormatFl3rArith: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, fra (0:11..15): FRegister _, frb (0:16..20): FRegister _, dummy (0:21..25): Dummy5 _ 0, subOp (0:26..30): FSubOp3r63 _, rc (0:31..31): Record _ ]; FormatFl2rArith: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, dummy (0:11..15): Dummy5 _ 0, frb (0:16..20): FRegister _, subOp (0:21..30): FSubOp2r63 _, rc (0:31..31): Record _ ]; FormatFlCmp: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, fb (0:6..8): CCGroup _, dummy (0:9..10): Dummy2 _ 0, fra (0:11..15): FRegister _, frb (0:16..20): FRegister _, subOp (0:21..30): FSubOp2r63 _, rc (0:31..31): Record _ ]; FormatFlMul: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, fra (0:11..15): FRegister _, dummy (0:16..20): Dummy5 _ 0, frc (0:21..25): FRegister _, subOp (0:26..30): FSubOp3r63 _, rc (0:31..31): Record _ ]; FormatFlMulAd: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, fra (0:11..15): FRegister _, frb (0:16..20): FRegister _, frc (0:21..25): FRegister _, subOp (0:26..30): FSubOp3r63 _, rc (0:31..31): Record _ ]; FormatLoad: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, ra (0:11..15): Register _, d (0:16..31): Disp16 _ ]; FormatLoadFl: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, ra (0:11..15): Register _, d (0:16..31): Disp16 _ ]; FormatLoadFlIndex: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, ra (0:11..15): Register _, rb (0:16..20): Register _, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatLoadi: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, zero (0:11..15): Zero5 _ 0, si (0:16..31): SI _ ]; FormatLoadui: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, zero (0:11..15): Zero5 _ 0, ui (0:16..31): UI _ ]; FormatMask: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rs (0:6..10): Register _, ra (0:11..15): Register _, rb (0:16..20): Register _, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMove: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy0 (0:9..10): Dummy2 _ 0, bfa (0:11..13): CCGroup _, dummy1 (0:14..15): Dummy2 _ 0, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, lk (0:31..31): Link _ ]; FormatMoveToCR: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy0 (0:9..10): Dummy2 _ 0, dummy1 (0:11..15): Dummy5 _ 0, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveFromCR: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, dummy1 (0:11..15): Dummy5 _ 0, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveFl: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, frt (0:6..10): FRegister _, dummy1 (0:11..15): Dummy5 _ 0, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveSPR: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rt (0:6..10): Register _, spr (0:11..15): SpecialRegister _, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveToCRField: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rs (0:6..10): Register _, dummy1 (0:11..11): Dummy1 _ 0, fxm (0:12..19): FXM _, dummy2 (0:20..20): Dummy1 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveToFPSCRBit: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bt (0:6..10): CCBitPosition _, dummy1 (0:11..15): Dummy5 _ 0, dummy2 (0:16..20): Dummy5 _ 0, subOp (0:21..30): SubOpFor31withoutOE _, rc (0:31..31): Record _ ]; FormatMoveToFPSCRField: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, dummy0 (0:6..6): Dummy1 _ 0, flm (0:7..14): FLM _, dummy1 (0:15..15): Dummy1 _ 0, frb (0:16..20): FRegister _, subOp (0:21..30): FSubOp2r63 _, rc (0:31..31): Record _ ]; FormatMoveToFPSCRFieldImm: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, bf (0:6..8): CCGroup _, dummy0 (0:9..10): Dummy2 _ 0, dummy1 (0:11..15): Dummy1 _ 0, i (0:16..19): I _, dummy2 (0:20..20): Dummy1 _ 0, subOp (0:21..30): FSubOp2r63 _, rc (0:31..31): Record _ ]; FormatRotateImmMask: TYPE ~ MACHINE DEPENDENT RECORD [ op (0:0..5): Op _, rs (0:6..10): Register _, ra (0:11..15): Register _, sh (0:16..20): ShiftCount _, mb (0:21..25): BitPosition _, me (0:26..30): BitPosition _, rc (0:31..31): Record _ ]; FormatUnknown: TYPE ~ RECORD [ bits: RS6000Instruction _ ]; Register: TYPE ~ MACHINE DEPENDENT { gpr0 (0), gpr1, gpr2, gpr3, gpr4, gpr5, gpr6, gpr7, gpr8 (8), gpr9, gpr10, gpr11, gpr12, gpr13, gpr14, gpr15, gpr16 (16), gpr17, gpr18, gpr19, gpr20, gpr21, gpr22, gpr23, gpr24 (24), gpr25, gpr26, gpr27, gpr28, gpr29, gpr30, gpr31 }; stackPointer: Register ~ Register.gpr1; stackPointerOffset: NAT ~ 68 * BYTES[TargetArchitecture.Contents]; stackAllocationForArgument: NAT ~ 8 * BYTES[TargetArchitecture.Contents]; stackAllocationForLinkArea: NAT ~ 6 * BYTES[TargetArchitecture.Contents]; stackAllocationUnit: NAT ~ 2 * BYTES[TargetArchitecture.Contents]; tocPointer: Register ~ Register.gpr2; XER: TYPE ~ MACHINE DEPENDENT RECORD [ SO (0:0..0): BOOLEAN, OV (0:1..1): BOOLEAN, CA (0:2..2): BOOLEAN, reserved0 (0:3..15): [0..4095], byte (0:16..23): BYTE, reserved1 (0:24..24): BOOLEAN, count (0:25..31): [0..127] ]; MQ: TYPE ~ WORD; SpecialRegister: TYPE ~ MACHINE DEPENDENT { mq (0), xfr (1), rtcu (4), rtcl (5), dec (6), lr (8), ctr (9) }; FRegister: TYPE ~ MACHINE DEPENDENT { fpr0 (0), fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7, fpr8 (8), fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15, fpr16 (16), fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23, fpr24 (24), fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31 }; FloatingPointStatusAndControlRegister: TYPE ~ MACHINE DEPENDENT RECORD [ fpResult (0:0..19): FPResult, fpException (0:20..31): FPException ]; ConditionRegister: TYPE ~ MACHINE DEPENDENT RECORD [ cr0 (0:0..3): CCField, cr1 (0:4..7): CCField, cr2 (0:8..11): CCField, cr3 (0:12..15): CCField, cr4 (0:16..19): CCField, cr5 (0:20..23): CCField, cr6 (0:24..27): CCField, cr7 (0:28..31): CCField ]; LinkRegister: TYPE ~ WORD32; CountRegister: TYPE ~ WORD32; MachineStateRegister: TYPE ~ MACHINE DEPENDENT RECORD [ reserved0 (0:0..15): WORD16, ee (0:16..16): BOOLEAN, pr (0:17..17): BOOLEAN, fp (0:18..18): BOOLEAN, me (0:19..19): BOOLEAN, fe (0:20..20): BOOLEAN, reserved1 (0:21..23): [0..7], al (0:24..24): BOOLEAN, ip (0:25..25): BOOLEAN, ir (0:26..26): BOOLEAN, dr (0:27..27): BOOLEAN, reserved2 (0:28..31): [0..15] ]; Op: TYPE ~ MACHINE DEPENDENT { -- bits [0..5] dozi (9), cmpli (10), cmpi (11), ai (12), -- muli (12), si (12), -- aiDot (13), -- siDot (13), -- cal (14), -- lil (14), -- cau (15), -- liu (15), -- bc (16), b (18), group19 (19), rlimi (20), rlinm (21), rlmi (22), rlnm (23), oril (24), oriu (25), xoril (26), xoriu (27), andil (28), andiu (29), group31 (31), l (32), lu (33), lbz (34), lbzu (35), st (36), stu (37), stb (38), lhz (40), lhzu (41), lha (42), lhau (43), sth (44), lm (46), stm (47), lfs (48), lfsu (49), lfd (50), lfdu (51), stfs (52), stfsu (53), stfd (54), stfdu (55), group63 (63) -- , last (63) -- }; SubOpFor31withOE: TYPE ~ MACHINE DEPENDENT { -- bits [22..30] sf (8), a (10), mul (107), sfe (136), ae (138), sfze (200), aze (202), sfme (232), me (234), muls (235), doz (264), cax (266), eqv (284), adiv (331), abs (360), divs (363), -- exts (922), -- nabs (488), last (511) }; SubOpFor31withoutOE: TYPE ~ MACHINE DEPENDENT { -- bit [21..30] cmp (0), t (4), mfcr (19), lx (23), sl (24), cntlz (26), and (28), maskg (29), cmpl (32), lux (55), andc (60), mfmsr (83), lbzx (87), lbzux (119), nor (124), mtcrf (144), stx (151), slq (152), sle (153), stux (183), sliq (184), stbx (215), sllq (216), sleq (217), stbux (247), slliq (248), lscbx (277), lhzx (279), lhzux (311), xor (316), mfspr (339), lhax (343), lhaux (375), sthx (407), orc (412), sthux (439), or (444), mtspr (467), nand(476), mcrxr (512), lsx (533), lbrx (534), lfsx (535), sr (536), rrib (537), maskir (541), lfsux (567), lsi (597), lfdx (599), lfdux (631), stsx (661), stbrx (662), stfsx (663), srq (664), sre (665), stfsux (695), sriq (696), stfdx (727), srlq (728), sreq (729), stfdux (759), srliq (760), lhbrx (790), sra (792), srai (824), sthbrx (918), sraq (920), srea (921), sraiq (952), last (1023) }; SubOpFor19: TYPE ~ MACHINE DEPENDENT { -- bit [21..30] mcrf (0), bcr (16), crnor (33), crandc (129), crxor (193), crnand (225), crand (257), creqv (289), crorc (417), cror (449), bcc (528), last (1023) }; FSubOp3r63: TYPE ~ MACHINE DEPENDENT { -- bit [26..30] fd (18), fs (20), fa (21), fm (25), fms (28), fma (29), fnms (30), fnma (31) --, last(31) -- }; FSubOp2r63: TYPE ~ MACHINE DEPENDENT { -- bit [21..30] fcmpu(0), frsp (12), fcmpo (32), mtfsb1 (38), fneg (40), mcrfs (64), mtfsb0 (70), fmr(72), mtfsfi (134), fnabs (136), fabs (264), mffs (583), mtfsf (711), last (1023) }; OVException: TYPE ~ BOOLEAN; Record: TYPE ~ BOOLEAN; Absolute: TYPE ~ BOOLEAN; Link: TYPE ~ BOOLEAN; SI: TYPE ~ CARD16; UI: TYPE ~ CARD16; Offset26: TYPE ~ [-33554432..33554431]; firstOffset26: Offset26 ~ -33554432; lastOffset26: Offset26 ~ 33554431; Disp24: TYPE ~ [-8388608..8388607]; firstDisp24: Disp24 ~ -8388608; lastDisp24: Disp24 ~ 8388607; Disp23: TYPE ~ [0..8388607]; Disp16: TYPE ~ INT16; -- [-32768..32767] firstDisp16: Disp16 ~ -32768; lastDisp16: Disp16 ~ 32767; Disp14: TYPE ~ [-8192..8191]; firstDisp14: Disp14 ~ -8192; lastDisp14: Disp14 ~ 8191; Disp13: TYPE ~ [0..8191]; BitPosition: TYPE ~ [0..31]; ShiftCount: TYPE ~ [0..31]; CCBitPosition: TYPE ~ [0..31]; CCGroup: TYPE ~ [0..7]; CCField: TYPE ~ MACHINE DEPENDENT RECORD [ lt(0:0..0): BOOLEAN, rb(0:1..1): BOOLEAN, eq(0:2..2): BOOLEAN, so(0:3..3): BOOLEAN ]; FPCCField: TYPE ~ [0..15]; FPCCGroup: TYPE ~ [0..7]; FPResult: TYPE ~ [0..1048575]; -- 20 bits FPException: TYPE ~ [0..4095]; -- 12 bits I: TYPE ~ [0..15]; Dummy5: TYPE ~ [0..31]; Dummy2: TYPE ~ [0..3]; Dummy1: TYPE ~ [0..1]; Zero5: TYPE ~ [0..31]; BranchOption: TYPE ~ MACHINE DEPENDENT RECORD [ ifzero: BOOLEAN, incFlag: BOOLEAN, ifFalse: BOOLEAN, ifTrue: BOOLEAN, always: BOOLEAN ]; FLM:TYPE ~ MACHINE DEPENDENT RECORD [ fpscr0To3: BOOLEAN, fpscr4To7: BOOLEAN, fpscr8To11: BOOLEAN, fpscr12To15: BOOLEAN, fpscr16To19: BOOLEAN, fpscr20To23: BOOLEAN, fpscr24To27: BOOLEAN, fpscr28To31: BOOLEAN ]; FXM:TYPE ~ MACHINE DEPENDENT RECORD [ cr0To3: BOOLEAN, cr4To7: BOOLEAN, cr8To11: BOOLEAN, cr12To15: BOOLEAN, cr16To19: BOOLEAN, cr20To23: BOOLEAN, cr24To27: BOOLEAN, cr28To31: BOOLEAN ]; OE: TYPE ~ MACHINE DEPENDENT { a (31) }; RegisterClass: TYPE ~ MACHINE DEPENDENT { none (LOOPHOLE[TargetArchitecture.RegisterClass.none]), globals, globalsAndIns, globalsInsAndFloats, globalsInsFloatsOutsAndLocals, nextAvailable, all (LOOPHOLE[TargetArchitecture.RegisterClass.all]) } _ nullRegisterClass; nullRegisterClass: RegisterClass ~ RegisterClass.none; Format: TYPE ~ { Format3rArith, Format2rsi, Format2rui, Format2rd, Format2rArith, Format3rS, FormatBranch, FormatBOnCond, FormatBOnCondCount, FormatCmp, FormatCmpi, FormatCmpui, FormatCount, FormatCondRegAnd, FormatFl3rArith, FormatFl2rArith, FormatFlCmp, FormatFlMul, FormatFlMulAd, FormatLoad, FormatLoadFl, FormatLoadFlIndex, FormatLoadi, FormatLoadui, FormatMask, FormatMove, FormatMoveToCR, FormatMoveFromCR, FormatMoveFl, FormatMoveSPR, FormatMoveToCRField, FormatMoveToFPSCRBit, FormatMoveToFPSCRField, FormatMoveToFPSCRFieldImm, FormatRotateImmMask, FormatUnknown }; Ai: PROCEDURE [rt: Register, ra: Register, si: SI] RETURNS [RS6000Instruction]; B: PROCEDURE [pc: RS6000Address, to: RS6000Address, abs, link: BOOLEAN] RETURNS [RS6000Instruction]; Brl: PROCEDURE [] RETURNS [RS6000Instruction]; Bctr: PROCEDURE [] RETURNS [RS6000Instruction]; Cror: PROCEDURE [bt: CCBitPosition, ba: CCBitPosition, bb: CCBitPosition, lk: BOOLEAN] RETURNS [RS6000Instruction]; L: PROCEDURE [rt: Register, offset: Disp16, ra: Register] RETURNS [RS6000Instruction]; Lil: PROCEDURE [rt: Register, low: SI] RETURNS [RS6000Instruction]; Liu: PROCEDURE [rt: Register, upper: UI] RETURNS [RS6000Instruction]; Lm: PROCEDURE [rt: Register, offset: Disp16, ra: Register] RETURNS [RS6000Instruction]; Mfspr: PROCEDURE [rt: Register, spr: SpecialRegister, rc: BOOLEAN] RETURNS [RS6000Instruction]; Mtspr: PROCEDURE [rt: Register, spr: SpecialRegister, rc: BOOLEAN] RETURNS [RS6000Instruction]; Mfcr: PROCEDURE [rs: Register, rc: BOOLEAN] RETURNS [RS6000Instruction]; Mtcrf: PROCEDURE [fxm: FXM, rs: Register, rc: BOOLEAN] RETURNS [RS6000Instruction]; Noop: PROCEDURE [] RETURNS [RS6000Instruction]; OrLConst: PROCEDURE [ra: Register, rs: Register, ui: UI] RETURNS [RS6000Instruction]; OrUConst: PROCEDURE [ra: Register, rs: Register, ui: UI] RETURNS [RS6000Instruction]; St: PROCEDURE [rs: Register, offset: Disp16, ra: Register] RETURNS [RS6000Instruction]; Stm: PROCEDURE [rs: Register, offset: Disp16, ra: Register] RETURNS [RS6000Instruction]; Stu: PROCEDURE [rs: Register, offset: Disp16, ra: Register] RETURNS [RS6000Instruction]; Si: PROCEDURE [rt: Register, ra: Register, si: SI] RETURNS [RS6000Instruction]; Relocate: PROCEDURE [ instruction: RS6000Instruction, from: RS6000Address, to: RS6000Address] RETURNS [RS6000Instruction]; IsNoopInstruction: PROCEDURE [instruction: RS6000Instruction] RETURNS [BOOLEAN]; NeedsRelocation: PROCEDURE [instruction: RS6000Instruction] RETURNS [BOOLEAN]; IsCallInstruction: PROCEDURE [instruction: RS6000Instruction] RETURNS [BOOLEAN]; GetOp: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [Op]; GetSubOp19: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [SubOpFor19]; GetSubOp31withoutOE: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [SubOpFor31withoutOE]; GetSubOp31withOE: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [SubOpFor31withOE]; GetSubOp3r63: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [FSubOp3r63]; GetSubOp2r63: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [FSubOp2r63]; GetDisp14: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [Disp14]; GetDisp24: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [Disp24]; SetDisp14: PUBLIC PROCEDURE [instruction: RS6000Instruction, disp14: Disp14] RETURNS [RS6000Instruction]; SetDisp24: PUBLIC PROCEDURE [instruction: RS6000Instruction, disp24: Disp24] RETURNS [RS6000Instruction]; High: PUBLIC PROCEDURE [value: CARD32] RETURNS [UI]; Low: PUBLIC PROCEDURE [value: CARD32] RETURNS [UI]; SetOp: PUBLIC PROCEDURE [instruction: RS6000Instruction, op: Op] RETURNS [RS6000Instruction]; IsNullRS6000Address: PROCEDURE [address: RS6000Address] RETURNS [BOOLEAN]; RS6000AddressFromDisplacement: PROCEDURE [ address: RS6000Address, displacement: TargetArchitecture.Displacement] RETURNS [RS6000Address]; DisplacementFromRS6000Addresses: PROCEDURE [ here: RS6000Address, there: RS6000Address] RETURNS [TargetArchitecture.Displacement]; IsNullRS6000Instruction: PROCEDURE [instruction: RS6000Instruction] RETURNS [BOOLEAN]; NextRS6000Instruction: PROCEDURE [pc: RS6000Address] RETURNS [RS6000Address]; PrevRS6000Instruction: PROCEDURE [pc: RS6000Address] RETURNS [RS6000Address]; RS6000AddressFromTargetAddress: PROCEDURE [address: TargetArchitecture.Address] RETURNS [RS6000Address]; TargetAddressFromRS6000Address: PROCEDURE [ rs6000Address: RS6000Address] RETURNS [TargetArchitecture.Address]; RS6000ContentsFromTargetContents: PROCEDURE [ contents: TargetArchitecture.Contents] RETURNS [RS6000Contents]; TargetContentsFromRS6000Contents: PROCEDURE [ contents: RS6000Contents] RETURNS [TargetArchitecture.Contents]; RS6000InstructionFromTargetInstruction: PROCEDURE [ instruction: TargetArchitecture.Instruction] RETURNS [RS6000Instruction]; TargetInstructionFromRS6000Instruction: PROCEDURE [ instruction: RS6000Instruction] RETURNS [TargetArchitecture.Instruction]; RS6000RegisterClassFromTargetRegisterClass: PROCEDURE [ registerClass: TargetArchitecture.RegisterClass] RETURNS [RegisterClass]; TargetRegisterClassFromRS6000RegisterClass: PROCEDURE [ registerClass: RegisterClass] RETURNS [TargetArchitecture.RegisterClass]; CantRelocate: ERROR; CantReach: ERROR; NullRS6000Address: ERROR; NullRS6000Instruction: ERROR; }. 0 RS6000Architecture.mesa Copyright 1991, 1992, 1993 by Xerox Corporation. All rights reserved. Peter B. Kessler, April 9, 1990 3:25:39 pm PDT(form comes from SPARCArchitecture) Architectural information about the RS6000. Udagawa, September 18, 1991 6:51 pm PDT Laurie Horton, February 24, 1993 8:24 pm PST Katsuyuki Komatsu March 5, 1992 1:15 pm PST Types. Miscellaneous Instruction Formats Registers Fixed Point Processor Registers There are 18 dubble words of floating registers, and 32 words of general registers at the stack. There are eight words of argument at least. Link area has six words for saved cr, saved lr, saved TOC, and etc. The stack has to be double-word aligned. Floatingpoint processor Branch Processor TYPE Components Miscellaneous Miscellaneous ProcessorRegister: TYPE ~ {pc, npc --and probably others-- }; Procedures. Code Assembly. ! CantReach ! CantReach ! CantReach Relocates an instruction from the given address to another address. ! CantRelocate Instruction Classification. Checks whether the instruction is a noop. Checks whether the instruction has pc-relative operands. Checks whether the instruction is a call instruction. Field accessors for instructions. GetFormat: PUBLIC PROCEDURE [instruction: RS6000Instruction] RETURNS [Format]; Constant and Displacement caliculation Field assigners for instructions. Miscellaneous. Tests if its argument is the null RS6000Address. Tests if its argument is the null RS6000Instruction. Returns the address of the next instruction. Returns a pointer to the previous instruction. Errors. Given for attempts to relocate an instruction too far, etc. Given for attempts to generate pc-relative instructions that don't reach. Given during code generation when null addresses are supplied. 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