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<<SparcInstruction.mesa>>
<<Copyright Ó 1991, 1992 by Xerox Corporation.  All rights reserved.>>
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    SparcInstruction: CEDAR DEFINITIONS
    ~ BEGIN

        BIT2: TYPE ~ [0..2**2);
        BIT4: TYPE ~ [0..2**4);
        BIT8: TYPE ~ [0..2**8);
        BIT9: TYPE ~ [0..2**9);
        BIT13: TYPE ~ [0..2**13);
        BIT22: TYPE ~ [0..2**22);
        BIT25: TYPE ~ [0..2**25);
        BIT30: TYPE ~ [0..2**30);

        Register: TYPE ~ [0..2**5);

        InstructionOverlay: TYPE ~ MACHINE DEPENDENT RECORD [
            SELECT OVERLAID * FROM
                op => [op: BIT2, opfill: BIT30 ¬ 0],
                rd => [rdpad: BIT2 ¬ 0, rd: Register, rdfill: BIT25 ¬ 0],
                regop => [regop2: BIT2 ¬ 2, reg: Register, regop: RegOp, rs1: Register, s2: Src2],
                ldstop => [ldstop2: BIT2 ¬ 3, ldstreg: Register, ldstop: LdStOp, ldstrs1: Register, ldsts2: Src2],
                cond => [condop: BIT2 ¬ 0, annul: BOOL, cond: Bicc, brop: BrOp, disp22: BIT22],
                fcond => [fcondop: BIT2 ¬ 0, fannul: BOOL, fcond: FBicc, fbrop: BrOp ¬ FBicc, fdisp22: BIT22 ¬ 0],
                ccond => [ccondop: BIT2 ¬ 0, cannul: BOOL, ccond: CBccc, cbrop: BrOp ¬ CBccc, cdisp22: BIT22 ¬ 0],
                sethi => [shiop: BIT2 ¬ 0, shird: Register, shibrop: BrOp ¬ sethi, imm22: BIT22],
                call => [callop: BIT2 ¬ 1, disp30: BIT30],
                fpop1 => [fp1op2: BIT2 ¬ 2, fp1rd: Register, fpop1: RegOp ¬ FPop1, fp1rs1: Register, opf1: BIT9, fp1rs2: Register],
                fpop2 => [fp2op2: BIT2 ¬ 2, fp2rd2: Register, fpop2: RegOp ¬ FPop2, fp2rs1: Register, opf2: BIT9, fp2rs2: Register],
                ENDCASE
            ];

        Src2: TYPE ~ MACHINE DEPENDENT RECORD [
            SELECT i: * FROM
                zero => [asi: BIT8, rs2: Register],
                one => [signed13: BIT13],
                ENDCASE
            ];

        LdStOp: TYPE ~ MACHINE DEPENDENT {
            ld(0), ldub(1), lduh(2), ldd(3), st(4), stb(5), sth(6), std(7),
            (8), ldsb(9), ldsh(10), (11), (12), ldstub(13), (14), swap(15),
            lda(16), lduba(17), lduha(18), ldda(19), sta(20), stba(21), stha(22), stda(23),
            (24), ldsba(25), ldsha(26), (27), (28), ldstuba(29), (30), swapa(31),
            ldf(32), ldfsr(33), (34), lddf(35), stf(36), stfsr(37), stdfq(38), stdf(39),
            (40), (41), (42), (43), (44), (45), (46), (47),
            ldc(48), ldcsr(49), (50), lddc(51), stc(52), stcsr(53), stdcq(54), stdc(55),
            (56), (57), (58), (59), (60), (61), (62), (63)
            };

        RegOp: TYPE ~ MACHINE DEPENDENT {
            add(0), and(1), or(2), xor(3), sub(4), andn(5), orn(6), xnor(7),
            addx(8), (9), (10), (11), subx(12), (13), (14), (15),
            addcc(16), andcc(17), orcc(18), xorcc(19), subcc(20), andncc(21), orncc(22), xnorcc(23),
            addxcc(24), (25), (26), (27), subxcc(28), (29), (30), (31),
            taddcc(32), tsubcc(33), taddcctv(34), tsubcctv(35), mulscc(36), sll(37), srl(38), sra(39),
            rdy(40), rdpsr(41), rdwim(42), rdtbr(43), (44), (45), (46), (47),
            wry(48), wrpsr(49), wrwim(50), wrtbr(51), FPop1(52), FPop2(53), CPop1(54), CPop2(55), 
            jmpl(56), rett(57), te(58), iflush(59), save(60), restore(61), (62), (63)
            };

        Bicc: TYPE ~ MACHINE DEPENDENT {
            n, e, le, l, leu, cs, m, vs, a, ne, g, ge, gu, cc, p, vc
            };

        FBicc: TYPE ~ BIT4; -- NB different from integer conditions
        CBccc: TYPE ~ BIT4; -- Coprocessor conditions

        BrOp: TYPE ~ MACHINE DEPENDENT {
            unimp(0), (1), Bicc(2), (3), sethi(4), (5), FBicc(6), CBccc(7)
            };


    END.