/* @(#)drreg.h 1.2 88/09/15 SMI */
/*
* Copyright (c) 1986 by Sun Microsystems, Inc.
*/
/*
* All statements, comments and code, concerning the MDB Systems DR11W board
* should not be regarded actual and were not tested.
*/
/*
* This file contains the device structure and control/status register
* definitions for the DR11-W driver which supports Ikon and MDB Systems
* VMEbus and Multibus boards.
*/
#ifdef KERNEL /* From ifdef to endif is used by kernel ONLY */
#ifdef sun4
/*
* needed on Sun-4 due to wrong inplementation of pritospl in psl.h
*/
#undef pritospl
#define pritospl(n) (SR←SMODE|((n)<<8))
#endif sun4
/*
* The device structure
*/
struct drdevice {
#ifdef MDB
u←short dr←lo←cur←wc; /* 00) low current word count (rw) */
u←short dr←start; /* 02) low bus address register (A1-A15) (rw) */
#define dr←lo←cur←adrs dr←start
u←short dr←status; /* 04) status (r) & command (w) register */
u←short dr←data; /* 06) data register (rw) */
u←short dr←hi←sa; /* 08) high bus address reg. (A16-A23) (rw) */
#define dr←hi←cur←adrs dr←hi←sa
u←short addrmod; /* 0A) Address modifier/vector intr. (rw) */
u←short dr←sfr; /* 0C) MDB Special Function Register (rw) */
#define dr←pulse dr←sfr /* Low bits of MDB's match Ikon's pulse reg */
#else
u←short dr←status; /* 00) status(r) control(w) register */
u←short dr←data; /* 02) data register (rw) */
u←short addrmod; /* 04) addr mod and vector int (rw) VME only */
u←short dr←pulse; /* 06) pulse commands (w) */
u←short filler[4]; /* 08-0E) not used */
u←short dr←dmacntrl; /* 10) dma control register (w) MB only */
u←short dr←start; /* 12) low dma start addr(w)
low dma control reg(r) */
u←short dr←lo←cur←wc; /* 14) low current word count(rw) */
u←short dr←lo←cur←adrs; /* 16) low current address (r) */
u←short filler1; /* 18) not used */
u←short dr←hi←sa; /* 1A) hi start addr (w) hi cntl reg (r) */
u←short dr←hi←wc; /* 1C) hi word count(rw) MB only */
u←short dr←hi←cur←adrs; /* 1E) hi current addr(r) */
#endif
};
/*
* Aliases for the above commands
*/
#define dr←cntrl dr←status
/*
* Definition of address modifier
*/
#define DR←ADDR←MOD 0x3D00 /* address modifier for VME shifted to its
left byte place (in a short word) */
/*
* Miscelenious constant definitions
*/
#define DR←1←MINUTE 60*hz /* number of clock ticks per minute */
#define DR←IVEC←MASK 0xff /* interrupt vector mask */
#define DR←MBUS←READY 1 /* Ikon Multibus board ready bit except DR←RDY
/* which should also be set when ready */
#ifdef MDB
#define DR←HA←SHIFT 16 /* shift count of high portion of address bits*/
#define DR←HA←MASK 0xff /* mask for high portion of address bits */
#define DR←LA←SHIFT 0 /* shift count of low portion of address bits */
#define DR←LA←MASK 0xfffe /* mask for low portion of address bits */
#else
#define DR←HA←SHIFT 17 /* shift count of high portion of address bits*/
#define DR←HA←MASK 0x7f /* mask for high portion of address bits */
#define DR←LA←SHIFT 1 /* shift count of low portion of address bits */
#define DR←LA←MASK 0xffff /* mask for low portion of address bits */
#endif
#define DR←LWC←MASK 0xffff /* mask for low portion of byte count */
#define DR←HWC←SHIFT 16 /* shoft count for high portion of word count */
#define DR←HWC←MASK 0xff /* mask for high portion of word count */
#define DR←EXCL←OPEN←BIAS 100 /* exclusive open is done by adding this
number to the minor device number */
#define DR←MAX←COLD←DELAYS 4 /* max times to wait dr←delay for the board
to be ready after coldstart */
/*
* From the endif on can be used by user programs
*/
#endif
/*
* Defintionion of the control and status bits
*/
#ifdef MDB
#define DR←RSTINTR 0xE000 /* Reset/clear interrupts (Bits 15 14 13) (w) */
#define DR←ERROR 0x8000 /* Bit 15 - Error flag set (r) */
#define DR←INTR 0x6000 /* Interrupt flag bits - 14 & 13 (w) */
#define DR←BERR 0x4000 /* Bit 14 - Clear BERR (w) ; BERR FF (r) */
#define DR←ATTF 0x2000 /* Bit 13 - Clear ATTN FF (w) ; ATTN FF (r) */
#define DR←INIT 0x1000 /* Bit 12 - Initialize module (w) */
#define DR←ATTH DR←INIT /* Current state of ATTN H from external (r) */
#define DR←STAT 0x0E00 /* All status bits */
#define DR←STTA 0x0800 /* Bit 11 - State of Status A input (r) */
#define DR←STTB 0x0400 /* Bit 10 - State of Status B input (r) */
#define DR←STTC 0x0200 /* Bit 9 - State of Status C input (r) */
#define DR←CYCL 0x0100 /* Bit 8 - enable DMA cycle (w) */
#define DR←RDY 0x0080 /* Bit 7 - Interface ready (r) */
#define DR←DONE DR←RDY /* DMA done (r) (I think?) */
#define DR←IENB 0x0040 /* Bit 6 - Interrupt enable (w) */
#define DR←BDLT 0x0020 /* Bit 5 - State of Burst Data Late (rw) */
#define DR←CNTL 0x0010 /* Bit 4 - State of of C1 CNTL signal (r) */
#define DR←FCN3 0x0008 /* Bit 3 - FUNCT 3 (rw) */
#define DR←FCN2 0x0004 /* Bit 2 - FUNCT 2 (rw) - also drives ACLO/FUNCT 2 in external device */
#define DR←FCN1 0x0002 /* Bit 1 - FUNCT 1 (rw) */
#define DR←GO 0x0001 /* Bit 1 - start DMA (w) */
#else
#define DR←RSTINTR 0xE000 /* Reset interupts */
#define DR←INTR 0xC000 /* Interupt flag bits */
#define DR←DMAF 0x8000 /* Reset DMA end flag (w)*/
#define DR←DONE DR←DMAF /* DMA done flag (r) */
#define DR←ATTF 0x4000 /* Reset ATTF flag (w) ATTF flag (r)*/
#define DR←ATTH 0x2000 /* ATTH flag (r) */
#define DR←WPERR DR←ATTH /* Reset PERR (w) */
#define DR←INIT 0x1000 /* Master clear and pulse init (w) */
#define DR←RPERR DR←INIT /* PERR flag (r) */
#define DR←STAT 0x0E00 /* status bits (r) */
#define DR←STTA 0x0800 /* State of status A input (r) */
#define DR←STTB 0x0400 /* State of status B input (r) */
#define DR←STTC 0x0200 /* State of status C input (r) */
#define DR←CYCL 0x0100 /* Force DMA cycle (w) */
#define DR←RDY 0x0080 /* Interface ready (r) */
#define DR←IENB 0x0040 /* Interupt enable/disable bit (rw) */
#define DR←FCN3 0x0008 /* FCN3 (rw) */
#define DR←FCN2 0x0004 /* FCN2 (rw) */
#define DR←FCN1 0x0002 /* FCN1 (rw) */
#define DR←GO 0x0001 /* Start DMA (w) */
#endif
#define MBRA←READY DR←GO /* Multibus flag (r) These are or'd with the*/
#define VMERA←READY 0x0000 /* VME flag (r) user given ready bits */
/*
* Ioctl parameter definitions
*/
#define DR←IOCSIG ←IOW(r,2,struct sigdata)/* Signal on intr */
#define DR←IOCNOSIG ←IO(r,3) /* Turn off IOCSIG */
#define DR←IOCRSTAT ←IOR(r,4,u←short) /* Get status */
#define DR←IOCWSTAT ←IOW(r,5,u←short) /* Put status */
#define DR←IOCSONINT ←IOW(r,6,u←short) /* Set this on intr */
#define DR←IOCISREAD ←IOW(r,7,u←short) /* This is a read */
#define DR←IOCISWRITE ←IOW(r,8,u←short) /* This is a write */
#define DR←IOCONREAD ←IOW(r,9,u←short) /* Set in intr upon read */
#define DR←IOCONWRITE ←IOW(r,10,u←short) /* Set in intr upon write */
#define DR←IOCISREADY ←IOW(r,11,u←short) /* This is the ready state */
#define DR←IOCISERROR ←IOW(r,12,u←short) /* This is the error state */
#define DR←IOCRESET ←IOW(r,13,u←short) /* This is the reset command */
#define DR←IOCWARM ←IOW(r,14,u←short) /* This is the warm start cmd */
#define DR←IOCDOCOLD ←IO(r,15) /* Do a reset */
#define DR←IOCDOWARM ←IO(r,16) /* Do a wrm start */
#define DR←IOCRDONE ←IOW(r,17,u←short) /* Read done */
#define DR←IOCWDONE ←IOW(r,18,u←short) /* Write done */
#define DR←IOCISTAT ←IOR(r,19,u←short) /* Status as of last intr */
#define DR←IOCONERROR ←IOW(r,20,u←short) /* Set in intr upon error */
#define DR←IOCDELAY ←IOW(r,21,int) /* Set delay */
#define DR←IOCLATCHWARM ←IOW(r,22,int) /* Do Cold if Warm fails */
#define DR←IOCWDATA ←IOW(r,23,u←short) /* Set Data register */
#define DR←IOCRDATA ←IOR(r,24,u←short) /* Read Data register */
#define DR←IOCPULSE ←IOW(r,25,u←short) /* Set Pulse register */
#define DR←IOCPID ←IOR(r,26,int) /* Get PID of proc to sig*/
#define DR←IOCPAUSE ←IOW(r,27,u←short) /* This signals a pause */
#define DR←IOCPISW ←IOW(r,28,u←short) /* If a write pulse this */
#define DR←IOCPISR ←IOW(r,29,u←short) /* If a read pulse this */
/*
* For DR←IOCSIG
*/
struct sigdata {
int pid; /* signal this process */
int sig; /* with this signal */
};
#define DR←NO←DMA←KICK 0x1000000 /* send signal to user process only on */
/* attn interrupts (dma completion wakeups */
/* read/write user process */
/*
* Ioctl defaults
*/
#define DR←SIGNAL SIGHUP
#define DR←ONINT DR←RSTINTR
#define DR←ISREAD (0x0000 | DR←RSTINTR | DR←GO | DR←IENB)
#define DR←ISWRITE (0x0000 | DR←RSTINTR | DR←GO | DR←IENB)
#define DR←ONREAD DR←STTC
#define DR←ONWRITE 0x0000
#define DR←ISREADY DR←RDY
#define DR←ISERROR (DR←ATTF | 0x0000)
#define DR←ISRESET (DR←INIT | DR←RSTINTR | DR←GO)
#define DR←ISWARM (DR←RSTINTR | DR←GO)
#ifdef MDB
#define DR←RDONE (DR←RDY | DR←IENB)
#define DR←WDONE (DR←STTA | DR←STTC | DR←RDY | DR←IENB)
#else
/*
* The following should be changed to default to Ikon conventions
*
* #define DR←RDONE ( DR←DONE | DR←RDY )
* #define DR←WDONE ( DR←DONE | DR←RDY )
*
*/
#define DR←RDONE (DR←ATTF | DR←STTC)
#define DR←WDONE DR←DMAF
#endif
#define DR←ONERROR DR←ISWARM
#define DR←LATCHWARM 1
#define DR←DELAY 9000000
#define DR←PAUSE DR←STTB
#define DR←PISW 0x0000
#define DR←PISR 0x0000
#define DR←IS10089 1