DIRECTORY
TargetArchitecture;

SPARCArchitecture: CEDAR DEFINITIONS ~ {
SPARCAddress: TYPE[SIZE[CARD32]];
nullSPARCAddress: SPARCAddress ~ LOOPHOLE[FIRST[CARD32]];
SPARCContents: TYPE[SIZE[CARD32]];
SPARCInstruction: TYPE[SIZE[CARD32]];
nullSPARCInstruction: SPARCInstruction ~ LOOPHOLE[CARD32[0]];

Format1: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ Op.call,
disp30MS	(0:2..15):	Unbiased30MS ฌ,
disp30LS	(0:16..31):	Unbiased30LS ฌ
];
Format2Imm22: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
rd	(0:2..6):	Register ฌ,
op2	(0:7..9):	Op2 ฌ,
imm22MS	(0:10..15):	Imm22MS ฌ,
imm22LS	(0:16..31):	Imm22LS ฌ
];
Format2Disp22: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
a	(0:2..2):	Annul ฌ,
cond	(0:3..6):	Cond ฌ,
op2	(0:7..9):	Op2 ฌ,
disp22MS	(0:10..15):	Unbiased22MS ฌ,
disp22LS	(0:16..31):	Unbiased22LS ฌ
];
Format3asi: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
rd	(0:2..6):	Register ฌ,
op3	(0:7..12):	Op3 ฌ,
rs1MS	(0:13..15):	RegisterMS ฌ,
rs1LS	(0:16..17):	RegisterLS ฌ,
i	(0:18..18):	I ฌ I.useRS2,
asi	(0:19..26):	ASI ฌ,
rs2	(0:27..31):	Register ฌ
];
Format3Simm13: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
rd	(0:2..6):	Register ฌ,
op3	(0:7..12):	Op3 ฌ,
rs1MS	(0:13..15):	RegisterMS ฌ,
rs1LS	(0:16..17):	RegisterLS ฌ,
i	(0:18..18):	I ฌ I.useSimm13,
simm13	(0:19..31):	Unbiased13 ฌ
];
Format3OpF: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
rd	(0:2..6):	Register ฌ,
op3	(0:7..12):	Op3 ฌ,
rs1MS	(0:13..15):	RegisterMS ฌ,
rs1LS	(0:16..17):	RegisterLS ฌ,
opf	(0:18..26):	OpF ฌ,
rs2	(0:27..31):	Register ฌ
];
Format3TiccRs2: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
  pad1	(0:2..2):	Ignored1 ฌ Ignored1.ignored,
cond	(0:3..6):	Cond ฌ,
op3	(0:7..12):	Op3 ฌ,
rs1MS	(0:13..15):	RegisterMS ฌ,
rs1LS	(0:16..17):	RegisterLS ฌ,
i	(0:18..18):	I ฌ I.useRS2,
  pad2	(0:19..26):	Ignored8 ฌ Ignored8.ignored,
rs2	(0:27..31):	Register ฌ
];
Format3TiccSimm13: TYPE ~ MACHINE DEPENDENT RECORD [
op	(0:0..1):	Op ฌ,
  pad1	(0:2..2):	Ignored1 ฌ Ignored1.ignored,
cond	(0:3..6):	Cond ฌ,
op3	(0:7..12):	Op3 ฌ,
rs1MS	(0:13..15):	RegisterMS ฌ,
rs1LS	(0:16..17):	RegisterLS ฌ,
i	(0:18..18):	I ฌ I.useSimm13,
simm13	(0:19..31):	Unbiased13 ฌ
];
FormatUnknown: TYPE ~ RECORD [
bits:	SPARCInstruction ฌ
];
Op: TYPE ~ MACHINE DEPENDENT {
branch (00B), call (01B), other2 (02B), other3 (03B)
};

Op2: TYPE ~ MACHINE DEPENDENT {
unimplemented0 (00B), bicc (02B), sethi (04B), fbfcc (06B), cbccc (07B)
};

Op3: TYPE ~ MACHINE DEPENDENT {
first (000B), last (077B)
};

Op10Op3: TYPE ~ MACHINE DEPENDENT {
add (000B), or (002B), sub (004B), 
jmpl (070B), rett (071B), 
save (074B), restore (075B), 
unimplemented77 (077B)
};

Op11Op3: TYPE ~ MACHINE DEPENDENT {
ld (000B), st (004B), unimplemented77 (077B)
};

Register: TYPE ~ MACHINE DEPENDENT {
global0 (0),	global1,	global2,	global3,	global4,	global5,	global6,	global7,
out0 (8),	out1,	out2,	out3,	out4,	out5,	out6,	out7,
local0 (16),	local1,	local2,	local3,	local4,	local5,	local6,	local7,
in0 (24),	in1,	in2,	in3,	in4,	in5,	in6,	in7
};
stackPointer: Register ~ Register.out6;
stackPointerOffset: NAT ~ 16 * BYTES[TargetArchitecture.Contents];
stackAllocationForCallee: NAT ~ 8 * BYTES[TargetArchitecture.Contents];
stackAllocationUnit: NAT ~ 2 * BYTES[TargetArchitecture.Contents];
framePointer: Register ~ Register.in6;
returnAddress: Register ~ Register.in7;

FloatingRegister: TYPE ~ MACHINE DEPENDENT {
float0 (0),	float1,	float2,	float3,	float4,	float5,	float6,	float7,
float8,	float9,	float10,	float11,	float12,	float13,	float14,	float15,
float16,	float17,	float18,	float19,	float20,	float21,	float22,	float23,
float24,	float25,	float26,	float27,	float28,	float29,	float30,	float31
};

RegisterClass: TYPE ~ MACHINE DEPENDENT {
none (LOOPHOLE[TargetArchitecture.RegisterClass.none]), 
globals, globalsAndIns, globalsInsAndFloats, globalsInsFloatsOutsAndLocals, 
nextAvailable,
all (LOOPHOLE[TargetArchitecture.RegisterClass.all])
} ฌ nullRegisterClass;
nullRegisterClass: RegisterClass ~ RegisterClass.none;

Annul: TYPE ~ MACHINE DEPENDENT {
execute (0), annul (1)
};

Cond: TYPE ~ MACHINE DEPENDENT {
never (00H), equal (01H), lessOrEqual (02H), less (03H), 
lessOrEqualUnsigned (04H), carrySet (05H), negative (06H), overflowSet (07H), 
always (08H), notEqual (09H), greater (0AH), greaterOrEqual (0BH), 
greaterUnsigned (0CH), carryClear (0DH), positive (0EH), overflowClear (0FH)
};

Disp30: TYPE ~ INT32;		-- this is not a biased subrange, now!
firstDisp30: Disp30 ~ -536870912;
lastDisp30: Disp30 ~ +536870911;
Imm22: TYPE ~ CARD32;
firstImm22: Imm22 ~ 0;
lastImm22: Imm22 ~ 4194303;
Imm22MS: TYPE ~ CARDINAL [0..63];
Imm22LS: TYPE ~ CARDINAL [0..65535];
Disp22: TYPE ~ INT32;		-- this is not a biased subrange, now!
firstDisp22: Disp22 ~ -2097152;
lastDisp22: Disp22 ~ +2097151;
Simm13: TYPE ~ INTEGER [-4096..4095];
firstSimm13: Simm13 ~ -4096;
lastSimm13: Simm13 ~ 4095;
Imm10: TYPE ~ CARDINAL [0..1023];
firstImm10: Imm10 ~ 0;
lastImm10: Imm10 ~ 1023;

Unbiased30: TYPE ~ CARD32;
firstUnbiased30: Unbiased30 ~ 0;
lastUnbiased30: Unbiased30 ~ 1073741823;
Unbiased30MS: TYPE ~ CARDINAL [0..16383];
Unbiased30LS: TYPE ~ CARDINAL [0..65535];
Unbiased22: TYPE ~ CARD32;
firstUnbiased22: Unbiased22 ~ 0;
lastUnbiased22: Unbiased22 ~ 4194303;
Unbiased22MS: TYPE ~ CARDINAL [0..63];
Unbiased22LS: TYPE ~ CARDINAL [0..65535];
Unbiased13: TYPE ~ CARDINAL [0..8191];
firstUnbiased13: Unbiased13 ~ 0;
lastUnbiased13: Unbiased13 ~ 8191;
RegisterMS: TYPE ~ CARDINAL [0..7];
RegisterLS: TYPE ~ CARDINAL [0..3];

I: TYPE ~ MACHINE DEPENDENT {
useRS2 (0), useSimm13 (1)
};
ASI: TYPE ~ CARDINAL [0..255];
OpF: TYPE ~ MACHINE DEPENDENT {
unimplemented000 (000B), unimplemented777 (0777B)
};

Ignored1: TYPE ~ MACHINE DEPENDENT {
ignored (0), (1)
} ฌ Ignored1.ignored;
Ignored8: TYPE ~ MACHINE DEPENDENT {
ignored (0), (255)
} ฌ Ignored8.ignored;

Format: TYPE ~ {
format1, format2, format3, format2imm22, format2disp22, format3asi, format3simm13, format3opf
};
ProcessorRegister: TYPE ~ {pc, npc --and probably others-- };

Noop: PROCEDURE [] RETURNS [SPARCInstruction];

Ld: PROCEDURE [base: Register, offset: Simm13, dest: Register]
RETURNS [SPARCInstruction];

St: PROCEDURE [source: Register, base: Register, offset: Simm13]
RETURNS [SPARCInstruction];

Sethi: PROCEDURE [hi: Imm22, dest: Register] RETURNS [SPARCInstruction];

BAa: PROCEDURE [pc: SPARCAddress, to: SPARCAddress] 
RETURNS [SPARCInstruction];

SaveConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

RestoreConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

AddConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

SubConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

OrConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

Call: PROCEDURE [pc: SPARCAddress, to: SPARCAddress] 
RETURNS [SPARCInstruction];

JmplConst: PROCEDURE [source: Register, constant: Simm13, dest: Register]
RETURNS [SPARCInstruction];

Relocate: PROCEDURE [
instruction: SPARCInstruction, 
from: SPARCAddress, 
to: SPARCAddress] 
RETURNS [SPARCInstruction];

IsDelayedControlTransfer: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

IsNoopInstruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];
NeedsRelocation: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

IsCallInstruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

IsDelayedBranchInstruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

IsJmplO7Instruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

IsJmplG0Instruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];

GetFormat: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Format];
GetOp: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Op];
GetDisp30: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Disp30];
GetRd: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Register];
GetOp2: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Op2];
GetImm22: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Imm22];
GetAnnul: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Annul];
GetCond: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Cond];
GetDisp22: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Disp22];
GetRs1: PUBLIC PROCEDURE [instinstruction: SPARCInstruction] 
RETURNS [Register];
RegisterFromRegisterML: PUBLIC PROCEDURE [
registerMS: RegisterMS, registerLS: RegisterLS]
RETURNS [Register];
GetI: PUBLIC PROCEDURE [instinstruction: SPARCInstruction] 
RETURNS [I];
GetASI: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [ASI];
GetRs2: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Register];
GetSimm13: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Simm13];
GetOpF: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [OpF];
GetOp3: PUBLIC PROCEDURE [instruction: SPARCInstruction] 
RETURNS [Op3];
Op10Op3FromOp3: PUBLIC PROCEDURE [op3: Op3] RETURNS [Op10Op3];
Op11Op3FromOp3: PUBLIC PROCEDURE [op3: Op3] RETURNS [Op11Op3];
Disp30FromUnbiased30: PUBLIC PROCEDURE [
unbiased30MS: Unbiased30MS, unbiased30LS: Unbiased30LS] 
RETURNS [Disp30];
Disp22FromUnbiased22: PUBLIC PROCEDURE [
unbiased22MS: Unbiased22MS, unbiased22LS: Unbiased22LS] 
RETURNS [Disp22];
Imm22FromImm22ML: PUBLIC PROCEDURE [imm22MS: Imm22MS, imm22LS: Imm22LS] 
RETURNS [Imm22];
Imm22MSFromImm22: PUBLIC PROCEDURE [imm22: Imm22] 
RETURNS [Imm22MS];
Imm22LSFromImm22: PUBLIC PROCEDURE [imm22: Imm22] 
RETURNS [Imm22LS];
Simm13FromUnbiased13: PUBLIC PROCEDURE [unbiased13: Unbiased13] 
RETURNS [Simm13];
Hi: PUBLIC PROCEDURE [value: CARD32] RETURNS [Imm22];
Lo: PUBLIC PROCEDURE [value: CARD32] RETURNS [Imm10];
HiLo: PUBLIC PROCEDURE[hi: Imm22, lo: Imm10] RETURNS [CARD32];
SetOp: PUBLIC PROCEDURE [instruction: SPARCInstruction, op: Op] 
RETURNS [SPARCInstruction];
SetDisp30: PUBLIC PROCEDURE [instruction: SPARCInstruction, disp30: Disp30] 
RETURNS [SPARCInstruction];
SetRd: PUBLIC PROCEDURE [instruction: SPARCInstruction, rd: Register] 
RETURNS [SPARCInstruction];
SetOp2: PUBLIC PROCEDURE [instruction: SPARCInstruction, op2: Op2] 
RETURNS [SPARCInstruction];
SetImm22: PUBLIC PROCEDURE [instruction: SPARCInstruction, imm22: Imm22] 
RETURNS [SPARCInstruction];
SetAnnul: PUBLIC PROCEDURE [instruction: SPARCInstruction, annul: Annul] 
RETURNS [SPARCInstruction];
SetCond: PUBLIC PROCEDURE [instruction: SPARCInstruction, cond: Cond] 
RETURNS [SPARCInstruction];
SetDisp22: PUBLIC PROCEDURE [instruction: SPARCInstruction, disp22: Disp22] 
RETURNS [SPARCInstruction];
SetRs1: PUBLIC PROCEDURE [instruction: SPARCInstruction, rs1: Register] 
RETURNS [SPARCInstruction];
RegisterMSFromRegister: PUBLIC PROCEDURE [register: Register]
RETURNS [RegisterMS];
RegisterLSFromRegister: PUBLIC PROCEDURE [register: Register]
RETURNS [RegisterLS];
SetI: PUBLIC PROCEDURE [instruction: SPARCInstruction, i: I] 
RETURNS [SPARCInstruction];
SetASI: PUBLIC PROCEDURE [instruction: SPARCInstruction, asi: ASI] 
RETURNS [SPARCInstruction];
SetRs2: PUBLIC PROCEDURE [instruction: SPARCInstruction, rs2: Register] 
RETURNS [SPARCInstruction];
SetSimm13: PUBLIC PROCEDURE [instruction: SPARCInstruction, simm13: Simm13] 
RETURNS [SPARCInstruction];
SetOpF: PUBLIC PROCEDURE [instruction: SPARCInstruction, opf: OpF] 
RETURNS [SPARCInstruction];
SetOp3: PUBLIC PROCEDURE [instruction: SPARCInstruction, op3: Op3] 
RETURNS [SPARCInstruction];
Op3FromOp10Op3: PUBLIC PROCEDURE [op10Op3: Op10Op3] RETURNS [Op3];
Op3FromOp11Op3: PUBLIC PROCEDURE [op11Op3: Op11Op3] RETURNS [Op3];
Unbiased30FromDisp30: PUBLIC PROCEDURE [disp30: Disp30] RETURNS [Unbiased30];
Unbiased30MSFromDisp30: PUBLIC PROCEDURE [disp30: Disp30]
RETURNS [Unbiased30MS];
Unbiased30LSFromDisp30: PUBLIC PROCEDURE [disp30: Disp30]
RETURNS [Unbiased30LS];
Unbiased22FromDisp22: PUBLIC PROCEDURE [disp22: Disp22] RETURNS [Unbiased22];
Unbiased22MSFromDisp22: PUBLIC PROCEDURE [disp22: Disp22]
RETURNS [Unbiased22MS];
Unbiased22LSFromDisp22: PUBLIC PROCEDURE [disp22: Disp22]
RETURNS [Unbiased22LS];
Unbiased22MSFromImm22: PUBLIC PROCEDURE [imm22: Imm22]
RETURNS [Unbiased22MS];
Unbiased22LSFromImm22: PUBLIC PROCEDURE [imm22: Imm22]
RETURNS [Unbiased22LS];
Unbiased13FromSimm13: PUBLIC PROCEDURE [simm13: Simm13] RETURNS [Unbiased13];

IsNullSPARCAddress: PROCEDURE [address: SPARCAddress] 
RETURNS [BOOLEAN];
SPARCAddressFromDisplacement: PROCEDURE [
address: SPARCAddress, displacement: TargetArchitecture.Displacement]
RETURNS [SPARCAddress];

DisplacementFromSPARCAddresses: PROCEDURE [
here: SPARCAddress, there: SPARCAddress]
RETURNS [TargetArchitecture.Displacement];

IsNullSPARCInstruction: PROCEDURE [instruction: SPARCInstruction] 
RETURNS [BOOLEAN];
NextSPARCInstruction: PROCEDURE [pc: SPARCAddress] 
RETURNS [SPARCAddress];

PrevSPARCInstruction: PROCEDURE [pc: SPARCAddress] 
RETURNS [SPARCAddress];

SPARCAddressFromTargetAddress: PROCEDURE [address: TargetArchitecture.Address] 
RETURNS [SPARCAddress];

TargetAddressFromSPARCAddress: PROCEDURE [
sparcAddress: SPARCAddress] 
RETURNS [TargetArchitecture.Address];

SPARCContentsFromTargetContents: PROCEDURE [
contents: TargetArchitecture.Contents]
RETURNS [SPARCContents];

TargetContentsFromSPARCContents: PROCEDURE [
contents: SPARCContents]
RETURNS [TargetArchitecture.Contents];

SPARCInstructionFromTargetInstruction: PROCEDURE [
instruction: TargetArchitecture.Instruction]
RETURNS [SPARCInstruction];

TargetInstructionFromSPARCInstruction: PROCEDURE [
instruction: SPARCInstruction]
RETURNS [TargetArchitecture.Instruction];

SPARCRegisterClassFromTargetRegisterClass: PROCEDURE [
registerClass: TargetArchitecture.RegisterClass]
RETURNS [RegisterClass];

TargetRegisterClassFromSPARCRegisterClass: PROCEDURE [
registerClass: RegisterClass]
RETURNS [TargetArchitecture.RegisterClass];

CantRelocate: ERROR;
CantReach: ERROR;
NullSPARCAddress: ERROR;

NullSPARCInstruction: ERROR;
}.

6
SPARCArchitecture.mesa
Copyright ำ 1989, 1990, 1991 by Xerox Corporation.  All rights reserved.
Peter B. Kessler, April 9, 1990 3:25:39 pm PDT

Architectural information about the SPARC, for the PrincOps compiler (sigh).
Types.
Miscellaneous
Instruction Formats
Subsidiary types
use Op10Op3 and Op11Op3 to get values for fields of this type.  Sigh.
Fill this in as you need it.
Fill this in as you need it.
When you use sp-relative addressing, you have to avoid the 16 word area at the bottom of the stack in which the system saves in and local registers whenever it wants to.
If you might be changing a leaf frame to a (non-aggregate-returning) caller frame, you have to allocate at least this much space, into which the callee may store register arguments.
The stack has to be double-word aligned.
In the PrincOps compiler, you can't have enumerations (or even subranges) like this, so we have to do our own, dynamic, type-checking.  Sigh.
Disp30: TYPE ~ INT [-536870912..536870911];	-- in Mimosa.
Imm22: TYPE ~ NAT [0..4194303];		-- in Mimosa.
Disp22: TYPE ~ INT [-2097152..2097151];	-- in Mimosa.
Types for signed bitfields in instruction records.
These are unbiased types, which is what you want in the instruction fields.
For signed fields, you have to undo the biasing that Mesa put on types.
Unbiased30: TYPE ~ MACHINE DEPENDENT {zero (0), (1073741823)}; -- in Mimosa.
Unbiased22: TYPE ~ MACHINE DEPENDENT {zero (0), (4194303)}; -- in Mimosa.
Unbiased13: TYPE ~ MACHINE DEPENDENT {zero (0), (8191)}; -- in Mimosa.

Miscellaneous
Miscellaneous
Procedures.
Code Assembly.
! CantReach
Relocates an instruction from the given address to another address.
! CantRelocate
Instruction Classification.
Checks whether the instruction is a noop.

Checks whether the instruction has pc-relative operands.
Checks whether the instruction is a call instruction.
Checks whether the instruction is a delayed branch instruction.
Checks whether the instruction is a jmpl with %o7 as the link register.
Checks whether the instruction is a jmpl with %g0 as the link register.
Field accessors for instructions.
Field assigners for instructions.
Miscellaneous.
Tests if its argument is the null SPARCAddress.

Tests if its argument is the null SPARCInstruction.

Returns the address of the next instruction.
Returns a pointer to the previous instruction.
Errors.
Given for attempts to relocate an instruction too far, etc.

Given for attempts to generate pc-relative instructions that don't reach.

Given during code generation when null addresses are supplied.
Given when supplied instruction is the null instruction.


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