MIPSBreakpoint.mesa
Copyright Ó 1992, 1993 by Xerox Corporation. All rights reserved.
Katsuyuki Komatsu August 5, 1992 6:03 pm PDT
DIRECTORY
MIPSArchitecture,
MIPSManger;
MIPSBreakpoint: CEDAR DEFINITIONS ~ {
Patches can't be monitored, since the processor executes out of them. My accesses of the patches and the pc's executing in them are races. That isn't a problem because the pc's never get to the patches until I'm done setting them up (fortunately), and I don't clear the patch. Clearing a breakpoint is just putting the instruction back, since you can't tell when the pc (or several of them) are done with the patch (that's is a garbage collection problem).
This closureCaller is for MIPS's: it includes pushing a link register and allocating space for saving the rest of the registers.
addiu $sp, $sp, -(stackAllocationForCallee+registerSaveArea)
sw r31, 20(sp)
jal ←save←regs
noop
  -- save←regs(@registerSaveArea).
lui %hi(clientData), $4
jal clientProc
ori  %lo(clientData), $4
  -- clientProc(clientData).
jal ←restore←regs
noop
  -- restore←regs(@registerSaveArea).
lw r31, 20(sp)
addiu $sp, $sp, (stackAllocationForCallee+registerSaveArea)
Constants.
registerSaveArea: NAT ~ 66 * BYTES[MIPSArchitecture.MIPSContents];
30 words (general without r0 & r31) + 32 words (floating-point) + 2 words (special) + 1 word (floating-point control) for saving the rest of the registers (double-word aligned).
Types.
Patches are self-describing, in that they include the address of the replaced instruction (in the header) and the replaced instruction (relocated into the patch).
PatchStruct: TYPE ~ MACHINE DEPENDENT RECORD [
closureCaller: ClosureCaller,
manger:  MIPSManger.Manger
];
ClosureCaller: TYPE ~ MACHINE DEPENDENT RECORD [
subiu:  MIPSArchitecture.MIPSInstruction,
sw:  MIPSArchitecture.MIPSInstruction,
callSaveRegs: MIPSArchitecture.MIPSInstruction,
noop1:  MIPSArchitecture.MIPSInstruction,
in the delay slot.
argHiClientData: MIPSArchitecture.MIPSInstruction,
callClientProc: MIPSArchitecture.MIPSInstruction,
argLoClientData: MIPSArchitecture.MIPSInstruction,
in the delay slot.
callRestoreRegs: MIPSArchitecture.MIPSInstruction,
noop2:  MIPSArchitecture.MIPSInstruction,
in the delay slot.
lw:  MIPSArchitecture.MIPSInstruction,
addiu:  MIPSArchitecture.MIPSInstruction
];
}.