MIPSArchitecture.mesa
Copyright Ó 1992, 1993 by Xerox Corporation. All rights reserved.
Katsuyuki Komatsu August 7, 1992 5:11 pm PDT
DIRECTORY
TargetArchitecture;
MIPSArchitecture: CEDAR DEFINITIONS ~ {
Types.
Miscellaneous
MIPSAddress: TYPE[SIZE[CARD32]];
nullMIPSAddress: MIPSAddress ~ LOOPHOLE[FIRST[CARD32]];
MIPSContents: TYPE[SIZE[CARD32]];
MIPSInstruction: TYPE[SIZE[CARD32]];
nullMIPSInstruction: MIPSInstruction ~ LOOPHOLE[CARD32[0]];
Instruction Formats
FormatI: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
rt (0:11..15): Register ¬,
imm16 (0:16..31): Imm16 ¬
];
FormatIRegImm: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
opRegImm (0:11..15): OpRegImm ¬,
imm16 (0:16..31): Imm16 ¬
];
FormatSI: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
rt (0:11..15): Register ¬,
simm16 (0:16..31): Simm16 ¬
];
FormatSIRegImm: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
opRegImm (0:11..15): OpRegImm ¬,
simm16 (0:16..31): Simm16 ¬
];
FormatJ: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
disp26 (0:6..31): Disp26 ¬
];
FormatR: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
rt (0:11..15): Register ¬,
rd (0:16..20): Register ¬,
sa (0:21..25): ShiftAmount ¬,
opspecial (0:26..31): OpSpecial ¬
];
FormatRTrap: TYPE ~ MACHINE DEPENDENT RECORD [
op (0:0..5): Op ¬,
rs (0:6..10): Register ¬,
rt (0:11..15): Register ¬,
code (0:16..25): Code ¬,
opspecial (0:26..31): OpSpecial ¬
];
FormatUnknown: TYPE ~ RECORD [
bits: MIPSInstruction ¬
];
Subsidiary types
Op: TYPE ~ MACHINE DEPENDENT {
special (00B), regimm (01B), j (02B), jal (03B),
beq (04B), bne (05B), blez (06B), bgtz (07B),
addi (10B), addiu (11B), slti (12B), sltiu (13B),
andi (14B), ori (15B), xori (16B), lui (17B),
cop0 (20B), cop1 (21B), cop2 (22B), cop3 (23B),
beql (24B), bnel (25B), blezl (26B), bgtzl (27B),
(30B), (31B), (32B), (33B), --
(34B), (35B), (36B), (37B), --
lb (40B), lh (41B), lwl (42B), lw (43B),
lbu (44B), lhu (45B), lwr (46B), -- (47B), --
sb (50B), sh (51B), swl (52B), sw (53B),
-- (54B), (55B), -- swr (56B), cache (57B),
ll (60B), lwc1 (61B), lwc2 (62B), lwc3 (63B),
-- (64B), -- ldc1 (65B), ldc2 (66B), ldc3 (67B),
sc (70B), swc1 (71B), swc2 (72B), swc3 (73B),
-- (74B), -- sdc1 (75B), sdc2 (76B), sdc3 (77B)
};
OpSpecial: TYPE ~ MACHINE DEPENDENT {
sll (00B), -- (01B), -- srl (02B), sra (03B),
sllv (04B), -- (05B), -- srlv (06B), srav (07B),
jr (10B), jalr (11B), -- (12B), (13B), --
syscall (14B), break (15B), -- (16B), -- sync (17B),
mfhi (20B), mthi (21B), mflo (22B), mtlo (23B),
(24B), (25B), (26B), (27B), --
mult (30B), multu (31B), div (32B), divu (33B),
(34B), (35B), (36B), (37B), --
add (40B), addu (41B), sub (42B), subu (43B),
and (44B), or (45B), xor (46B), nor (47B),
-- (50B), (51B), -- slt (52B), sltu (53B),
(54B), (55B), (56B), (57B), --
tge (60B), tgeu (61B), tlt (62B), tltu (63B),
teq (64B), -- (65B), -- tne (66B) --, (67B), --
(70B), (71B), (72B), (73B), --
(74B), (75B), (76B), (77B) --
};
OpRegImm: TYPE ~ MACHINE DEPENDENT {
bltz (00B), bgez (01B), bltzl (02B), bgezl (03B),
(14B), (15B), (16B), (17B) --
tgei (10B), tgeiu (11B), tlti (12B), tltiu (13B),
teqi (14B), -- (15B), -- tnei (16B), -- (17B), --
bltzal (20B), bgezal (21B), bltzall (22B), bgezall (23B)
(24B), (25B), (26B), (27B) --
(30B), (31B), (32B), (33B), --
(34B), (35B), (36B), (37B) --
};
Register: TYPE ~ MACHINE DEPENDENT {
r0 (0), r1, r2, r3, r4, r5, r6, r7,
r8 (8), r9, r10, r11, r12, r13, r14, r15,
r16 (16), r17, r18, r19, r20, r21, r22, r23,
r24 (24), r25, r26, r27, r28, r29, r30, r31
};
zero: Register ~ Register.r0;    -- wired zero
at: Register ~ Register.r1;    -- assembler temp
v0: Register ~ Register.r2;    -- return value
v1: Register ~ Register.r3;
a0: Register ~ Register.r4;    -- argument registers
a1: Register ~ Register.r5;
a2: Register ~ Register.r6;
a3: Register ~ Register.r7;
t0: Register ~ Register.r8;    -- caller saved
t1: Register ~ Register.r9;
t2: Register ~ Register.r10;
t3: Register ~ Register.r11;
t4: Register ~ Register.r12;
t5: Register ~ Register.r13;
t6: Register ~ Register.r14;
t7: Register ~ Register.r15;
s0: Register ~ Register.r16;    -- callee saved
s1: Register ~ Register.r17;
s2: Register ~ Register.r18;
s3: Register ~ Register.r19;
s4: Register ~ Register.r20;
s5: Register ~ Register.r21;
s6: Register ~ Register.r22;
s7: Register ~ Register.r23;
t8: Register ~ Register.r24;    -- code generator
t9: Register ~ Register.r25;
k0: Register ~ Register.r26;    -- kernel temporary
k1: Register ~ Register.r27;
gp: Register ~ Register.r28;    -- global pointer
sp: Register ~ Register.r29;    -- stack pointer
fp, s8: Register ~ Register.r30;    -- frame pointer, one more callee saved
ra: Register ~ Register.r31;    -- return address
globalPointer: Register ~ Register.r28;
stackPointer: Register ~ Register.r29;
stackPointerOffset: NAT ~ 0 * BYTES[TargetArchitecture.Contents];
When you use sp-relative addressing, you have to avoid the 0 word area at the bottom of the stack in which the system saves in and local registers whenever it wants to (not necessary for MIPS).
stackAllocationForCallee: NAT ~ 6 * BYTES[TargetArchitecture.Contents];
If you might be changing a leaf frame to a (non-aggregate-returning) caller frame, you have to allocate at least this much space, into which the callee may store register arguments.
stackAllocationUnit: NAT ~ 2 * BYTES[TargetArchitecture.Contents];
The stack has to be double-word aligned.
returnAddress: Register ~ Register.r31;
FloatingRegister: TYPE ~ MACHINE DEPENDENT {
f0 (0), f2, f4, f6,
f8, f10, f12, f14,
f16, f18, f20, f22,
f24, f26, f28, f30
};
RegisterClass: TYPE ~ MACHINE DEPENDENT {
none (LOOPHOLE[TargetArchitecture.RegisterClass.none]),
globals, globalsAndIns, globalsInsAndFloats, globalsInsFloatsOutsAndLocals,
nextAvailable,
all (LOOPHOLE[TargetArchitecture.RegisterClass.all])
} ¬ nullRegisterClass;
nullRegisterClass: RegisterClass ~ RegisterClass.none;
Cond: TYPE ~ MACHINE DEPENDENT {
never (00H), equal (01H), lessOrEqual (02H), less (03H),
lessOrEqualUnsigned (04H), carrySet (05H), negative (06H), overflowSet (07H),
always (08H), notEqual (09H), greater (0AH), greaterOrEqual (0BH),
greaterUnsigned (0CH), carryClear (0DH), positive (0EH), overflowClear (0FH)
};
AddressFormat: TYPE ~ MACHINE DEPENDENT RECORD [
high (0:0..3): HighOrderBits ¬,
target (0:4..29): Disp26 ¬,
tag (0:30..31): TagBits ¬
];
Disp26: TYPE ~ [0..67108863];
firstDisp26: Disp26 ~ 0;
lastDisp26: Disp26 ~ 67108863;
Disp16: TYPE ~ INT32;
firstDisp16: Disp16 ~ -32768;
lastDisp16: Disp16 ~ 32767;
Imm16: TYPE ~ CARD16;
firstImm16: Imm16 ~ 0;
lastImm16: Imm16 ~ 65535;
Simm16: TYPE ~ INT16;
firstSimm16: Simm16 ~ -32768;
lastSimm16: Simm16 ~ 32767;
Code: TYPE ~ [0..1023];
firstCode: Code ~ 0;
lastCode: Code ~ 1023;
ShiftAmount: TYPE ~ [0..31];
firstShiftAmount: ShiftAmount ~ 0;
lastShiftAmount: ShiftAmount ~ 31;
HighOrderBits: TYPE ~ [0..15];
firstHighOrderBits: HighOrderBits ~ 0;
lastHighOrderBits: HighOrderBits ~ 15;
TagBits: TYPE ~ [0..3];
firstTagBits: TagBits ~ 0;
lastTagBits: TagBits ~ 3;
Ignored5: TYPE ~ MACHINE DEPENDENT {
ignored (0), (31)
} ¬ Ignored5.ignored;
Miscellaneous
Format: TYPE ~ {
formatI, formatIRegImm, formatSI, formatSIRegImm, formatJ, formatR, formatRTrap
};
Miscellaneous
ProcessorRegister: TYPE ~ {pc, hi, lo --and probably others-- };
Procedures.
Code Assembly.
Noop: PROCEDURE [] RETURNS [MIPSInstruction];
LW: PROCEDURE [base: Register, offset: Simm16, dest: Register]
RETURNS [MIPSInstruction];
SW: PROCEDURE [source: Register, base: Register, offset: Simm16]
RETURNS [MIPSInstruction];
LUI: PROCEDURE [hi: Imm16, dest: Register] RETURNS [MIPSInstruction];
ORI: PROCEDURE [source: Register, constant: Imm16, dest: Register]
RETURNS [MIPSInstruction];
ADDIU: PROCEDURE [source: Register, constant: Simm16, dest: Register]
RETURNS [MIPSInstruction];
J: PROCEDURE [pc: MIPSAddress, to: MIPSAddress]
RETURNS [MIPSInstruction];
! CantReach
JAL: PROCEDURE [pc: MIPSAddress, to: MIPSAddress]
RETURNS [MIPSInstruction];
! CantReach
JR: PROCEDURE [to: Register]
RETURNS [MIPSInstruction];
JALR: PROCEDURE [returnAddress: Register ¬ ra, to: Register]
RETURNS [MIPSInstruction];
Relocate: PROCEDURE [
instruction: MIPSInstruction,
from: MIPSAddress,
to: MIPSAddress]
RETURNS [MIPSInstruction];
Relocates an instruction from the given address to another address.
! CantRelocate
Instruction Classification.
IsDelayedControlTransfer: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
IsNoopInstruction: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Checks whether the instruction is a noop.
NeedsRelocation: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Checks whether the instruction has pc-relative operands.
IsBranchInstruction: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Checks whether the instruction is a conditional branch instruction.
IsCallInstruction: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Checks whether the instruction is a call instruction.
IsJumpInstruction: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Checks whether the instruction is a unconditional branch instruction.
Field accessors for instructions.
GetFormat: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Format];
GetOp: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Op];
GetOpSpecial: PROCEDURE [instruction: MIPSInstruction]
RETURNS [OpSpecial];
GetOpRegImm: PROCEDURE [instruction: MIPSInstruction]
RETURNS [OpRegImm];
GetDisp26: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Disp26];
GetDisp16: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Disp16];
GetImm16: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Imm16];
GetSimm16: PROCEDURE [instruction: MIPSInstruction]
RETURNS [Simm16];
Hi: PROCEDURE [value: CARD32] RETURNS [Imm16];
Lo: PROCEDURE [value: CARD32] RETURNS [Imm16];
HiLo: PROCEDURE[hi: Imm16, lo: Imm16] RETURNS [CARD32];
Field assigners for instructions.
SetDisp16: PROCEDURE [instruction: MIPSInstruction, disp16: Disp16]
RETURNS [MIPSInstruction];
SetImm16: PROCEDURE [instruction: MIPSInstruction, imm16: Imm16]
RETURNS [MIPSInstruction];
SetSimm16: PROCEDURE [instruction: MIPSInstruction, simm16: Simm16]
RETURNS [MIPSInstruction];
Field accessors for address.
GetHighOrderBits: PROCEDURE [address: MIPSAddress]
RETURNS [HighOrderBits];
GetTargetBits: PROCEDURE [address: MIPSAddress]
RETURNS [Disp26];
GetTagBits: PROCEDURE [address: MIPSAddress]
RETURNS [TagBits];
Miscellaneous.
IsNullMIPSAddress: PROCEDURE [address: MIPSAddress]
RETURNS [BOOLEAN];
Tests if its argument is the null MIPSAddress.
MIPSAddressFromDisplacement: PROCEDURE [
address: MIPSAddress, displacement: TargetArchitecture.Displacement]
RETURNS [MIPSAddress];
DisplacementFromMIPSAddresses: PROCEDURE [
here: MIPSAddress, there: MIPSAddress]
RETURNS [TargetArchitecture.Displacement];
IsNullMIPSInstruction: PROCEDURE [instruction: MIPSInstruction]
RETURNS [BOOLEAN];
Tests if its argument is the null MIPSInstruction.
NextMIPSInstruction: PROCEDURE [pc: MIPSAddress]
RETURNS [MIPSAddress];
Returns the address of the next instruction.
PrevMIPSInstruction: PROCEDURE [pc: MIPSAddress]
RETURNS [MIPSAddress];
Returns a pointer to the previous instruction.
MIPSAddressFromTargetAddress: PROCEDURE [address: TargetArchitecture.Address]
RETURNS [MIPSAddress];
TargetAddressFromMIPSAddress: PROCEDURE [
mipsAddress: MIPSAddress]
RETURNS [TargetArchitecture.Address];
MIPSContentsFromTargetContents: PROCEDURE [
contents: TargetArchitecture.Contents]
RETURNS [MIPSContents];
TargetContentsFromMIPSContents: PROCEDURE [
contents: MIPSContents]
RETURNS [TargetArchitecture.Contents];
MIPSInstructionFromTargetInstruction: PROCEDURE [
instruction: TargetArchitecture.Instruction]
RETURNS [MIPSInstruction];
TargetInstructionFromMIPSInstruction: PROCEDURE [
instruction: MIPSInstruction]
RETURNS [TargetArchitecture.Instruction];
MIPSRegisterClassFromTargetRegisterClass: PROCEDURE [
registerClass: TargetArchitecture.RegisterClass]
RETURNS [RegisterClass];
TargetRegisterClassFromMIPSRegisterClass: PROCEDURE [
registerClass: RegisterClass]
RETURNS [TargetArchitecture.RegisterClass];
Errors.
CantRelocate: ERROR;
Given for attempts to relocate an instruction too far, etc.
CantReach: ERROR;
Given for attempts to generate pc-relative instructions that don't reach.
NullMIPSAddress: ERROR;
Given during code generation when null addresses are supplied.
NullMIPSInstruction: ERROR;
Given when supplied instruction is the null instruction.
}.