*----------------------------------------------------------------------------
Title[EtherDefs.Mc...November 23, 1982  10:34 AM...Taft];
*** Pilot-only version ***
*----------------------------------------------------------------------------


*----------------------------------------------------------------------------
* Hardware definitions
*----------------------------------------------------------------------------

* TIOA assignments
Device[EData, 15];	* Input and output data
Device[EControl, 16];	* Control and status

* Receiver status bits in end-of-packet word (EData).  Assignments are
* Alto-compatible (except RxCollision, which the Alto doesn't have)
MC[RxCollision, 200];	* Receiver-detected collision
MC[RxDataLate, 40];	* Input data late
MC[RxCRCError, 10];	* CRC bad
MC[EInCmd, 4];		* Input command issued	** Not in hardware:	   **
MC[EOutCmd, 2];		* Output command issued	** for Alto emulation only **
MC[RxIncTrans, 1];	* Incorrectly terminated packet

* Transmitter and general interface status bits (EControl)
* Left byte is Ethernet host address.
MC[RxOn, 200];		* Receiver on
MC[TxOn, 100];		* Transmitter on
MC[LoopBack, 40];	* Loop-back mode on
MC[TxCollision, 20];	* Transmitter-detected collision
MC[NoWakeups, 10];	* Task wakeups enabled if 0, disabled if 1
MC[TxDataLate, 4];	* Output data late
MC[SingleStep, 2];	* Single-step mode on
MC[TxFifoPE, 1];	* Transmitter-detected IOB or Fifo parity error

* Status masks useful for Alto emulation
MC[EISMask, RxCollision, RxDataLate, RxCRCError, RxIncTrans]; * Input status
MC[EOSMask, TxDataLate, TxCollision, TxFifoPE]; * Output status
MC[ECmdBits, EInCmd, EOutCmd]; * Command bits

* Control bits (EControl) -- Transmitter control (bits 0-3)
MC[TxCmdEnbl, 007777];	* Bit 0 = 0 enables decoding of output commands
MC[STxOn, 40000];	* Turn on output if 1, off if 0
MC[STxEOP, 20000];	* Send end of packet if 1
MC[STxCntDown, 10000];	* Generate countdown wakeup if 1

MC[TurnOffTx, TxCmdEnbl];
MC[TurnOnTx, TxCmdEnbl, STxOn];
MC[CountDown, TxCmdEnbl, STxOn, STxCntDown];
MC[SendEOP, TxCmdEnbl, STxOn, STxEOP];

* Control bits (EControl) -- Receiver control (bits 4-7)
MC[RxCmdEnbl, 170377];	* Bit 4 = 0 enables decoding of input commands
MC[SRxOn, 2000];	* Turn on input if 1, off if 0
MC[SRxBOP', 1000];	* Wait for beginning of next packet if 0

MC[TurnOnRx, RxCmdEnbl, SRxOn, SRxBOP'];
MC[TurnOffRx, RxCmdEnbl];
MC[WaitForBOP, RxCmdEnbl, SRxOn];

* Control bits (EControl) -- Test control (bits 8-15)
MC[TestCmdEnbl, 177400]; * Bit 8 = 0 enables decoding of test commands
MC[SLoopBack, 100];	* Turn on loop-back mode if 1, off if 0
MC[SSingleStep, 40];	* Turn on single-step mode if 1, off if 0
MC[SNoWakeups, 20];	* Enable task wakeups if 0, disable if 1
MC[SEtherClk, 10];	* Generate one EtherClk if 1 (SSingleStep must be 1)
MC[SCollision', 4];	* Cause a collision indication if 0
MC[SPDInput, 2];	* Set flop that ORs a 1 into the received data if 1 
MC[SReportCollisions, 1]; * Report receiver detected collisions

*----------------------------------------------------------------------------
* R-registers
*----------------------------------------------------------------------------

* The input and output R-registers have to be in separate banks because
* the two tasks share task-independent subroutines that need to reference
* task-specific registers and temporaries.  However, we don't need very
* many R-registers in either bank, so these banks may be shared with
* other tasks.

SetRMRegion[EIRegs];	* Used by input task -- first 3 must parallel EORegs
	RVN[EICB];	* Pointer to IOCB being worked on
	RVN[EIPtr];	* Input main loop pointer/count
	RVN[EITemp1];	* Input temporaries
	RVN[EITemp2];

SetRMRegion[EORegs];	* Used by output task -- first 3 must parallel EIRegs
	RVN[EOCB];	* Pointer to IOCB being worked on
	RVN[EOPtr];	* Output main loop pointer/count
	RVN[EOTemp1];	* Output temporary
	RVN[EOTemp2];	* Output temporary
	RVN[EOTime];	* Time at end of last packet successfully transmitted
	RVN[RNum];	* State for random number generator
	RV[RConst, 33031]; * Constant (13849) for random number generator

* Region-independent R-register definitions
RVRel[ExCB, And[IP[EICB], 17]];
RVRel[ExPtr, And[IP[EIPtr], 17]];
RVRel[ExTemp1, And[IP[EITemp1], 17]];

*----------------------------------------------------------------------------
* Memory base registers
*----------------------------------------------------------------------------

% -- Defined in ADefs.mc --
BR[EIBR, ?];		* Input base register
BR[EOBR, ?];		* Output base register
%

*----------------------------------------------------------------------------
* Data structures
*----------------------------------------------------------------------------

* This microcode supports a "multicast" input regimen.  The client can specify from
* 0 to 255 host numbers, using a bit vector.  Packets directed to any of the specified
* hosts will be accepted by the microcode.  It is up to the client to sort out the results.
* The feature is enabled by setting the ICSB.host field to -1.  Then the ICSB.hosts vector
* will be used to decide which packets to accept.  Note that the client can disable the
* acceptance of broadcast packets.  Setting ICSB.host to a valid host returns to the
* conventional single-host mode.  The ICSB.hosts vector should have the proper value
* before the ICSB.host field is set to -1.

* Ethernet has a 40B-word CSB shared by input and output.

* InputControllerStatusBlock: TYPE = MACHINE DEPENDENT RECORD [
MC[ICSB.next, EtherCSB, 0];	* next: POINTER TO IOControlBlock,
MC[ICSB.interruptMask, EtherCSB, 1]; * interruptMask: WORD,
MC[ICSB.host, EtherCSB, 2];	* host: CARDINAL, -- if >=0, conventional one-host style
MC[ICSB.missed, EtherCSB, 3];	* missed: CARDINAL,
				* software: ARRAY [4..7] OF WORD, -- software use only
MC[ICSB.hosts, EtherCSB, 10];	* hosts: PACKED ARRAY [0..256) OF BOOLEAN];

* OutputControllerStatusBlock: TYPE = MACHINE DEPENDENT RECORD [
MC[OCSB.next, EtherCSB, 30];	* next: POINTER TO IOControlBlock,
MC[OCSB.interruptMask, EtherCSB, 31]; * interruptMask: WORD,
MC[OCSB.minPacketSpacing, EtherCSB, 32]; * minPacketSpacing: CARDINAL, -- 32us units
				* software: ARRAY [33..37] OF WORD]; -- software use only

* IOControlBlock: TYPE = MACHINE DEPENDENT RECORD [
MC[IOCB.next, 0];		* next: POINTER TO IOControlBlock,
MC[IOCB.completion, 1]; 	* completion: CompletionStatus,
MC[IOCB.wordsUsed, 2];		* wordsUsed: CARDINAL,
MC[IOCB.load, 3];		* load: CARDINAL,
MC[IOCB.length, 4];		* length: CARDINAL,
MC[IOCB.buffer, 5];		* buffer: LONG POINTER];

* CompletionStatus: TYPE = MACHINE DEPENDENT RECORD [
*	microcode: {busy, done, bufferOverflow, loadOverflow, (377B)},
*	hardware: [0..377B]]
* Hardware status for input is status word received through receive fifo;
* for output is status word read from EControl.

* Microcode completion status codes:
MC[CS.done, 400];
MC[CS.bufferOverflow, 1000];
MC[CS.loadOverflow, 1400];