*** RegisterDefs.mc last edited October 23, 1979 11:48 AM
** stored in [ivy]<DoradoSource>AemuSources.dm
*** T H I S I S F O R S E R I A L 1 ****

TITLE[RegisterDefs.mc... November 9, 1979 6:31 PM];
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November 9, 1979 6:31 PM
Add eventReturn and use a new RBASE for all events.

November 9, 1979 2:16 PM
Add eventAovFlg, eventBovFlg

November 9, 1979 11:39 AM
Add event* registers for tripple precision event counters.

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***** - - - - - - - - - - - - - - - - - - - -
*** Region 0
RMREGION[RMforIFU];* needs to be first
rvn[IFUreg0]; reserve[17];

** MACRO for renaming the first 20b registers
M[RenameIFUreg, (IFG[#2,17,ER[too-many-IFUregs]],
RM[#1, ADD[ IP[IFUreg0], #2]])];

**e.g., RenameIFUreg[RTEMP1, 1]

***** - - - - - - - - - - - - - - - - - - - -
M[rme, RM[#1, IP[#2]]];

***** - - - - - - - - - - - - - - - - - - - -
*** Region 1
RMREGION[AemRegs]; *AltoEmulator Registers
RVN[AC0];
RVN[AC1];
RVN[AC2];
RVN[AC3];
RVN[PC];* emulator program counter
RVN[NWW];* New Wakeups Waiting
RVN[CRY];* Emulator carry bit
RVN[ACRY];* Emulator carry bit during AFunctions

rvn[EmuBrHiReg];* holds hi bits of emulator normal space
rvn[EmuXMBrHiReg];* holds hi bits of emulator alternate space
rvn[debugReg];* may be useful
rvn[EmuFltPC];* save pc of task 0 at fault time

** define temps as the higher numbered registers
RVN[Ireg];* holds current instruction
RVN[Xreg];* a temp
RVN[Yreg];
RVN[temp17];* temp for mult and div - must be 17b

***** - - - - - - - - - - - - - - - - - - - -
*** Region 2
RMREGION[BBREGS]; * AltoEmulator Registers, for Convert and BitBlt
RVN[NWRDS];* number of words per scan line
RVN[XH];* bit map height
RVN[DWAX];* destination word address
RVN[DBA];* destination bit address
RVN[CMASK];* mask from MASKTAB
RVN[PtrXW];* ptr to XW words of character descriptor block
RVN[ct1];* temp
RVN[ct2];* temp
* Remainder not used by Convert but used by BitBlt

***** - - - - - - - - - - - - - - - - - - - -
* BitBlt registers, selected during horizontal loops.

rme[BBDST, NWRDS];
rme[BBSRC, XH];
rme[DSTINC, DWAX];
rme[SRCINC, DBA];
rme[DRAST, CMASK];
rme[SRAST, PtrXW];
rme[PREFDST, ct1];
rme[PREFSRC, ct2];
rvn[PREFINC]
rvn[VCOUNT];
rvn[HCOUNT];
rvn[IHCOUNT];
rvn[ICNT];
rvn[BBDISP];
RESERVE[1];
rvn[SRCWD];*Must be RVREL 17

* BitBlt temps, overlaid with Alto emulator temps
rme[GRAY0, ACRY];
rme[GRAY1, Ireg];
rme[GRAY2, Xreg];
rme[GRAY3, Yreg];

***** - - - - - - - - - - - - - - - - - - - -
*** Region 3
RMREGION[EIREGS];*Used by ether input task
RVN[EIPTR];*Input main loop pointer/count
RVN[EITEMP1];*Input temporaries
RVN[EITEMP2];

rvn[FltPipe0];
rvn[FltPipe1];
rvn[FltPointers];
rvn[FltErrors];
rvn[FaultVal];
rvn[FaultMapVal];
rvn[FaultInfo];
rvn[FltMemPtr];
rvn[fltTemp];* one always needs a temp


***** - - - - - - - - - - - - - - - - - - - -
*** Region 4
** Register definitions for the display
** These definitions really reside in RegisterDefs.mc
** AChannelRegion must be assigned an RBase value with zero in bit 2.
** BChannelRegion must equal AChannelRegion, but with one in bit 2.

RmRegion[AChannelRegion];

* following registers hold subtask specific values for the A channel
* accessed by DWT

rvn[AAddress];
rvn[ACount];
rvn[ANextCount];
rvn[ANextAddrLo];
rvn[ANextAddrHi];
rvn[ASetCWCBFlagANDClearNWCBFlag];

* following registers hold parameters NOT accessed by DWT

rvn[AReaderPtrReg];
rvn[ADWRDSMinus1];
rvn[ADCBChainReg];
rvn[AVCWShadowReg];
rvn[ASAHiReg];
rvn[ASALoReg];
rvn[ANWRDSReg];
rvn[ASLCReg];
rvn[AChannelReg];
rvn[AScratch];

***** - - - - - - - - - - - - - - - - - - - -
*** Region 5
* Register definitions for the display horizontal task DHT

RmRegion[DHTRegion];

rvn[VCWShadowReg];
rvn[FieldAreaReg];
rvn[CursorBaseMinus2];
rvn[CursorYReg];
rvn[HRamSAReg];
rvn[HRamLengthReg];
rvn[HRamDataReg];
rvn[Reg400C];
rvn[DHTScratch];
rvn[TerminalHi];
rvn[TerminalLo];
rvn[OISMdReg];
rvn[OISScratch];
rvn[OISMCount];
rvn[OISBootCount];
rvn[AllowXtdAddr];

***** - - - - - - - - - - - - - - - - - - - -
*** Region 6
RmRegion[BChannelRegion];

* following registers hold subtask specific values for the B channel
* accessed by DWT

rvn[BAddress];
rvn[BCount];
rvn[BNextCount];
rvn[BNextAddrLo];
rvn[BNextAddrHi];
rvn[BSetCWCBFlagANDClearNWCBFlag];

* following registers hold parameters NOT accessed by DWT

rvn[BReaderPtrReg];
rvn[BDWRDSMinus1];
rvn[BDCBChainReg];
rvn[BVCWShadowReg];
rvn[BSAHiReg];
rvn[BSALoReg];
rvn[BNWRDSReg];
rvn[BSLCReg];
rvn[BChannelReg];
rvn[BScratch];

***** - - - - - - - - - - - - - - - - - - - -
*** Region 7
RMREGION[EOREGS];*Used by output task
RVN[EOPTR];*Output main loop pointer/count
RVN[EOTEMP1];*Output temporaries
RVN[EOTEMP2];
RVN[RNUM];*Random number generator state
*RV[RCONST, 33031];*Constant (13849) for random number generator
RVN[RCONST];

***** - - - - - RealTimeClock registers
RVN[RTCLOCK];*Real-time clock, updated by display task
rvn[RtClockHi];* holds core addr for hi part of RtClock
rvn[RTC430];* copy of vm 430
***** - - - - - - - - - - - - - - - - - - - -
*** Region 10
rmregion[DiskRegs];* disk registers
rvn[sector];* sector counter
rvn[KPTR];* command block pointer
rvn[KAddr];* disk address
rvn[KCmmd];* disk command
rvn[DskMAddr];* memory address
rvn[KStatus];* temp
rvn[Krscr6];* temp
rvn[Krscr7];* temp, mostly used to save ShC

rvn[Krscr2];* no longer need to be aliases
rvn[Krscr3];
rvn[Krscr4];
rvn[Krscr5];
rvn[KrscrLink];* for nested subroutines
rvn[KrscrLink2];
rvn[TridentFlag];
rvn[DefaultDisk];

rmregion[events];* event counter registers


****These registers used by junk wakeup task to provide tripple precision event counters

rvn[eventAHi0];
rvn[eventAhi1];
rvn[eventALo];
rvn[eventAovFlag];
rvn[eventBHi0];
rvn[eventBHi1];
rvn[eventBLo];
rvn[eventBovFlag];

rvn[eventReturn];