[_CD8_]<doradosource>diagnosticsubrs.dm!11>memSubrsD.mc

RoutineDescription
iMunchCtrl:Initialize cache munch counter
iCDvaCtrl:Initialize cache va control
iCDpatCtrl:Initialize cache data pattern control
nextVa:Return next cache va in "va"
nextMunch:Return next munch addr in "va"
nextCDpat:Return next cache data pattern
getCDpat:Return current cache data pattern
iDboard:Initialize the D-board
cdRead:Read a word from va = t, result in rscr2
cdWrite:Write a word w/ t = va, rscr = data
colForVa:Return t = column for a va (not general purpose)
cacheAforVa:Return "midas" cache addr for a va in t
presetCache:Set all cache flags cache addrs
pcSetCflags:Set CFlags; private subr for presetCache
pcSetAmemory:Set cacheA, private subr for presetCache
zeroCache0:For va IN cacheAddrs DO cache[va]←0
setCache0:FOR va IN cacheAddrs DO cach[va]←t
pcGetHi8B:Return current pcHi8
pcGetCflags:Return current pcFlags

%

SUBROUTINE;

knowRbase[rmForMemDloops];

iMunchCtrl:
RBASE ← rbase[cMunchVa];
cMunchVa ← t - (20c);
t ← (t)+(cdMaxVa);
return, cMunchEnd ← t, rbase ← rbase[defaultRegion];

iCDvaCtrl:* init next va control. T = begin addr.
* va IN [beginAddr..beginAddr+4000B)

RBASE ← rbase[cdVa];
cdVa ← t - 1;* initial value -1
t ← (t)+(cdMaxVa);
cdVaEnd ← t;* last value +1
return, cdVaEnd ← t, rbase ← rbase[defaultRegion];

iCDpatCtrl:
t←cm1;
CDpatx ← t;
SpatX ← t;
curSPattern ← t;
return, curCDpattern ← t;

* December 22, 1977 10:20 AM
nextVa:* WRITE NEXTVA DIRECTLY INTO "VA"
RBASE ← rbase[cdVa];
t ← cdVa ← (cdVa)+1, ;
va ← t;* write it into caller’s rbase
t ← cdVaEnd;
RBASE ← rbase[defaultRegion];
return, (va)-(t);

nextMunch:* WRITE next munch DIRECTLY INTO VA
rbase ← rbase[cMunchVa];
t ← cMunchVa ← (cMunchVa) + (20C);
va ← t;
t ← cMunchEnd;
RBASE ← rbase[defaultRegion];
return, (va)-(t);* ugh. return w/ fast branch condition

* August 13, 1979 5:26 PM
nextCDpat:* compute next pattern index; return in t
%

RBASE← rbase[CDpatx];* compute end of patterns as branch condition
Drlink ← link;* save return link
top level;
t←CDpatx←(CDpatx)+1;
RBASE ← rbase[defaultRegion];* keep it simple.
t-(CDpat2EndC);* see if IN [0..pat1EndC)
branch[nxtCDPat3, alu>=0];* goto[nextPat3, ~IN [0..pat2EndC)]

* IN Pattern1 or Pattern2. We’ll use nextSpat to do the work.
call[nextSpat];
branch[nxtCDPatXit];

nxtCDPat3:* This pattern also gets generated
% by the nextSpat code. However, we’re not interested in the full and glorious alternatives of pattern 3 (it is a left cycled va which gets left cycled 28 times).
%
t - (CDpat3EndC);* if we’re done with the local
branch[nxtCDPat4, ALU>=0];* version of pattern 3, try next one
noop;
call[nextSpat];
branch[nxtCDPatXit];

nxtCDPat4:* this pattern consists of pseudo randoms
% that are generated by nextSpat, getSpat. So far, this subroutine has "secretely" called nextSpat and everything worked. Unfortunately there more pattern3 values for the nextSpat than nextCDpat really needs. Consequently, here we notice if we’ve just begun nextCDpat’s pattern4. In that case, we set nextSpat’s SpatX to the proper value to begin pattern 4.
%
t - (CDpat4EndC);* see if we’ve just entered pattern4
skpif[ALU#0], t ← Spat3EndC;
SpatX ← t;* diddle nextSpat’s index. ugly.
noop;* for placement
call[nextSpat];
branch[nxtCDPatXit];

nxtCDPatXit:
subroutine;
RBASE ← rbase[Drlink];
link ← Drlink;* restore return link, fix up rbase,
t ← CDpatX, RBASE ← rbase[defaultRegion];
return,t-(CDlastPatC);* return w/ proper branch condition

* August 13, 1979 5:25 PMCACHE DATA pattern generator

getCDPat:* compute next pattern; return it in T
%
This code actually does much of it’s work by calling getSpat, the storage pattern generator. It was easier (and less microcode) to do it this way. However, nextSpat’s pattern3 left cycles a 28 bit virtual address and uses that cycled value as a pattern. Naturally the cache test is not interested in doing things that way, consequently we depend upon nextCDpat to change nextSpat’s value in SpatX.
%
RBASE← rbase[CDpatx];
Drlink ← link;
top level;
t ← CDpatX, RBASE ← rbase[defaultRegion];
t-(CDpat4EndC);* see which pattern we are using
branch[getCDP5,alu>=0];
noop;* for placement
call[getSpat];
branch[getCDPxit];

getCDP5:* add code for pattern 5 here
branch[getCDPXit];

getCDPXit:
RBASE ← rbase[Drlink];
link ← Drlink;
subroutine;
return, RBASE← rbase[defaultRegion];

* December 12, 1978 11:25 AM

iDboard:* init the dBoard
pushReturn[];
t ← FaultInfo’;* clear out waiting errors
call[setMbase], t ← r0;* use membase 0, br=0
rscr ← t-t;
call[setBR], rscr2 ← t-t;
t ← r0;* reset mcr to allow everything
call[setMCR];

returnP[];

* December 21, 1978 8:46 PM

top level;* assure that midas subroutines really work
noop;* for placement
call[cdRead]; call[cdWrite]; call[cacheAforVa];
noop;
subroutine;
cdRead:* T = va. This subr to be used from Midas
fetch ← t;
noop;
rscr2 ← md;
return;* make it possible to return

cdWrite:* T = va, rscr = data
store ← t, DBuf ← rscr;
noop;
return;* make it possible to return

colForVa:* given a va, return its cache column
* T = 16 bit va. The 4 lsb pertain to munch, then skip the bits in the row then use 2 bits

return, t ← ldf[t,2,add[nBitsInRow, cacheShift]];* extract 2 bits for column

cacheAforVa:* T = va. Return the midas style "cache" addr
* for va. This subr to be used from Midas
pushReturn[];
rscr ← cacheRowMask0;* make mask = size of cache row bits
rscr ← (rscr) OR (cacheRowMask1);
rscr ← (rscr) OR (3c);* add mask for bits addressed by column
t ← ldf[t, nBitsInRow, cacheShift];* isolate cache row bits
t ← t AND (rscr);* isolate cache addr whose size is
* nBitsInRow + 2 (2 bits for the four columns)
returnP[];

presetCache:* t = hi8, rscr = low 16, rscr2 = CFlags
pcHi8 ← t;
pushReturn[];
va ← rscr;* save va
t ← rscr2;
pcFlags ← t;* save Cache flags

call[iMunchCtrl], t ← va;
presetL:
call[nextMunch];* SETS VA DIRECTLY!
skpif[alu#0];* see if more to do
branch[presetTag];
noop;

call[pcSetCflags];
call[pcSetAmemory];

branch[presetL];* loop again

presetTag:
t ← (va) - (100C);* we know this address is in the cache
call[resetTag];* now cause the tag to get reset

returnP[];

pcSetCflags:* private subroutine to presetCache
t ← link;* inits CFLAGS for "va" to contain value
Drlink ← t;* of pcFlags. This subr MUST NOT CALL
top level;* another subr that stores link in Drlink!

call[colForVa], t←va;* Set mcr to select appropriate row, column
call[makeUseMcrV];* for this va
t ← t OR (mcr.fdMiss);
t ← t OR (mcr.noRefHold);
call[setMCR];

call[pcGetCFlags];
t ← t # (cflags.mask);* invert only the cflags bits
t ← (va) - t;* compute value for BR
rscr2 ← t;
call[setBR], rscr ← (rscr)-(rscr);* BRLO = va-cflags, BRHI = 0

call[pcGetCFlags];* now set the cache flags
t ← t # (cflags.mask);* invert only the cflags bits
dummyRef ← t;
CFLAGS ← t;

subroutine;
returnUsing[Drlink];

pcSetAmemory:* private subroutine to presetCache
t ← link;* inits cache A memory to "contain" specific
Drlink ← t;* va. Sets BRHI to value of pcHi8! This subr
top level;* MUST NOT CALL another subr that stores
* link in Drlink!

call[colForVa],t←va;* set MCR for current column.
col ← t;
t ← mcr.fdMiss;
t ← t OR (mcr.noRef);
call[mcrForCol];

call[pcGetHi8];
rscr ← t;
call[setBR], rscr2 ← (rscr2) - (rscr2);* init BRHI = pcGetHi8

t ← r0;* perform the reference
STORE ← va, DBuf ← t;

subroutine;
returnUsing[Drlink];

%
Zero the cache. presume it has been init’d for va IN [0..3777B]
Clobber T (that all!)
%
* May 21, 1981 11:44 AM This routine was modified to provide for setting the cache to an arbitrary value.

zeroCache0:
pushReturn[];
top level;
branch[setCache], t← a0;

setCache0:
stkp+1;
stack← link;

setCache:
rscr← t;* value to use is in rscr

call[iCDvaCtrl], t←r0;
zcVaL:* FOR va IN [0..3777B] DO
call[nextVa];
skpif[alu#0], t←rscr;* exit if required. setup t=0
branch[zcXit];

branch[zcVaL],DBuf ←t,store←va;* cache[va] ← value

zcXit:
returnP[];

* October 14, 1978 3:13 PM
subroutine;
pcGetHi8:
RBASE ← rbase[pcHi8];
return, t ← pcHi8, RBASE ← rbase[defaultRegion];

pcGetCflags:
RBASE ← rbase[pcFlags];
return, t ← pcFlags, RBASE ← rbase[defaultRegion];

knowRbase[defaultRegion];
top level;

memSubrsDDone:;