INSERT[D1DLANG];
TITLE[LOADER];
*	Last edited: 4 May 1980

%Midas uses microinstructions assembled here to read and write the
machine state of Dorado.  D1DLANG defines the language.  Only the
"B", and "NOT A" alu operations are available.

D1DLANG is a modified version of D1LANG that assembles microinstructions
destined for loading into MIR rather than for D1 memories.  Instructions
are assembled in IM format here, and permuted into MIR format by the
loader in Midas.

Instructions here are executed by the following procedures in Midas:
	Xct(NOOP)		executes the instruction
	XctR16(RT,DVec)		executes RT and stores B into DVec!0
	XctR16C(RT,DVec)	executes RT and stores B' into DVec!0
	XctR16Link(RLINK,DVec)	executes RLINK with UseCPReg off, puts
				B into DVec!0, and turns UseCPReg on again.
	XctL16(LT,Value)	loads CPReg with Value, then executes LT.
	XctL16C(LT,Value)	loads CPReg with Value', then executes LT.
	XctLFF(WAKEUP,17)	adds the displacement 17 to the FF field of
				WAKEUP, then executes it.
	SetALUF(LAF0,n)		Sets up instruction with n added to ALUF
				field of LAF.(1795)
	SetRSTK(LRM0,n)		Sets up instruction with n added to RSTK
				field of LRM0.
Normally, Freeze and UseCPReg are true during execution of any
instructions, but UseCPReg is turned off before XctR16Link.

The "LdData" command in Midas.Midas ignores the LDR address symbols defined
here but goes ahead and loads MDATA, MADDR, DMUX, and $ABSOLUTE addresses
(because of the bit for these memories in the MEMCON table).  A consequence
of loading all these symbols is that greater symbol block fragmentation
occurs when a real microprogram is loaded.

The 34 memories and 23 registers use 57*2+166 words of symbol space.  The
5 MDATA, 11 MADDR, 85 DMUX, 13 $ABSOLUTE, 3 $ABS, and 12 MSTAT addresses
here use 129*3 + ~449 words (= 114+166+387+449 = 1116 words) of symbol
storage.
%

TARGET[LDRLC];

SET[XTASK,0];

RT:
NOOP:	PD_B_T, RSTK[0];	*No-op--must be at loc 0
TSTINS: B_RB, RSTK[0];
MKINS:	PD_B_T, RSTK[0], A_T;	*Modified by SetALUF and SetRSTK

RETN:	RETURN;
STARTX:	RETURN, B_RWCPREG;
*B_STACK = BLOCK for io tasks (***Stack&ChkUFL wrong here***)
GOLAST:	LONGBR[7777], B_STACK;
RTPC:	RDTPC_CPREG;
LTPC:	LDTPC_CPREG;
RLINK:	B_LINK;
LLINK:	B_RWCPREG;
TON:	TASKINGON;
TOFF:	TASKINGOFF;
WAKE0:	NOTIFY[0];	*Add 0 to 17 to FF to notify tasks 0 to 17
RIM0:	READIM[0];
RIM1:	READIM[1];
RIM2:	READIM[2];
RIM3:	READIM[3];
LIMLK:	IMLHR0POK_CPREG;
LIMLB:	IMLHR0PBAD_CPREG;
LIMLFK:	IMLHR0'POK_CPREG;
LIMLFB:	IMLHR0'PBAD_CPREG;
LIMRK:	IMRHBPOK_CPREG;
LIMRB:	IMRHBPBAD_CPREG;
LIMRFK:	IMRHB'POK_CPREG;
LIMRFB:	IMRHB'PBAD_CPREG;

LT:	T_CPREG;
RQ:	B_Q;
LQ:	Q_CPREG;
TFSHC:	T_SHC;
SHCFQ:	SHC_Q;
TFCNT:	T_CNT;
CNTFQ:	CNT_Q;
TFPTRS:	T_POINTERS;	*MEMBX, MEMBASE, STKOVF, STKUND, RBASE
TFTIOA:	T_TIOA&STKP;
TIOAFQ:	TIOA_Q;
STKPFQ:	STKP_Q;
RSTACK:	B_RB, RSTK[0], BLK[1];	*Kludge for no STKP=0 underflow check
WSTACK:	RB_CPREG, RSTK[0], BLK[1];
OUTPUTFQ:	OUTPUT_Q;
LRB0:	RBASE_0S;		*Add 0 to 17 to FF
LMB0:	MEMBASE_0S;		*Add 0 to 37 to FF
LMBX0:	MEMBX_0S;		*Add 0 to 3 to FF
RRM0:	B_RB, RSTK[0];		*Add 0 to 17 to RSTK
LRM0:	RB_CPREG, RSTK[0];
TFAF0:	T_ALUFMEM, ALUF[0];	*Add 0 to 17 to ALUF
LAF0:	ALUFMRW_Q, ALUF[0];
LAF0T:	T_(ALUFMRW_Q), ALUF[0];
WF:	WF_T;
RF:	RF_T;
RMSH:	SHIFTNOMASK, BSEL[4], FF[0];	*Add shift control to FF
TSH:	SHIFTNOMASK, BSEL[7], FF[0];	*Add shift control to FF
SFTN:	SHIFTNOMASK, RSTK[0];
SFTL:	SHIFTLMASK, RSTK[0];
SFTR:	SHIFTRMASK, RSTK[0];
SFTB:	SHIFTBOTHMASKS, RSTK[0];

RFINFO:	B_FAULTINFO';
RVAHI:	B_VAHI;
RVALO:	B_VALO;
RPIPE2:	B_PIPE2';
RMAP:	B_MAP';
RERRS:	B_ERRORS';
RPIPE5:	B_PIPE5;
BRLOFT:	BRLO_T;
BRHIFT:	BRHI_T;
MCRFT:	LOADMCR[T,T];
SRNFT:	PROCSRN_T;
SRNFQ:	PROCSRN_Q;
CFLAGSFT:	CFLAGS_T;
RCONFG:	B_CONFIG';
LTSYN:	LOADTESTSYNDROME;
DUMMYFT:	DUMMYREF_T;
FETCHM:	FETCH_T;
STORETQ:	STORE_T, DBUF_Q;
RDMAP:	RMAP_RB, RSTK[0];
MAPTQ:	MAP_T, MAPBUF_Q;	*Emulator only
TFMD:	T_MD;
FLUSHT:	FLUSH_T;	*Emulator only

BRKINSFQ:	BRKINS_Q;
RPCX:	B_PCX';
PCFFQ:	PCF_Q;
RIFL:	B_IFUMRH';
IFLFQ:	IFUMRH_Q;
RIFH:	B_IFUMLH';
IFHFQ:	IFUMLH_Q;
REVA:	B_EVENTCNTA';
ISEVFQ:	INSSETOREVENT_Q;
IFRES:	IFURESET;
NOSKED:	NORESCHEDULE;
SKED:	RESCHEDULE;
EVBFQ:	EVENTCNTB_Q;
TESTFQ:	IFUTEST_Q;
REVB:	B_EVENTCNTB';
WAKE17:	NOTIFY[17];

SET[XTASK,2];

IOFET:	IOFETCH_T;

SET[XTASK,0];
LMBSX0:	MEMBASEX_0S;	*Add 0 to 3 to FF

**Normally add new instructions here.  If overflow LDR size limit, have to
**expand MEMLEN entry in d1tables.asm for LDR memory; D1DLANG.MC length
**of LDR must agree.

**Do not reorder--assembled in MDATA.ASM
MDATA[BITS-CHECKED,0];	MDATA[SHOULD-BE,1];	MDATA[DATA-WAS,2];
MDATA[BITS-DROPPED,3];	MDATA[BITS-PICKED,4];

MADDR[LOW-ADDR,0];	MADDR[HIGH-ADDR,1];	MADDR[LOOP-COUNT,2];
MADDR[DWATCH,3];	MADDR[CURRENT-ADDR,4];	MADDR[ADDR-INC,5];
MADDR[ADDR-INTERS,6];	MADDR[ADDR-UNION,7];	MADDR[NFAILURES,10];
MADDR[COMM-ERRS,11];	MADDR[MIR-PES,12];	MADDR[VMBASE,13];

DMUX[CJNK0,0];		DMUX[CIAINC,1];		DMUX[CIA,2];
DMUX[BNT,3];		DMUX[PENC,4];		DMUX[TNIA,5];
DMUX[BNPC,6];		DMUX[CTASK,7];		DMUX[NEXT,10];
DMUX[CTD,11];		DMUX[RA,12];		DMUX[TOPE,13];
DMUX[CJNK1,14];		DMUX[FFEQ,15];		DMUX[CJNK3,16];
DMUX[READY,17];	

DMUX[ALUB,20];		DMUX[ALUA,21];		DMUX[ABCON,22];
DMUX[PERR,23];		DMUX[SHMV,24];		DMUX[MAR,25];
%DMUX[SPARE,26];%	DMUX[PRFA,27];		DMUX[SCCON,30];
DMUX[QPDCON,31];	DMUX[ALUCON,32];	DMUX[NEXTCL,33];
DMUX[RADDR,34];		DMUX[STKRB,35];		DMUX[RTSB,36];
DMUX[PJUNK,37];

DMUX[PVAH,40];		DMUX[PVAL,41];		DMUX[MAPAD,42];
DMUX[HIT,43];		DMUX[HOLD,44];		DMUX[PAIR,45];
DMUX[PIPEAD,46];

DMUX[MEMD0,50];		DMUX[DAD,51];		DMUX[FD,52];
DMUX[EC,53];		DMUX[TSYN,54];		DMUX[MDMAD,55];
DMUX[DADE,56];		%MCR=57 is a register%

DMUX[MAPBUF,60];	DMUX[P34INEC,61];	DMUX[MCDTSK,62];
DMUX[STA,63];		DMUX[APESRN,64];	DMUX[STOUT,65];
DMUX[TAGAT,66];		DMUX[MEMST,67];
DMUX[FLTMEM,71];	DMUX[RFSSRN,72];	DMUX[EC1MAKE,73];
DMUX[MAPCTRL,74];	DMUX[PEEC,75];		DMUX[INMAP,76];

DMUX[KSTATE,100];	DMUX[KSTAT,101];	DMUX[KRAM,102];
DMUX[KTAG,103];		DMUX[KFIFO,104];	DMUX[ERX0,105];
DMUX[ETX,106];		DMUX[ERX1,107];

DMUX[CLKRUN,110];

DMUX[MEMRQ,120];	DMUX[LOADS,121];	DMUX[HJ,122];
DMUX[MX,123];		DMUX[JMPEXC,124];	DMUX[PCJ,125];
DMUX[FFK,126];		DMUX[IDLY,127];

DMUX[APTRS,140];	DMUX[BPTRS,141];	DMUX[ITEMS,142];
DMUX[SPSIZE,143];	DMUX[RESON,144];

DMUX[TEMP,160];		DMUX[AAD,161];		DMUX[MEMB,162];
DMUX[BMUX,163];		%DMUX[ESTAT,164];%	DMUX[OLDCIA,165];

$ABSOLUTE[OUTOFSPEC,1];

MSTAT[VOLTS,0];		MSTAT[AMPS,1];		MSTAT[TEMP0,2];
*MSTAT[FVOLTS,5];	MSTAT[FAMPS,6];		MSTAT[FTEMP0,7];
MSTAT[MINVOLTS,12];	MSTAT[MINAMPS,13];	MSTAT[MINTEMP0,14];
MSTAT[MAXVOLTS,17];	MSTAT[MAXAMPS,20];	MSTAT[MAXTEMP0,21];

$ABS[ZPTR,57];
$ABS[ZPC,60];		$ABSOLUTE[ZS,142];	$ABSOLUTE[ZP,143];
$ABSOLUTE[ZA,144];	$ABSOLUTE[ZX,145];	$ABSOLUTE[ZY,146];
$ABSOLUTE[BADSUPPLYSPEC,147];	$ABSOLUTE[PROBLEMS,150];

$ABS[ZSUBPC,65];	$ABSOLUTE[ZSUBS,154];	$ABSOLUTE[ZSUBP,155];
$ABSOLUTE[ZSUBA,156];	$ABSOLUTE[ZSUBX,157];	$ABSOLUTE[ZSUBY,160];

END;