//D1simmi.d -- memory and ifu declarations for the DMux simulator
//	Last edited: 3 June 1981

structure MC:
[
g0		word 43B	//40B words
//!dPVAH			Tn ge 2 & no clock
//!dPVAL			Tn ge 2 & no clock
//!dMAPAD			Never**

//HIT
g1		bit 7
MiscPCHPx	bit	//Tn ge 2
ColVic		bit 2	//Tn ge 2 unless T1EcHasA % (Hit & T1Dbusy)
HitColVApar	bit	//0 on miss
HitColDirty	bit	//0 on miss
Hita		bit	//(Tn ge 2) & ForceMiss
			//(**should also check when PairHasA false)
g2		bit 3

//HOLD **Structure violated**
g3		bit 2
HaveMC		bit
WantCHdlyx	bit	//Tn ge 1
MiscHoldx	bit	//Tn ge 2
MDholdx		bit	//Tn ge 2
RefHoldx	bit	//(Tn ge 2) & not miss with ForceMiss
BLretry		bit	//Forced to 0
AwasFreex	bit	//Tn ge 2
Dbusy		bit	//Tn ge 2
DbufBusy	bit	//Tn ge 2
AtookST		bit	//Tn ge 2
SomeExtHoldx	bit	//On StkError % CHoldReq
Afreex		bit	//EcHasA
StartMapx	bit	//Always
AwantsMapFSx	bit	//Always

//PAIR **Structure violated**
StoregInA	bit	//EcHasA % (Tn ge 2)
IoStoreInA	bit	//EcHasA % (Tn ge 2)
MapgInPairx	bit	//Tn ge 2
FlushInA	bit	//EcHasA % (Tn ge 2)
PrefetchInA	bit	//EcHasA % (Tn ge 2)
IfuRefInA	bit	//EcHasA % (Tn eq 2)
IoRefInAx	bit	//EcHasA % (Tn ge 2)
CacheRefInA	bit	//EcHasA % (Tn ge 2)
g4		bit
PrivRefInPair	bit	//Tn ge 2
VicInPairx	bit	//(Tn ge 2) & (WantVic' % ForceDirtyMiss)
FSinPairx	bit	//(Tn ge 2) & (FlushInA' % Miss)
bEcHasA		bit	//Tn ge 2
KillIfuRef	bit	//Always
gPrVArow	bit	//Tn eq 2
PairFullx	bit	//Tn ge 2

//PIPEAD
PipeAd		bit 4	//Tn eq 2
CacheConfig	bit 2	//Never
PageConfig	bit 2	//Never
g5		byte

g6		word 8

//MCR
dVAgVic		bit	//Never
ForceDirtyMiss	bit	//Never
UseMcrV		bit	//Never
Victim		bit 2	//Never
NextV		bit 2	//Never
DisBR		bit	//Never
DisCflags	bit	//Never
DisHold		bit	//Never
NoRef		bit	//Never
g7		bit 2	//Never
WakeOnCL	bit	//Never
ReportSEx	bit	//Never
NoWakeups	bit	//Never

//!dAAD never**
//!dMEMB never**
]

structure MD:
[
g0		word 50B

//MEMD0
SinD00		bit	//Never
CD00		bit	//Never
D0in00		bit
D1in00		bit
EcSout00x	bit
g1		bit 3
D00		bit
dMD00		bit
Fout00		bit
g2		bit 5

//DAD--all bits predicted when ProcVA and Dad loaded identically;
//Dad9=13 predicted on ClearWA.
Dad		bit 13	//2-9 low true
Dad1		bit 3

//FD
FgD		bit	//Tn ge 2
DgDbuf		bit	//Tn ge 1
SoutgD		bit	//Tn ge 1
FoutgD		bit	//Tn ge 1
DgCD		bit	//Tn ge 1
MDgD		bit	//Tn ge 1
MakeMDMgDx	bit	//Always from the equiv MemX signal
bFastDgDbuf	bit	//Always
Dbufgx		bit	//Tn ge 1
DadHgx		bit	//Tn ge 2
DontLoad1	bit	//Always
GenPh1		bit	//(Tn ge 2) & EnEcGen
DontWriteMDM	bit	//Tn eq 2
g3		bit 3

//EC
g4		bit 4
StartEcChkx	bit	//Always
StartEcGenx	bit	//Always
g5		bit
EcInD		bit 2	//Never
WordInErrorx	bit	//When DisableEc true
DisableEcx	bit	//Not now--could predict at Tn eq 3
ChkPh1		bit	//(Tn ge 2) & preEcEn
ChkPH4x		bit
ChkLastPh6x	bit
DoubleErrorx	bit
ChkErrEnx	bit

//TSYN
tSyn		byte	//tSyn0:6 and 7x
g6		byte

//MDMAD
MDMadx		word	//Tn ge 2

//DADE
DCExc		bit 4	//Two chip enables always predicted false,
			//other two if (T1Transport & (Tn ge 2))
WriteD0xe	bit	//Tn ge 2
WriteD1xd	bit	//Tn ge 1
g7		bit 10
]

structure MX0:
[
g0		word 61B	//60B words, MAPBUF	//Tn ge 2

//P34INEC
Mapbuf1617	bit 2	//Tn ge 2
ProcTagInA	bit	//Tn ge 2
PrivRefinPair	bit	//Always--**copy of MemC**
Pipe34Ad	bit 4	//Tn ge 2
WPinEc1		bit	//Tn ge 2
MapTroubleinEc1	bit	//Tn ge 2
TagInEc2	bit	//Never
CacheRefInEc2	bit	//Never
StoregInEc2x	bit	//Never
IFURefInEc2	bit	//Never
MapPEInEc2	bit	//Never
MapTroubleInEc2	bit	//Tn ge 2

//MCDTSK
MDMtagAd	bit 4	//Always
CurTask		bit 4	//Always
ProcTag		bit	//Always
MDMtagx		bit	//CacheRefInPair & (Atask eq CurTask)
AteqCurtx	bit	//Always
DteqCurtx	bit	//Always
Dtask		bit 4	//Never

//STA
VictimInST	bit	//Tn ge 2
STIdlex		bit	//Always
StartST		bit	//Always
STWaitMemx	bit	//Tn ge 2
STState		bit 4	//Tn ge 2
STfreex		bit	//Tn ge 2
VictimInA	bit	//Always--**Not much help since VicInPair on MemC**
MapRfshDly	bit	//Tn ge 1
RefUsesDinEc1	bit	//(Tn ge 2) & StartEc1
AWordRefToD	bit	//Always
MapWantsPipe	bit	//Tn ge 2
MapFree		bit	//Tn ge 2
UseAsrn		bit	//Tn ge 2

//APESRN
ASrn		bit 4	//Tn ge 2
ProcSrn		bit 4	//Tn ge 2
MapIs16K	bit	//Never
MapIs64K	bit	//Never
MapIs256K	bit	//Never
RfshAd0		bit	//Never
Ec2Srn		bit 4	//Tn ge 2

//STOUT
LoadEnx		bit	//Never (**could predict at Tn eq 3)
EcLoadEnx	bit	//Never (**could predict at Tn eq 3)
ShiftEnx	bit	//Tn ge 2
EnEcGenx	bit	//Tn ge 2
MapWaitSTx	bit	//Tn ge 2
STPerrNowx	bit	//Never
EnableAllMods	bit	//Never (**could predict at Tn eq 3)
StartEc1	bit	//Never
PairFull	bit	//Always--**Copy of MemC signal**
Transporta	bit	//Always
ECFaultx	bit	//Never
MemErrorx	bit	//Never
g1		bit	//Never
ChipsAre25616K	bit	//Never
ChipsAre64K	bit	//Never
VicSTPerr	bit	//Never**
]

structure MX1:
[
g0		word 66B

//TAGAT
MemColSela	bit	//Never (**could predict at Tn eq 3)
EcHasA		bit	//Tn ge 2
Ptag		bit	//Never
MapWaitEc2	bit	//Tn ge 2
Dtagx		bit	//Tn ge 2
sHold		bit	//Always
MapWaitMemStatex	bit	//Always
MapRfsh		bit	//Always
AcanHaveD	bit	//Tn ge 2
CacheRefInPairx	bit	//Tn ge 2--**CacheRefInA on MemC**
EcWordRefToD	bit	//Always
ChkLastPh6	bit	//Always
Atask		bit 4	//Tn ge 2

//MEMST
MapWaitMemD	bit	//Tn ge 2
MapWaitMemIO	bit	//Always
MemIdlex	bit	//Always
MemFree		bit	//Tn ge 2
MemState	bit 4	//Tn ge 2
FinNext		bit	//Tn ge 2
MemRfsh		bit	//Tn ge 2
StopFinTaskLoad	bit	//Tn ge 2
DdataGoodx	bit	//Tn ge 2
MakeSoutgD	bit	//Tn ge 2
MakeTransport	bit 3	//***not yet***

g1		word

//FLTMEM
g2		bit 3
ProcSrngx	bit	//Tn ge 1
Faults		bit	//Never (**could predict sometimes)
LoadFltSrn	bit	//If independent of FaultSrn eq 0
ReportFault	bit	//Always
MapPEInMem	bit	//Never
MapTroubleInMem	bit	//Never
RfshInMem	bit	//Tn ge 2
WriteInMemx	bit	//Tn ge 2
MemWP		bit	//Never
IOFetchInMemx	bit	//Tn ge 2
RefUsesD10InMemx	bit	//Tn ge 2
RefUsesDInMem	bit	//Tn ge 2
DirtyIOFetchInMem	bit	//Tn ge 2

//RFSSRN
STPerr		bit	//Never (**could predict if NoWakeups % no clock)
MapPerr		bit	//Never (**could predict if NoWakeups % no clock)
HitPerr		bit	//Never (**could predict if NoWakeups % no clock)
WantRfsh	bit	//Tn ge 2
NeedRfsh	bit	//Always
StartMema	bit	//Tn ge 2
StkWake		bit	//Never
gFaultInfoDlyx	bit	//Never (**could predict at Tn eq 3)
MapSrn		bit 4	//Tn ge 2
MemSrn		bit 4	//Tn ge 2
]

structure MX2:
[
g0		word 73B

//EC1MAKE
StartEc2x	bit	//Tn ge 2
Ec1Freex	bit	//Tn ge 2
Ec1Idle		bit	//Always
Ec1FnState	bit 5	//Tn ge 2
EcWantsAa	bit	//Tn ge 2
FoutNext	bit	//Tn ge 2 usually
MakeFoutgD	bit	//Tn ge 2 usually
MakeDgCD	bit	//Tn ge 2 usually
MakeDgDbuf	bit	//Always
MakeFgD		bit	//Always
MakeMDgD	bit	//Always
MakeMDMgDx	bit	//Tn ge 2

//MAPCTRL
MapBufHi	bit 2	//Never
MapRASx		bit	//Tn ge 2 when forced high
MapCASx		bit	//Tn ge 2 when forced high
MapWEx		bit	//(Tn ge 2) % StartMap
RefWEx		bit	//Tn ge 2
DirtyWEx	bit	//(Tn ge 2) % StartMap
g1		bit
MapWait		bit	//Always
WantMapWaitx	bit	//Always
ValidMapFltInEc2x	bit	//Tn ge 2
MapFnxState	bit 5	//Tn ge 2

//PEEC
PEsrn		bit 4	//Always
Ec1Srn		bit 4	//Tn ge 2
CacheLoadx	bit	//Always
Ec2Free		bit	//Tn ge 2
Ec2Idle		bit	//Always
Ec2FnState	bit 5	//Tn ge 2

//INMAP
RefUsesDInMapx	bit	//DirtyIOFetchInMap % ((Tn ge 2) & StartMap)
RefUsesD10InMapx	bit	//Tn ge 2
DirtyIOFetchInMapx	bit	//Never
WriteInMapx	bit	//Tn ge 2
IOFetchInMapx	bit	//Tn ge 2
gMapInMap	bit	//Never
StoregInMapx	bit	//Tn ge 2
EcWantsPipe4x	bit	//Tn ge 2
g2		byte
]

structure IFU0:
[
//K stable means no IFUM write and InstrSet doesn't change, and it implies
//that Testing' remains false also.

g0		word 120B

//MEMRQ
PcF815		byte	//Tn eq 2 if K stable
NewF		bit	//Tn eq 2 & Testing' (in D1SimMem)
KillResponse	bit	//Tn ge 1 & Testing'
Pause		bit	//Tn ge 2 if K stable
RefOutstanding	bit	//Never (need TestMemAck)
IncPcF		bit	//Never (Need TestMemAck)
IncPcFGx	bit	//Always
WantIfuRefx	bit	//Always
ThreeOutOfFive	bit	//Always

//LOADS
ValidRam	bit	//Always
JgOddF		bit	//Always
RealPcFG15	bit	//Tn eq 2 & K stable
FDv		bit	//Tn eq 2 & K stable
GDv		bit	//Tn eq 2 & K stable
HDv		bit	//Tn eq 2 & K stable
JDv		bit	//Tn ge 2 & K stable
MDvx		bit	//Tn ge 2 & K stable
EnableFGx	bit	//Always
XLd		bit	//Always
AlphaXLd	bit	//Always
BrkLd		bit	//Tn ne 1
MLd		bit	//Always
InstrAddrLd	bit	//Tn ge 2
JLda		bit	//Always
GLdx		bit	//Always

//HJ
H		byte	//Never
J		byte	//Tn ge 2 & Testing' unless IFUM write when
			//no clock or on J_H the 1's are simulated.

//MX **Structure violated**
TwoAlphaX	bit	//Tn ge 2 & Testing'
JFault		bit	//Tn ge 2 & K stable & IfuReset'
HFaultx		bit	//Tn eq 2 & Testing'
NMeq17		bit	//Tn ge 2 & K stable
TwoAlphaM	bit	//Tn ge 2 & K stable
TypeJumpMx	bit	//Tn ge 2 & K stable
LengthM		bit 2	//Tn ge 2 & K stable
DSel		bit 2	//Tn ge 2 & Testing' unless XShift with DSel eq 0
LengthX		bit 2	//Tn ge 2 & Testing'
NX		bit 4	//Tn ge 2 & Testing' when unclocked or NM=17

//JMPEXC
Exception	bit	//Always
SayNotReady	bit	//Always
WantResched	bit	//Tn ge 2 & Testing'
SawRamParityErr	bit	//During Reset only **
SawFGParityErr	bit	//During Reset or when testing **
ReschedPending	bit	//Tn ge 2 & Testing' & ExceptionDispatch insignificant
KReady		bit	//Always
g1		bit
ZapFGH		bit	//Always
ZapJ		bit	//Always
NewJ		bit	//Tn ge 2 & K stable
DoJump		bit	//Tn ge 2 & K stable
TurnOffAlu	bit	//Tn even
NewGo		bit	//Always
BMuxEnable	bit	//Tn even
FGFault		bit	//Never (Need FFault muffled)
]

structure IFU1:
[
g0		word 125B

//PCJ
PcJ815		byte	//Tn eq 2 & K stable
MLdDlyx		bit	//Tn ge 2 & Testing'
BetaInM		bit	//Tn ge 2 & Testing'
FGErrDly	bit	//Tn ge 2
RamErrDly	bit	//Tn ge 1
InstrSet	bit 2	//Never (could predict at Tn eq 3)
OBJinJ		bit	//Tn ge 2 & Testing'
OBJinJd		bit	//Tn ge 2 & Testing'

//FFK
Testg		bit	//Tn ge 1
GenOutgx	bit	//Tn ge 1
NewPcg		bit	//Tn ge 2 & Testing'
IfuReset	bit	//Tn ge 2
BrkInsg		bit	//Tn ge 2 & Testing'
Testing		bit	//Tn ge 2
SignXx		bit	//Never
BrkPending	bit	//Tn eq 2 & Testing'
g1		bit 3
TypeJumpKx	bit	//Never
TypePauseKx	bit	//Never
LengthK		bit 2	//Never
SignK		bit	//Never

//IDLY **Structure violated**
GDvDly		bit	//Tn eq 2 & Testing'
HDvDly		bit	//Tn eq 2 & Testing'
FDvDly		bit	//Tn eq 2 & Testing'
KReadyDly	bit	//Tn ge 2 & K stable
GLdDlyx		bit	//Tn eq 2 & K stable
IncPcFGDlyx	bit	//Tn eq 2 & K stable
GFaultDlyx	bit	//Never
ExceptionDly	bit	//Tn ge 2 & Testing'
g2		bit 2
TestMakeFgD	bit	//Tn ge 2
NK		bit 4	//Never
TwoAlphaK	bit	//Never
]