//D1sim.d -- declarations for Midas D1 DMux simulator
//	Last edited: 19 July 1979

structure C:
[ //CJNK0
Stop		bit	//Always
preStartCyclea	bit	//Always
dStartCycle	bit	//Always
Phase0		bit	//Always
Phase4		bit	//Always
RWTPCorRWIM	bit	//Always
BigBorBDisp	bit 2	//Tn ge 2 & no switch
RWIMTPCx	bit 4	//WIMx, RIMx, WTPCx, RTPCx	//Always
g0		bit 4

g1		word 9	//CIAINC Tn ge 1
			//CIA Tn ge 2
			//BNT Tn ge 2
			//PENC Always
			//TNIA Always unless Return or IfuJump
			//BNPC Never
			//CTASK Tn ge 2
			//NEXT Always
			//CTD Tn ge 1
//RA
CSBDbx		bit 4	//Always
RAQuad		bit 2	//no hardware implemented
RA		bit 10	//Always

TOPE		word	//Always **Leading bit**

//CJNK1
Call		bit	//Always if low 4 bits of TNIA are predictable
bSWdx		bit	//Always
GND		bit	//Always
brtypex		bit 5	//LocalBr'a, IFUNext'a, LongJump'a,
			//Return'a, CondBr'a	//Always
bFFokxc		bit	//Always
FAeq01x		bit 2	//Always (FA=0' and FA=1')
bDoCBr		bit	//Never **
LinkgBMuxa	bit	//Tn ge 1
BgLinkx		bit	//Tn ge 1
RIMorRTPCdly	bit	//Tn ge 2
MulStep		bit	//Tn ge 2 & no switch

FFeq		word	//Always (FF=TaskingOn,
			//FF=TaskingOff, FF=MidasOn, 0,
			//FF=WriteLink, FF=Link_CPReg, FF=ReadLink,
			//0, 0, 0
			//FF=UseDMD, FF=TOffIsOk, FF=Notify'
			//FF=MulStep, FF=BDispatch, FF=BigBDispatch)

//CJNK3
g2		bit 4
Nexteq0		bit	//Always
CTaskeq0	bit	//Always
PEncGtTrueNextx	bit	//Always
PEncLtTrueNextx	bit	//Always
StopTasks	bit	//Tn ge 2
PEnceqCTx	bit	//Always
TPCBypass	bit	//Tn ge 2
PreEmptingx	bit	//Always
bHoldA		bit	//Always (in D1SimDec)
RepeatCurz	bit	//Always
bSwitchxa	bit	//Tn ge 2
bSwitchUpx	bit	//Tn ge 2

//READY
g3		bit
Ready		bit 15	//Tn ge 2

//ESTAT	Always (**only IMlhPE and IMrhPE checked**)
]

structure P0:
[
gw		word 18	//16 words
			//ALUB if driven from BMux or constant
			//ALUA Tn ge 1 from small constant & not shift

//ABCON **structure violated**
g0		byte	//Same as 8-15
MarMuxAEnx	bit	//Tn ge 1
AmuxEnx		bit	//Tn ge 1
Amux		bit 2	//Tn ge 1
IOBout		bit	//Tn ge 1
BmuxEnx		bit	//Tn ge 1
Bmux		bit 2	//Tn ge 1

//PERR
EMUx		bit	//Always (in D1SimCon)
CkMdParityx	bit	//Tn ge 2 (**Tn ne 1??)
g1		bit 6	//=xx, xx, IOPerr, MDPerr, RmPerr, TmPerr
StkSela		bit	//Always
StkSelSaved	bit	//Never
IOBoutSaved	bit	//Tn ge 2
gMDSaved	bit	//Never
IOPerr		bit	//Never
MDPerr		bit	//Never
RmPerr		bit	//Never
TmPerr		bit	//Never

g2		word 3	//SHMV if Pmux odd or not shift
			//MAR' Tn ge 1 from processor, no shift
			//	Tn eq 2 bits 8:15 when driven by IFU,
			//	Tn eq 2 bits 0:15 when not driven by IFU
			//SPARE unused

//PRFA
g3		byte	//Same as 8-15
LasteqCurrx	bit	//Tn ge 2 (in D1SimCon)
CurreqNextx	bit	//Always
Shiftx		bit	//Always
IOBinx		bit	//Tn ge 1
FAx		bit 4	//Always

//SCCON
g4		bit 3	//--, RepeatCurrC, Holda
LdTaskSimx	bit	//Always
g5		bit 3	//Same as 12-14
PropCntx	bit	//If DecCnt is false
g6		bit
RepeatCurrC	bit	//Always (in D1SimCon)
Holda		bit	//Always (from D1SimMem)
LdHoldSimx	bit	//Tn ge 1
FFshiftx	bit	//Always
ShcWriteEnx	bit	//Tn ge 1
LoadCntx	bit	//Always
DecCntx		bit	//Always (in D1SimCon)

//QPDCON **structure violated**
g7		bit 4	//Same as 8-11
ShiftBitsEnx	bit	//Tn ge 1
g8		bit 3	//Same as 13-15
QshiftLx	bit	//Tn ge 1
QshiftRx	bit	//Tn ge 1
RmaskEnx	bit	//Tn ge 1
LmaskEnx	bit	//Tn ge 1
ALUFWriteEnx	bit	//Always
Pmux		bit 3	//Tn ge 1
]

structure P1:
[
g0		word 26

//ALUCON
Pdata00		bit	//Tn ge 1 if Pdata source is ALU barring shifter
Pdata04		bit	//Tn ge 1 if source is ALU
TIOAWriteEnx	bit	//Tn ge 1
TIOABypass	bit	//Always
MBWriteEnx	bit	//Tn ge 2
MBBypass	bit	//Always
MBMux		bit 2	//Tn ge 1
aluCin		bit	//Never
Pdata08		bit	//Tn ge 1 if source is ALU
Pdata12		bit	//Tn ge 1 if source is ALU
aluFM		bit 5	//Never

g1		byte	//Same as 8-15
LastNextx	bit 4	//Tn ne 1
CurrLastx	bit 4	//Tn ne 1

//RADDR
Back2x		bit 4	//Tn ge 2
Back3x		bit 4	//Tn ge 2 (in D1SimCon)
RbWadr		byte	//1st 4 bits low true (sometimes Tn ge 2)
			//next 4 high true (Tn ge 2)

//STKRB
BCWriteEnx	bit	//Tn ge 2
CnteqZerox	bit	//Never**
IOatta		bit	//Never**
ResEqZerox	bit	//Never** (Could simulate the 4 ALU BC's at Tn eq 3
ResLtZerox	bit	//Never**  or at Tn eq 2 if T1Carry20 were muffled
ALUCarry	bit	//Never**  provided oldSWitch is false)
Overflowx	bit	//Never**
RmLtZerox	bit	//Never**
RBaseBypassx	bit	//Tn ge 1
SelRBaseWadrx	bit	//Always
RBaseWriteEnx	bit	//Tn ge 1
BumpRBase	bit	//Always
BumpRSTK	bit	//Always
StkPMux1	bit	//Always
StkPWriteEnx	bit	//Always
RmOddx		bit	//Never**

//RTSB **Structure violated**
ReSchedWrEnx	bit	//Always
NextMacro	bit	//Always (in D1SimCon)
g2		bit 6	//Same as 10-15
StkPSaveEnx	bit	//Tn ge 1
StkError	bit	//Never**
RbWriteEnx	bit	//Tn ge 2
RbSelMd		bit	//Tn ge 2
RbBypassDly	bit	//Never**
TbWriteEnx	bit	//Tn ge 2
TbSelMd		bit	//Tn ge 2
TbBypass	bit	//Tn ne 1

//PJUNK
FFokxa		bit	//Always
g3		bit
NextDatax	bit	//Always
g4		bit	//Same as BgExt
FFmem		bit 2	//Always
g5		bit 2	//RisIFdata, TisIFdata
FFokxb		bit	//Always
gMD		bit	//Always
gMDI		bit	//Always
BgExt		bit	//Always
SbTskDlyx	bit 2	//Never
RisIFdata	bit	//Always
TisIFdata	bit	//Always

//BMux if driven from ALUB
]