%
Page Numbers: Yes First Page: 1
Heading:
ifuChaosSubrs.mcMay 17, 1982 6:00 PM%
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Table of Contents
Organized by Occurence of subroutine in this Listing
SubroutineFunction
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ifuChaosPhase1:First half of current chaos test
makeIfuOpcodeRecord:Creates the data for the current opcode
fixIfuInstr:Modify ifuInstrRH so that it is legal.
makeIfuSequence:Make value that predicts ID sequence
readSeqTable:Reads the sequence table given t = index in table
getExpectedID:Returns current expected ID
initIfuChaosX:initi ifu chaos index variable
nextIfuChaosX:return next ifu chaos index variable (ALU=0 => done)
getIfuOpcode:return current value of ifuOpcode
getIfuAlpha:return current value of ifuAlpha
getIfuBeta:return current value of ifuBeta
getIfuInstrLH:return current value of ifuInstrLH
getIfuInstrRH:return current value of ifuInstrRH
getIfuInstrIL:return value of current ifuInstr’s IL
getIfuRBasereturn value of current ifuInstr’s rbase
getIfuMbasereturn value of current ifuInstr’s membase
setIfuILfield:modify IL field of an ifu instr in rscr, new value in t
setIfuTypefield:modify type field of an ifu instr in rscr; new val in t
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
%
May 17, 1982 6:01 PM
Add some comments.
September 17, 1979 11:20 AM
Fix bug in SetIfuTypeField -- apparently a lost fix, I remember doing this once before.
July 2, 1979 5:44 PM
Fix seqTable so that 1 byte opcodes w/ packed alpha And encoded constants return IL instead of NX, IL.
July 1, 1979 1:24 PM
Fix more bugs in getExpectedID -- beta is never sign extended.
July 1, 1979 12:55 PM
Fix some bugs in getExpectedID -- called getIfuInstrLH instead of getIfuInstrRH when trying to access sign extension bit.
June 30, 1979 6:30 PM
Fix several more bugs in makeIfuSequence.
June 30, 1979 5:39 PM
Change some labels in makeIfuSequence that still use "getIfu...", fix 2 bugs in computation of the index --using wrong register and failure to set a register. getExpectedID uses wrong mask to isolate an octal digit, sign extention logic is incorrect on IDisNX, IDisAlpha, IDisBeta.
June 29, 1979 5:19 PM
Change makeIfuOpcodeRecord’s call to getIfuSequence (no longer exists)into call on makeIfuSequence.
June 29, 1979 5:04 PM
Rename getIfuSequence to makeIfuSequence (since it always reconstructs the ifuSequence value rather than returning the current one), and fix a bug in computing whether or not 10B should get or’d into the table index -- skip/sex bug. Change getExpectedID to access ifuSequence directly rather than calling getIfuSequence.
June 29, 1979 4:18 PM
Add ;s to end of data statements that define the seqTable -- this clobbered the first instruction ofgetExpectedId.
June 29, 1979 3:31 PM
Change incorrect call to ifuSetInstrSet in ifuChaosPhase1 to setIUsingInstrSet. Fix small bugs in getIfuRbase, getIfuMbase.
June 29, 1979 11:56 AM
ifuChaosPhase1 called getIfuPc where it should have called getIfuOpcode.
June 29, 1979 10:59 AM
Fix bug in makeIfuOpcodeRecord -- neglected to call getIfuSequence and set
ifusequence.
June 29, 1979 10:03 AM
Fix bugs associated with fixIfuInstr. In particular, micro does not complain about the construct, "t ← not[ifu.ilMask];" It generates an instruction of "PD←3c" which is completely wrong. The proper syntax (I wrote it wrong) is "t ← not[ifu.ilMask!]C;".
June 24, 1979 5:54 PM
Add get(IfuRBase, Mbase, MBx).
June 24, 1979 4:28 PM
Remove all uses of dpf that deposit into rm or t!
June 19, 1979 10:02 AM
Fix fixIfuInstr and makeIfuOpcodeRecord--used hi true ifadm in mior and used wrong register in fii.
June 17, 1979 6:02 PM
Change location of sequence table to accommodate changes in postamble that accommodate ifu entrypoint locations.
Fix placement problems in fixInstr, getIfuSequence, readSeqTable
June 5, 1979 10:23 AM
Remove placement errors, add new procedures.
June 1, 1979 6:14 PM
Remove makeifuopcoderecord from ifuchaosphase1 so that an infinit loop can be constructed when a particular opcode goes astray.
May 22, 1979 11:55 AM
Add ifuChaosPhase1, various other subroutines, makeIfuOpcodeRecord’s microcode.
May 14, 1979 9:15 PM
Add makeIfuOpcodeRecord, getIfuIDsequence
May 2, 1979 10:53 AM
Construct this file and begin to write Mesa version of getExectedID.
%
* June 29, 1979 3:32 PM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ifuChaosPhase1
This subroutine uses the data record created by makeIfuOpcodeRecord to initialize all the raw data associated with the current test. It uses that data to write into IFUM, and storage.
The "opcode record", which is really a dedicated RM region, contains the following information:
ifuPcByte address in storage for the test opcode
ifuAlphaFirst data byte (may not be used by instruction)
ifuBetaSecond data byte (may not be used by instruction)
ifuOpcodeThe value of the opcode (ie., address, including instruction set bits, in the Ifu memory).
<other values of no concern here>
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ifuChaosPhase1:
pushReturn[];
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Write opcode, alpha, beta into storage
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
call[getIfuOpcode];* write opcode; begin by setting current
t ← ldf[t, 2, 10];* instruction set indicator
call[setIUsingInstrSet];
call[getIfuOpcode];
call[getIfuPc], rscr ← t;
call[putCDbyte], stack+1 ← t;* push addr of opcode onto stack
call[getIfuAlpha];* write Alpha
rscr ← t;
call[putCDbyte], t ← (stack)+1;
call[getIfuBeta];* write Beta
rscr ← t;
call[putCDbyte], t ← (stack&-1) + (2c);
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Write instruction into IfuMem
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
call[resetIfu];
call[getIfuInstrLH];
call[getIfuInstrRH], rscr ← t;
call[getIfuOpcode], rscr2 ← t;
call[putIfuWd];
call[resetIfu];
returnP[];
* June 29, 1979 5:20 PM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
makeIfuOpcodeRecord
Create all the data associated with the new opcode. This includes constructing the high and low words for the Ifu Memory, choosing the opcode value and instruction set, choosing alpha and beta, and assuring that the instruction is legal (no 3 byte jumps, no instructions of type (jump and pause).
makeIfuOpcodeRecord: PROCEDURE RETURNS [rec: IfuOpcodeRecord] =
BEGIN OPEN rec;
ifuPc ← getRandom[];
ifuAlpha ← getRandom[] and 377B;
ifuBeta ← getRandom[] and 377B;
ifuOpcode ← getRandom[] and 1777B;
ifuInstrHi ← getRandom[] and ignoreIfAdMmask;
ifuInstrLH ← getRandom[] and (ignoreParity);
[ifuInstrHi, ifuInstrLH] ← fixIfuInstr[ifuInstrHi, ifuInstrLH];
ifusequence ← getIfusequence[ifuInstrHi, ifuInstrLH];
END;
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
makeIfuOpcodeRecord: subroutine;
pushReturn[];
getRandom[];* 16-bit byte pc
ifuPc ← t;
getRandom[];* Alpha and Beta
RBase ← rbase[ifuBeta];
ifuBeta ← ldf[t, 10, 0];* extract right byte
ifuAlpha ← ldf[t, 10, 10];* extract left byte
RBASE ← rbase[defaultRegion];
getRandom[];* opcode, including instruction set bits
t ← t and (1777C);
ifuOpcode ← t;
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
The instruction, as it appears in the ifu memory, consists of two parts, the left and right halves. The left half contains the packed alpha bit (selected randomly) and the IM target address that is always chosen to be the IM address, opAt15. The right half contains the parity bits which this code masks out. Correct parity gets constructed when the words are written into the Ifu memory. The subroutine, fixIfuInstr, modifies il and it (length and type) to guarantee that the instruction is legal.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
getRandom[];* The actual instruction in Ifu Memory
rscr ← lshift[1, ifu.paShift]C;* isolate packed alpha
t ← t and (rscr);
rscr ← not (15c);* default IfadM = opAt15
rscr ← (rscr) and (ifu.adMask);* Remember that Ifad bits are low true.
t ← t or (rscr);
ifuInstrLH ← t;
getRandom[];
t ← t and (not[ifu.peMask!]C);* don’t set the parity bits in ifuRH
ifuInstrRH ← t;
call[fixIfuInstr];
call[makeIfuSequence];
ifuSequence ← t;
returnP[];
* June 29, 1979 10:08 AM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
fixIfuInstr
This subroutine guarantees that the ifuOpcodeRecord is legal. A randomly chosen instruction may contain zero length instructions, 3 byte jumps, or instructions that are both of type pause and jump. These are illegal and must not occur.
fixIfuInstr: PROCEDURE[hi: IfuHiPart, low:ifuLowPart] RETURNS [newHi: IfuHiPart, newLow: ifuLowPart] =
BEGIN
newHi ← hi;
newLow ← low;
IF low.il = 0 THEN newLow.il ← 3;-- zero length instructions are illegal
IF (newLow.il = 3) AND (newLow.type = jump) THEN newLow.il ← 2;
IF (newLow.type=jumpAndPause) THEN newLow.type ← jump;
END;
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
fixIfuInstr:
pushReturn[];
call[getIfuInstrRH];
call[getIfuIL], rscr ← t;* save ifuInstrRH in rscr
t ← t # (0c);* see if IL = 0
skpif[ALU=0];
branch[fixInstr2];*If so, reset it to 3
call[setIfuILfield], t ← 3c;* use rscr = instr, t = new il
IfuInstrRH ← t;
fixInstr2:
call[getIfuIL];
PD ← t # (3C);
skpif[ALU=0];* (IL bits low true) IF IL=3 AND
branch[fixInstr3];* (IL is not 3)
t ← ldf[rscr, ifu.jumpSize, ifu.jumpShift];
PD ← t;* jump is low true
branch[fixInstr3, ALU#0], t ← 2c;* ...IF JUMP THEN IL ← 2
call[setIfuILfield];* use rscr = instr, t = new il
IfuInstrRH ← t;
fixInstr3:
t ← ldf[rscr, ifu.typeSize, ifu.typeShift];
PD ← t;* IF type = (JUMP AND PAUSE)
branch[fixInstr4, ALU=0], t ← rscr;
fixInstrCont:
IfuInstrRH ← t;
returnP[];
top level;
fixInstr4:
call[setIfuTypefield], t ← (r0)+1;
branch[fixInstrCont];
* July 2, 1979 5:44 PM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
makeIfuSequence
Return a sequence of values (each value is an octal digit -- 3 bits) that describes the sequence of data that the Ifu delivers in response to "←ID". The rightmost octal digit encodes the type of the current IfuData. As the test performs ←IDs, the routine that returns the expected IfuData and right shifts the sequence to keep in synch with the Ifu. Zero encodes "IL", so an unlimited number of ←IDs can be properly simulated.
The table, sequenceTable, which is addressed by information about the current opcode, contains a sequence for all the relevant different possible sequences that aren’t JUMP instructions. Remember that all jump instructions return ID = IL. The indeces for the table consist of the concatenation of the following bits: <nx=17><pAlpha><IL0><IL1>. Thus there 20B entries that range [0..17B]. The bit nx=17 means that there’s no encoded constant, pAlpha means packed alpha is true, and IL0, IL1 are the instruction length bits.
Here is a table that interprets the octal digits in a sequence:
0 => IL
1 => nx
2 => alpha
3 => alpha1 (packed alpha -- left side)
4 = > alpha2 (packed alpha -- right side)
5 => beta
6,7 => ERROR
makeIfuSequence: PROCEDURE[hi:hiInstrPart, low: LowInstrPart] RETURNS[seq: ifuSequence] =
BEGIN
sequenceTable = ARRAY[0..17B] OF CARDINAL ←
[-- x refers to index (octal) in the table. The four bits that
-- address the entry are shown before the sequence. Illegal instructions
-- imply zero length instructions.
77777B,-- x=0,<0,0,0,0>illegal
01B,-- x=1,<0,0,0,il1>IL, nx
021B,-- x=2,<0,0,il0,0>IL, alpha, nx
0521B,-- x=3,<0,0,il0,il1>IL, beta, alpha, nx
77777B,-- x=4,<0,pA,0,0>illegal
00B,-- x=5,<0,pA,0,il1>IL USED to be 01, IL nx
0431B,-- x=6,<0,pA,il0,0>IL, pAlpha2, pAlpha1, nx
05431B,-- x=7,<0,pA,il0,il1>IL, beta, pAlpha2, pAlpha1, nx
77777B,-- x=10,<nx17,0,0,0>illegal
00B,-- x=11,<nx17,0,0,il1>IL
02B,-- x=12,<nx17,0,il0,0>IL, alpha
052B,-- x=13,<nx17,0,il0,il1>IL, beta, alpha
77777B,-- x=14,<nx17,pA,0,0>illegal
00B,--x=15,<nx17,pA,0,il1>IL
043B,-- x=16,<nx17,pA,il0,0>IL, alpha2, alpha1
0543B,-- x=17,<nx17,pA,il0,il1>IL, beta, alpha2, alpha1
];
IF low.type=jump THEN RETURN[seq←0];
IF low.il=0 THEN SIGNAL ZeroLengthInstr[hi, low];
x ← IF hi.nx=17=17 THEN 0 ELSE 10B;-- "nx17"
x ← x or (IF low.pAlpha THEN 4 ELSE 0);-- "pAlpha"
x ← x or (low.il AND 3);-- "IL0IL1"
seq ← sequenceTable[x];
IF seq = 77777 THEN SIGNAL illegalInstruction[hi, low];
RETURN;
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
makeIfuSequence:
pushReturn[];
call[getIfuInstrRH];
rscr ← t;* keep IfuInstrRH in T.
rscr2 ← ldf[t, ifu.jumpSize, ifu.jumpShift];
PD ← rscr2;
skpif[ALU#0];
branch[makeIfuSeqRet], t ← t-t;* jump instrs’ seq = 0
noop;* for placement.
call[getIfuIL];
PD ← t;
skpif[alu#0];
makeIfuSeqErr0:* should never see zero length instruction
error;
t ← (rscr) and (ifu.nMask);* now construct in rscr2 the index into
(t) # (17c);* the table.
skpif[ALU=0], rscr2 ← 10c;* assume nx = 17
rscr2 ← a0;* no, nx#17, there’s an encoded constant
call[getIfuInstrLH];* check for packed alpha
t ← ldf[t, ifu.paSize, ifu.paShift];
PD ← t;
skpif[ALU=0];
rscr2 ← (rscr2) or (4c);* packed alpha contributes 4B to index
call[getIfuIL];* IL contributes low 2 bits of index.
t ← rscr2 ← (rscr2) or t;
call[readseqTable];
makeIfuSeqRet:
returnP[];
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
readSeqTable
Actually reads the sequence table given t = index in table.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
set[seqTableLoc, 5000];
mc[seqTableLocC, seqTableLoc];
readSeqTable:
pushReturnAndT[];
rscr ← seqTableLocC;
t ← (stack) and (17c);
t # (stack);
skpif[ALU=0], t ← t rsh 1;
readSeqTableErr:* called with parameter > 7B
error;
t ← (rscr) + t;* this is the word address
branch[readSeqTableRH, r odd], stack;
noop;* for placement
call[getImLh];
PD ← t # (7c);
readSeqTableChk:
skpif[ALU#0];
readSeqTableErr2:
error;* got ’7’ which is illegal
pReturnP[];
readSeqTableRH:* read right half of sequence table
top level;
call[getImRh];
branch[readSeqTableChk], PD ← t # (7c);
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
seqTable
The entries in this table must be read left to right in increasing IM address. Ie., seqTable[1] is 01 and seqTable[2] is 21.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
data[(seqTable:
lh[77777]rh[01],at[seqTableLoc, 0])];
data[(lh[21]rh[521],at[seqTableLoc, 1])];
data[(lh[77777]rh[00],at[seqTableLoc, 2])];
data[(lh[431]rh[5431],at[seqTableLoc, 3])];
data[(lh[77777]rh[0],at[seqTableLoc, 4])];
data[(lh[2]rh[52],at[seqTableLoc, 5])];
data[(lh[77777]rh[0],at[seqTableLoc, 6])];
data[(lh[43]rh[543],at[seqTableLoc, 7])];
* July 1, 1979 1:26 PM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
getExpectedID
Return the currently expected value for "ID". We use the value indicated by the right most octal digit in ifuSequence. A side-efect of calling this routine is that the ifuSequence value gets right shifted.
getExpectedID: PROCEDURE[rec: IfuOpcodeRecord] RETURNS[expect: CARDINAL] =
BEGIN
type ← rec.ifuSequence AND 3b;
rec.ifuSequence ← (rec.ifuSequence rshift 3);
expect ← SELECT type FROM
0 => rec.ifuInstrLH.il;
1 => IF (rec.ifuInstrLH.sign # 0) AND ((rec.ifuInstrLH.nx and 10) # 0)
THEN 17776B or rec.ifuInstrLH.nx
ELSE rec.IfuInstrLow and 17B;
2 => IF (rec.ifuInstrLH.sign # 0) AND ( (rec.ifuAlpha and 200B) # 0)
THEN 177400B or rec.ifuAlpha
ELSE rec.ifuAlpha;
3 => ifuAlpha AND 17B;
4 =>(ifuAlpha rshift 4) AND 17B;
5 => rec.ifuBeta;
default => SIGNAL illegalIDsequence;
END;
END;
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
getExpectedID:
pushReturn[];
RBASE ← rbase[ifuSequence];
t ← ifuSequence, RBASE ← rbase[defaultRegion];
rscr ← t and (7c);* isolate current sequence digit, and
t ← rsh[t, 3];* replace current sequence with right
call[putIfuSequence];* shifted version
bdispatch ← rscr;* go compute correct ID
branch[expectedIDis];
set[IDisTbl, 4200];
expectedIDis:
branch[IDisIL],at[IDisTbl, 0];
branch[IDisnx],at[IDisTbl, 1];
branch[IDisAlpha],at[IDisTbl, 2];
branch[IDisAlpha1],at[IDisTbl, 3];
branch[IDisAlpha2],at[IDisTbl, 4];
branch[IDisBeta],at[IDisTbl, 5];
branch[IDisBad],at[IDisTbl, 6];
branch[IDisBad],at[IDisTbl, 7];
IDisIL:
call[getIfuIL];
branch[getExpectedIDret];
IDisNX:
call[getIfuInstrRH];
branch[getExpectedIDret], t ← t and (ifu.nMask);* t = sign extended nx
IDisAlpha:
call[getIfuInstrRH];* isolate signX into rscr
rscr ← ldf[t, 1, ifu.signShift];
call[getIfuAlpha];* get the value of alpha
PD ← rscr;
skpif[ALU#0];
branch[getExpectedIDret];* signX is not true, so NO sign extention
t and (200C);* see if hi order bit of alpha is set.
skpif[ALU=0];
t ← t or (177400C);* We must extend the sign
branch[getExpectedIDret];
IDisAlpha1:
call[getIfuAlpha];
branch[getExpectedIDret], t ← ldf[t, 4, 4];
IDisAlpha2:
call[getIfuAlpha];
branch[getExpectedIDret], t ← ldf[t, 4, 0];
IDisBeta:
call[getIfuBeta];
branch[getExpectedIDret];
IDisBad:
error;* rscr = sequence digit, ifuOpcodeRecord contains current info.
getExpectedIDret:
returnP[];
* June 29, 1979 3:33 PM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
initIfuChaosX
nextIfuChaos
initIfuChaosXinitialize ifu chaos loop control
nextIfuChaosXincrement and return next ifuchaos loop value (ALU=0 => no more)
getIFUxxxWhere xxx are the pieces of the ifuOpcodeRecord
setIfuILfieldrscr = ifuRH, t = hi true, new value for il. Return t = new ifuRH
setIfuTypeFieldrscr = ifuRH, t = hi true, new value fo type, Return t = new IfuRH.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
initIfuChaosX: subroutine;
t ← cm1;
return, ifuChaosX ← t;
nextIfuChaosX: subroutine;
RBASE ← rbase[ifuChaosX];
t ← ifuChaosX ← (ifuChaosX)+1, RBASE ← rbase[defaultRegion];
t - (ifuChaosEndC);
RETURN, t-(ifuChaosEndC);
getIfuOpcode: subroutine;
RBASE ← rbase[ifuOpcode];
return, t ← ifuOpcode, RBASE ← rbase[defaultRegion];
getIfuPc: subroutine;
RBASE ← rbase[ifuPc];
return, t ← ifuPc, RBASE ← rbase[defaultRegion];
getIfuAlpha: subroutine;
RBASE ← rbase[ifuAlpha];
return, t ← ifuAlpha, RBASE ← rbase[defaultRegion];
getIfuBeta: subroutine;
RBASE ← rbase[ifuBeta];
return, t ← ifuBeta, RBASE ← rbase[defaultRegion];
getIfuInstrLH: subroutine;
RBASE ← rbase[ifuInstrLH];
return, t ← ifuInstrLH, RBASE ← rbase[defaultRegion];
getIfuInstrRH: subroutine;
RBASE ← rbase[ifuInstrRH];
return, t ← ifuInstrRH, RBASE ← rbase[defaultRegion];
getIfuIL: subroutine;
RBASE ← rbase[ifuInstrRH];
t ← ldf[ifuInstrRH, ifu.ilSize, ifu.ilShift];
t ← not(t), RBASE ← rbase[defaultRegion];* return true sex
return, t ← t and (3c);
getIfuRBase:
pushReturn[];
call[getIfuInstrRH];
rscr2 ← ldf[t, 1, ifu.rbSelShift];
PD ← rscr2;
skpif[ALU=0], t ← (r0)+1;* (low true) 0 ==> rbase should be 1
t ← a0;* (low true) 1 ==> rbase should be 0
returnP[];
getIfuMBase:
pushReturn[];
call[getIfuInstrRH];
rscr ← ldf[t, 2, ifu.memBLow2Shift];
t ← ldf[t, 1, ifu.memBK34Shift];
PD ← t;
skpif[ALU=0], t ← rscr;
t ← t or (34C);* add 2 bits
returnP[];
putIfuSequence:
return, IfuSequence ← t;
setIfuILfield:
pushReturnAndT[];% enter w/ t = new IL bits, rt. justified,
and rscr = current value of ifuRH. Return T = new value for ifuRH. Original value in T is treated as if it were high true! We invert the bits before modifying the value found in rscr. Thus, this routine stores low true values into IL. Return with rscr unmodified.
%
stack ← not(stack);
stack ← (stack) and (ifu.ilMask);* force into low true value
t ← not[ifu.ilMask!]C;*remove current IL bits
t ← lcy[t,t, ifu.ILshift];
rscr ← t and (rscr);
stack ← lsh[stack, ifu.ilShift];* position new il bits
t ← t or (stack&-1);* add new bits & decrement stack
returnP[];
setIfuTypefield:
pushReturnAndT[];% enter w/ t = new type bits, rt. justified,
and rscr = current value of ifuRH. Return T = new value for ifuRH. Original value in T is treated as if it were high true! We invert the bits before modifying the value found in rscr. Thus, this routine stores low true values into type. Return with rscr unmodified.
%
stack ← not(stack);
stack ← (stack) and (ifu.typeMask);* force into low true value.
t ← not[ifu.typeMask!]C;*remove current type bits
t ← lcy[t,t, ifu.typeShift];
rscr ← t and (rscr);
t ← lsh[stack&-1, ifu.typeShift];* position new type bits
t ← t or (rscr);* add new bits & decrement stack
returnP[];