[_CD8_]<doradosource>IfuSources.dm!53>ifu3b.mc

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Ifu3b.mcMay 17, 1982 5:46 PM%

%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Organized by Occurence of subroutine in this Listing

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

beginIfu3b:"main control", it calls the test subroutines
ifuPcAdderTest:Force worst case carry propogation thru Ifu’s adder
iMiscEffects:Check miscellaneous side-effects, etc of IfuJump
iFastTest:Fast execution test (ifuJumps happen immediately)
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

May 17, 1982 5:46 PM
Miscellaneous comments.

May 6, 1982 11:18 PM
Add comments

June 18, 1981 10:13 AM
Fix bug in iMisc8-14....using wrong linkage for ifujumps.

June 17, 1981 3:43 PM
Add test for Amux, Bmux checkout for IfuData

May 27, 1981 11:42 AM
Add Fetch←ID test to iMiscEffects.

May 20, 1981 3:21 PM
Construct this file out of ifu3.mc

May 19, 1981 4:50 PM
Begin adding iMiscEffects test (for RestoreStkP, IDFetch←, Fetch←ID, etc.)

February 1, 1980 8:05 PM
Fix miscellaneous comments, fix performance bug in iFastTest.

September 19, 1979 1:14 PM
Set expectedDispatch<0 in beginIfu3 -- for robustness.

September 18, 1979 11:07 AM
Cause tests that enableConditionalHold to disableConditionalTask as well -- seem to have mysterious bug that is associated with tasking. Fix some comments in IfuXqtTest.

...

July 3, 1979 2:08 AM
Add noops for placement purposes. -- apparently setIUsingInstrSet causes some problems.

...

June 5, 1979 11:40 AM
Add calls to enableConditionalTask

...

May 30, 1979 10:16 AM
Extend ifuPcAdderTest to cover regular opcodes and two byte jumps.

...

April 26, 1979 5:10 PM
Remove initIfuCache thru ifuTestLoop--moved into ifuTestSubrs.mc.

...

Make iFastTest accessible to normal testing. (no longer infinite loop).

April 24, 1979 3:49 PM
Add Pc adder test.

* May 20, 1981 3:21 PM

beginIfu3b:
pushReturn[];
expectedDispatch←a1;

call[ifuPcAdderTest];* find out if jumps involving many carry propogates work
call[iMiscEffects];
call[iFastTest];
endIfu3b:
returnP[];

* June 5, 1979 11:35 AM

%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

See if the logic that performs jumps works properly when worst case carry conditions obatain. The idea is to have a loop that bounces back and forth between location 0 and location 177777B. There are three test cases: use one byte jumps, use two byte jumps and use a jump and a one byte normal opcode (the jump gets the Pc to the 17777X range and the normal opcode gets the Pc to 0).

%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

ifuPcAdderTest:
pushReturn[];
call[initIfuCache];
call[setIUsingInstrSet], t ← 3c;
noop;* for placement.
call[enableConditionalTask];

FETCH ← r0;* save contents of word 0, word 7777 in
stack+1←MD;* the stack.
t ← 77777C;
FETCH←t;
stack+1 ← MD;

ifuPcAdder2:% Test 2 involves two one byte jumps, one at location 0 and the other at location "-1":

Pc (byte addres)Contents of byte
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

0one byte jump .-1
177777one byte jump .+1
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

%

* Remember: putCDByte uses t= byte address, rscr=byte value to write into memory
t ← (r0);* putCDbyte takes t=byte addr,
* rscr=value to write into memory
rscr ← jumpM1;* one byte (jump .-1) in byte 0,
call[putCDbyte];* one byte (jump .+1) in byte 177777B
t ← 177777C;* remember, it is instruction set 3
rscr ← jump1;
call[putCDbyte];
t ← 2c;* begin with test 2.
stack+1 ← t;* there are 3 tests we’ll perform. keep test indicator in top of stack

ifuPcAdderReset:* Top of the test loop.
call[resetIfu];
PcF←r0;
call[ifuSetPcCont];

call[initITestCount];
ifuPcAdderL:* within each test, after an IfuJump,
call[nextITestCount];* control comes here
skpif[ALU#0];
branch[afterIfuPcAdder];

ifuJump[0];
ifuPcAdderCont:
branch[ifuPcAdderL];

ifuSetPcCont:* set KLINK so that this test can regain
pushReturn[];
call[ispc];* control from afterDispatch.
t←link;
klink←t;
returnP[];
ispc:
coreturn;
branch[ifuPcAdderCont];

* February 1, 1980 8:04 PM

top level;
afterIfuPcAdder:
PD ← stack ← (stack)-1;* see if we’re done w/ tests;
branch[ifuPcAdderXit, ALU<0], PD ← stack;
branch[IfuPcAddr0, ALU#0];* currently on test 1
ifuPcAdder1:% Test 1 involves a 2 byte jump at location zero to location "-3" where there are 3 one byte, normal opcodes:

Pc (byte addres)Contents of byte
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

02 byte jump opcode, sign extended
1-3
177775one byte, regular opcode
177776one byte, regular opcode
177777one byte, regular opcode
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

%
t ← cm1;
call[putCDbyte], rscr ← opNoop;
t ← cm2;
call[putCDbyte], rscr ← opNoop;
t ← 177775C;* -3
call[putCDbyte], rscr ← opNoop;
t←A0;
call[putCDbyte], rscr ← jumpML2;
t ← 1c;
call[putCDbyte], rscr ← 177775c;* 2 byte jump to .-3 at location 0
branch[ifuPcAdderReset];
ifuPcAddr0:% test 0 involves two 2 byte jumps between location 0 and location -2:

Pc (byte address)Contents of byte
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

02 byte jump, sign extended
1"-2"
1777762 byte jump
177777"2"
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

t ← A0;
call[putCDbyte], rscr ← JumpML2;
t ← 1c;
call[putCDbyte], rscr ← cm2;
t ← cm2;
call[putCDbyte], rscr ← jumpL2;
t ← cm1;
call[putCDbyte], rscr ← 2c;
branch[ifuPcAdderReset];

ifuPcAdderXit:* done with all our tests
t ← 77777C, stack&-1;* fix stack which has current test number on it, and then restore clobbered memory locations.
STORE ← t, DBuf ← stack&-1;
t←r0;
STORE←t, DBuf ← stack&-1;
call[disableConditionalTask];
returnP[];

* May 27, 1981 11:41 AM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

This test checks that miscellaneous effects associated with an IFUjump work properly:

IDFetch← must work.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

iMiscEffects:
pushReturn[];
%
Test RestoreStkP.

The basic idea is to set StkP to one value, do an IFU jump, set StkP do a new value then to do RestoreStkP. Then StkP should be equal to the original value. We check for original value = 1 and original value=376. There is an implementation problem with this test: the afterDispatch code insists upon writing into the Stack at StkP+1! thus we preserve the value at Stack[2] which is the stack location that will be clobbered when afterdispatch gets control (and StkP=1). We don’t care about the other location because it is so "high" in the stack that we never use it.

rscr3← current stkp,
rscr4← value of stack[2]
%
call[initIfuCache];
call[setIUsingInstrSet], t←3c;
t← (r0)+1;* for placement.
call[setPcF200], rscr4← t+1;* keep "2" in rscr for a moment
rscr3← Tioa&StkP;
call[setStkP], t← rscr4;* stkp=1 when IfuJump happens
branch[getiMisc1Cont], rscr4←Stack&-1;* rscr4← Stack[2]

iMiscJ1:* get here from getiMisc1Cont.
IfuJump[];* processor should save StkP as it executes this IfuJump

iMisc1Cont:* get here from AfterDispatch.
call[setStkP], t← a1;* now set StkP to a different value
call[iMiscGetStkP], RestoreStkP;* processor restores old StkP
t # (1c);* original value was 1
skpif[alu=0];
iMiscErr1:* RestoreStkP did not restore us
error;* to 1, the value before ifujump

* Now try the same thing, but use different values for StkP.

call[setStkP], t← 376C;
call[setPcF200];
branch[getiMisc2Cont];
iMiscJ2:
IfuJump[];
iMisc2Cont:
call[setStkP], t←a0;
call[iMiscGetStkP], RestoreStkP;
t#(376C);
skpif[alu=0];
iMiscErr2:* RestoreStkP did not restore us to
error;* 376B, the value before IFU jump.

* Restore the original value of Stack[2], StkP, then return.

call[setStkP], t← 2c;
t←rscr4;
Stack← t;
StkP← rscr3;

* May 6, 1982 11:11 PM
%
Test Fetch←ID. We assume Store←Id will work if Fetch works. The idea is to execute an ifujump for a 3 byte instruction w/ alpha=377C and beta=0.

First we set BrLo=377 THEN perform Fetch←ID. The pipeVa ought to be 377(BrLo)+377(Alpha).
We check for correct ID, correct Va, correct Md.

Set BrLo to zero and perform Fetch←ID. Check PipeVa, Id, Md.

%
t←1000C;* use byte location 1000
call[putCDbyteAddr];
call[putNextByte], t← opNoopL3;* Use 3 byte instruction w/
call[putNextByte], t← 377C;* ENCODED CONSTANT=3 (throw it away)
call[putNextByte], t← a0;* alpha=377B, beta=0
call[setPcF1000];

t←377C;
BrLo←t;
call[longWait],t←10C;
branch[getiMisc3Cont];
iMiscJ3:
IfuJump;
iMisc3Cont:
t←Id;* throw away encoded constant.
t← (Fetch←Id);
t#(377C);* first id should be 377
skpif[ALU=0];
iMiscErr3a:
error;* got incorrect Id (t)

rscr←VaLo;
t← t+t;
t#(rscr);
skpif[ALU=0];
iMiscErr3b:* va is wrong in pipe. should be 377+377
error;

rscr←a0;* now reset BrLo to zero
BrLo←rscr;
noop;

Fetch←t, rscr←Md;
(Md)#(rscr);
skpif[ALU=0];
iMiscErr3c:* data from memory is wrong
error;

* Try it again, only use ID=beta=0
t← (Fetch←Id);
Pd←t;* SECOND id should be 0
skpif[ALU=0];
iMiscErr4a:
error;* got incorrect Id (t)

rscr←VaLo;
skpif[ALU=0];
iMiscErr4b:* va is wrong in pipe. should be 0
error;

Fetch←t, rscr←Md;
(Md)#(rscr);
skpif[ALU=0];
iMiscErr4c:* data from memory is wrong
error;

* May 28, 1981 9:04 AM
%
Test Ifetch← code.

Ifetch← works by replacing the low 8 bits of the current base register with ID. Consequently the address computed by the memory system is the value
BR[0..23],,Id+Mar. Ie., the concatenation of the high bits of the current base register with Id plus the value on Mar.

Set the low 8 bits of BR to zero and non-zero values to see if Ifetch replaces those bits with Id.

We are still using the 3 byte opcode with alpha =377, beta=0.
%

call[setPcF1000];*This test uses BR=0
branch[getiMisc5Cont];
iMiscJ5:
IfuJump;
iMisc5Cont:
t←a0, RisID;* throw away encoded constant
IFetch←t;* Ifetch does not advance IFUdata
t←Id;* thus, this ID is same as one for IFetch
t#(377C);* first id should be 377
skpif[ALU=0];
iMiscErr5a:
error;* got incorrect Id (t)

rscr← VaLo;
(rscr)#t;* t=id
skpIF[alu=0];
iMiscErr5b:* Low bits of va should be 377=ID
error;

Fetch←t, rscr← Md;
(Md)#(rscr);
skpif[ALU=0];
iMiscErr5c:
error;

* test IFetch with brlo=377, ID=0 (means va should be zero)

t←377c;
BrLo←t, t←a0;
IFetch←t;* IFetch does not advance IfuData
t← Id;* thus, this ID is same as one for IFetch
rscr←a0;
BrLo←rscr, Pd←t;
skpif[ALU=0];* ID should be zero!
iMiscErr6a:
error;* got incorrect Id (t)

rscr← VaLo;
(rscr)#t;* t=id
skpIF[alu=0];
iMiscErr6b:* Low bits of va should be 0=ID
error;

Fetch←t, rscr← Md;
(Md)#(rscr);
skpif[ALU=0];
iMiscErr6c:
error;

* June 18, 1981 10:12 AM

% This test checks that RM & T, Amux and Bmux
The idea is to test the following sets of actions:
t← A← ID, B← opposite bits from ID
RM← A← ID, B← opposite bits from ID
T← B← ID, A← opposite bits from ID
RM← B← ID, A← opposite bits from ID
%
call[setPcf1000];
call[getiMisc7Cont];
iMiscJ7:
IfuJump;
iMisc7Cont:
rscr← a1;
Pd← Id;* throw away encoded constant
Pd← Id;* throw away alpha byte
T← A← Id, B← rscr;* ID is all zeros
skpif[ALU=0];
iMisc7Err1:* should have id=t=0
error;

call[setPcf1000];
call[getiMisc8Cont];
iMiscJ8:
IfuJump;
iMisc8Cont:
t← a1;
Pd← Id;* throw away encoded constant
Pd← Id;* throw away alpha byte
rscr← A← Id, B← rscr;* ID is all zeros
skpif[ALU=0];
iMisc8Err1:* should have id=t=0
error;

call[setPcf1000];
call[getiMisc9Cont];
iMiscJ9:
IfuJump;
iMisc9Cont:
rscr← a1;
Pd← Id;* throw away encoded constant
Pd← Id;* throw away alpha byte
T← T, TisID, A← rscr;* ID is all zeros
skpif[ALU=0];
iMisc9Err1:* should have id=t=0
error;

call[setPcf1000];
call[getiMisc10Cont];
iMiscJ10:
IfuJump;
iMisc10Cont:
t← a1;
Pd← Id;* throw away encoded constant
Pd← Id;* throw away alpha byte
rscr← rscr, RisID, A← rscr;* ID is all zeros
skpif[ALU=0];
iMisc10Err1:* should have id=t=0
error;

t←1000C;* use byte location 1000
call[putCDbyteAddr];
call[putNextByte], t← opSign3;* Use 3 byte instruction w/ sign bit, no encoded
call[putNextByte], t← 377c;* constant. alpha byte=377=>ID=-1=177777C

call[setPcf1000];
call[getiMisc11Cont];
iMiscJ11:
IfuJump;
iMisc11Cont:
rscr← a0;
T← A← Id, B← rscr;* ID is all ones
t # (177777C);
skpif[ALU=0];
iMisc11Err1:* should have id=t=all ones
error;

call[setPcf1000];
call[getiMisc12Cont];
iMiscJ12:
IfuJump;
iMisc12Cont:
t← a0;
rscr← A← Id, B← rscr;* ID is all ones
(rscr) # (177777C);
skpif[ALU=0];
iMisc12Err1:* should have id=t=all ones
error;

call[setPcf1000];
call[getiMisc13Cont];
iMiscJ13:
IfuJump;
iMisc13Cont:
rscr← a0;
T← T, TisId, A← rscr;* ID is all ones
t # (177777C);
skpif[ALU=0];
iMisc13Err1:* should have id=t=0
error;

call[setPcf1000];
call[getiMisc14Cont];
iMiscJ14:
IfuJump;
iMisc14Cont:
t← a0;
rscr← rscr, RisID, A← rscr;* ID is all ones
(rscr) # (177777C);
skpif[ALU=0];
iMisc14Err1:* should have id=t=all ones
error;

returnP[];

* May 6, 1982 11:16 PM
* miscellaneous subroutines for iMisc tests.

* SetPCF to 200 or 1000 +++++++++++++++++++++
setPcF200: subroutine;
t←200C;
PcF←t, RETURN;
setPcF1000: subroutine;
t←1000c;
PcF←t, RETURN;

* Set/Read StkP. value in T +++++++++++++++++++++
setStkP: subroutine;
StkP←t, RETURN;

iMiscGetStkP: subroutine;
t← Tioa&StkP;
RETURN, t← t and (377C);

*Set KLink for iMisc1 thru iMisc14 +++++++++++++++++++++
top level;
getiMisc1Cont:
call[iMisc1Setup];
klink← link, branch[iMiscJ1];
iMisc1Setup: subroutine;
coreturn;
branch[iMisc1Cont];

top level;
getiMisc2Cont:
call[iMisc2Setup];
klink← link, branch[iMiscJ2];
iMisc2Setup: subroutine;
coreturn;
branch[iMisc2Cont];

top level;
getiMisc3Cont:
call[iMisc3Setup];
klink← link, branch[iMiscJ3];
iMisc3Setup: subroutine;
coreturn;
branch[iMisc3Cont];

top level;
getiMisc5Cont:
call[iMisc5Setup];
klink← link, branch[iMiscJ5];
iMisc5Setup: subroutine;
coreturn;
branch[iMisc5Cont];

top level;
getiMisc7Cont:
call[iMisc7Setup];
klink← link, branch[iMiscJ7];
iMisc7Setup: subroutine;
coreturn;
branch[iMisc7Cont];

top level;
getiMisc8Cont:
call[iMisc8Setup];
klink← link, branch[iMiscJ8];
iMisc8Setup: subroutine;
coreturn;
branch[iMisc8Cont];

top level;
getiMisc9Cont:
call[iMisc9Setup];
klink← link, branch[iMiscJ9];
iMisc9Setup: subroutine;
coreturn;
branch[iMisc9Cont];

top level;
getiMisc10Cont:
call[iMisc10Setup];
klink← link, branch[iMiscJ10];
iMisc10Setup: subroutine;
coreturn;
branch[iMisc10Cont];

top level;
getiMisc11Cont:
call[iMisc11Setup];
klink← link, branch[iMiscJ11];
iMisc11Setup: subroutine;
coreturn;
branch[iMisc11Cont];

top level;
getiMisc12Cont:
call[iMisc12Setup];
klink← link, branch[iMiscJ12];
iMisc12Setup: subroutine;
coreturn;
branch[iMisc12Cont];

top level;
getiMisc13Cont:
call[iMisc13Setup];
klink← link, branch[iMiscJ13];
iMisc13Setup: subroutine;
coreturn;
branch[iMisc13Cont];

top level;
getiMisc14Cont:
call[iMisc14Setup];
klink← link, branch[iMiscJ14];
iMisc14Setup: subroutine;
coreturn;
branch[iMisc14Cont];

* February 1, 1980 8:04 PM

%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

This is a test that executes most ifuJumps very quickly. It "runs" the program written into word location 200 in the memory. The program it runs consists of a sequence of six one byte opcodes followed by "failing" conditional jump followed by a loop to the top of the program.

%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

iFastTest:
pushReturn[];
call[initIfuCache];
call[setIUsingInstrSet], t ← 3c;
noop;* for placement.
call[enableConditionalTask];
ifuTest ← r0;
call[resetIfu];
t ← (r0)-1;
clockCount ← t;* for future use.

t ← 101400C;* use instruction set 3
iftSetInstrSet:* this FF writes the instruction set
MOS ← t;* register when BMux.0=1.

call[iftGetContinueLoc];
t ← link;
klink ← t;

iftFlush:
t ← 200c;
rscr ← (Flush←t) + t;* flush our munch, compute byte addr.
t ← 100c;
call[longWait];* wait arbitrary time for flush to finish.
t ← lastTestCountC;
cnt ← t;* control how many times we’ll loop.
stkp+1;* increment stack so the opcodes won’t
iftSetPcF:* clobber our return link.
PcF ← rscr;
noop;* wait for it to take effect.

ifuJump[0];
error;* only get here if IfuJump didn’t work.

subroutine;;
iftGetContinueLoc:
coreturn;

iftGetCont:* KLink points here
t ← cnt;* get here from afterDispatch!
PD←t;
skpif[ALU=0];* quit if cnt=0
ifuJump[0];
afterIft:
top level;
call[disableConditionalTask];
pReturnP[];