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MODEL 1: ifuDefs.mcJune 17, 1981 3:30 PM%
TITLE[ifuDefs];
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
June 17, 1981 3:30 PM
Add opSign3 for miscEffects test.
May 28, 1981 2:54 PM
Change Bmux to BmuxRM to eliminate midas unhappiness.
February 1, 1980 5:48 PM
Add patterns 5 &6 for the pattern generator constants.
October 10, 1979 3:32 PM
Add lastEventB
October 9, 1979 10:42 AM
Add lastEventA
October 8, 1979 7:14 PM
Add ctrFlag.
September 27, 1979 5:37 PM
Add ctrLo, ctrHi, beginHi, beginLo
July 2, 1979 11:53 PM
define exceptions.*, RM locations for exception (ifu exception) handling.
June 24, 1979 5:41 PM
Add definition for ifu.typeMask.
June 20, 1979 8:14 AM
Add new RM definitions (in defaultRbase) for ifu random address/data test
June 19, 1979 8:00 AM
Add new 16 bit pattern constant.
June 18, 1979 9:35 AM
Add constants to define"base" dispatch locations.
June 17, 1979 4:24 PM
Move old "opIfad10" to "opIfad22" because of FGParity3 conflict
June 15, 1979 4:21 PM
Add mos.ifuCmmd
June 7, 1979 5:34 PM
Set defaultFlagsP to flags.conditionalP.
June 5, 1979 12:41 PM
Update ifLength macro to use ILlength, ILMask, ILsize symbols.
June 5, 1979 11:29 AM
Add rbsel and membk34 definitions for ifuchaos.
June 1, 1979 6:32 PM
More IfuChaos glitches.
May 30, 1979 5:48 PM
Glitches to accommodate ifuChaos.
May 30, 1979 11:00 AM
Add MemoryOK for initMem, add new pattern limit for pat16.
May 23, 1979 10:42 AM
Add rm definitions for ifu chaos.
May 1, 1979 6:58 PM
Fix ifu.instrSet* for difference between ’geting’ and ’seting’.
May 1, 1979 4:58 PM
Add ifu.InstrSetSize, ifu.InstrSetShift, ifu.InstrSetMask.
April 26, 1979 8:54 AM
Add iUsingInstrSet, pat8X.
April 25, 1979 12:53 PM
Add fastexit, fastfetch, faststore definitions.
April 24, 1979 3:47 PM
Remove dispatchOffset=r01, change iAddrX to r01.
April 23, 1979 9:02 AM
Move opcode definitions (byte values) from ifu3 to here.
April 19, 1979 11:01 AM
Increment lastTestCountC, create composeIfuWd macro.
April 5, 1979 12:05 AM
Add rm & constants to control test execution.
March 2, 1979 9:12 AM
Add constants for exception conditions.
February 15, 1979 9:00 AM
Change ifum definition macros to save IM space.
January 26, 1979 5:26 PM
Make ifum macros call subroutines rather than do all the work in-line.
January 22, 1979 8:27 PM
Construct IfAdHi, ifAdLow to cope with ifadm values that aren’t legal ff constants.
January 22, 1979 9:33 AM
Make b0 the default trigger value
January 17, 1979 2:50 PM
pat16End2C, instruction set parameter for endIfuWd
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* October 10, 1979 3:34 PM
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
IFU RegisterDeclarations
Ifu Loop control constants
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
RMRegion[ifuSubrsRM];
rv[iLink0,0];
rv[iLink1, 0];
rv[iSubrScr, 0];
rv[triggerCount, 0];
rv[triggerValue, b15];
rv[triggerZero, 0];
rv[clockCount, 0];
rv[currentCDbyte,0];
rv[iTestX, 0];* current test index
rv[iTestCountX, 0];* current iteration count for current test
rv[iCurrentTestLoc, 0];
rv[iUsingInstrSet, 0];
rv[pat8X, 0];
rv[ifuChaosX, 0];
rv[memoryOK, 0];
RMRegion[ifuChaosRM];
rv[ifuPc, 0];
rv[ifuAlpha, 0];
rv[ifuBeta, 0];
rv[ifuOpcode, 0];
rv[ifuInstrLH, 0];
rv[ifuInstrRH, 0];
rv[ifuSequence, 0];
* The exception (Kfault, FGPe, Resched, RamPE) handling code uses these locations.
rv[exceptionsMask, 0];
rv[exceptionBit, 0];
rv[exceptionPointers, 0];
* Counter values
rv[ctrBeginLo, 0];
rv[ctrBeginHi, 0];
rv[ctrElapsedHi, 0];
rv[ctrElapsedLo, 0];
rv[lastEventA, 0];
rv[lastEventB, 0];
knowRbase[defaultRegion];
rm[expectedDispatch, IP[r10]];
rm[pat16, IP[rhigh1]];rm[bmuxRM, IP[rhigh1]]; rm[iAddr1, IP[rhigh1]];
rm[pat16X, IP[rm1]];rm[FGbits, IP[rm1]];rm[iAddr2, IP[rm1]];
rm[IAddrX, IP[r01]];rm[value1left, IP[r01]];
rm[value1right, IP[rscr3]];rm[ctrLo, IP[rscr3]];
rm[value2left, IP[rscr4]];rm[ctrHi, IP[rscr4]];
rm[value2right, IP[stackPAddr]];rm[ctrFlag, IP[stackPAddr]];
br[br0,0];
mc[IfuEndAddrC, 2000];* last ifu address + 1
mc[pat16End1C, 20];* IN [0..20)
mc[pat16End2C, 40];* IN [0..40)
mc[pat16End3C, 60];* IN [0..60)
mc[pat16End4C, 200];* IN [0..100)
mc[pat16End5C, 201];* IN [0..101)
mc[pat16End6C, 202];* IN [0..102)
mc[pat16EndAllC, 202];* IN [0..102)
mc[lastTestC, 4];* IN [0..4)
mc[lastTestCountC, 1000];* IN [0..1000)
mc[ifuChaosEndC, 10000];* IN [0..10000)
sp[defaultFlagsP, flags.conditionalP];* conditional task and hold sim -- used by postamble.
mc[test0MemByteLocC, 0];
mc[test1MemByteLocC, 60];
mc[test2MemByteLocC, 120];
mc[test3MemByteLocC, 200];
mc[ifuLHmaskC, 3777];* IFU mem left half on low 11 bits of Bmux
* Bit definitions for each exception: The exception handling code assumes "not ready" is always ok.
mc[exceptions.kfault3, b0];mc[exceptions.FGPe3, b1];
mc[exceptions.resched3, b2];mc[exceptions.RamPe3, b3];
mc[exceptions.kfault2, b4];mc[exceptions.FGPe2, b5];
mc[exceptions.resched2, b6];mc[exceptions.RamPe2, b7];
mc[exceptions.kfault1, b8];mc[exceptions.FGPe1, b9];
mc[exceptions.resched1, b10];mc[exceptions.RamPe1, b11];
mc[exceptions.kfault0, b12];mc[exceptions.FGPe0, b13];
mc[exceptions.resched0, b14];mc[exceptions.RamPe0, b15];
* June 17, 1979 4:25 PM
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
IFU TEST REGISTER Definitions
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
mc[test.parity, b8];
mc[test.fault, b9];
mc[test.memAck, b10];
mc[test.makeFD, b11];
mc[test.myfh, b12];
mc[test.mysh, b13];
mc[test.en, b14];
mc[test.myfh’, 0];* zero turns on fh, 1 bit turns it off
mc[test.mysh’, 0];* zero turns on sh, 1 bit turns it off
mc[test.FH, OR[test.en!,test.myfh’!, test.mysh!] ];* enable, fh’ (disable sh)
mc[test.SH, OR[test.en!, test.mysh’!, test.myfh!] ];* enable, sh’ (disable fh)
mc[test.FHSH, OR[test.en!, test.mysh’!, test.myfh’!] ];* enable, fh’, sh’
mc[test.FhAck, OR[test.Fh!, test.memAck!] ];* enable, fh, memAck
mc[test.FhAckFd, OR[test.FhAck!, test.MakeFd!] ];* enable, fh, memAck, MakeFd
mc[test.FhFd, OR[test.Fh!, test.MakeFd!] ];* enable, fh, MakeFd
mc[test.ShAck, OR[test.Sh!, test.memAck!] ];* enable, sh, memAck
mc[test.ShAckFd, OR[test.ShAck!, test.MakeFD!] ];* enable, sh, memAck, MakeFd
mc[test.ShFd, OR[test.Sh!, test.MakeFd!] ];* enable, sh, MakeFd
* June 18, 1979 9:40 AM
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
IFU Opcode and Entry Point constants
The opATxx constants are the absolute IM address for the opcode whose IFADM field in the IFU ram has the value xx. Eg., if an opcode has an Ifadm value = 14, then opAt14 is the absolute location of that opcode’s entry point in IM.
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* These are entry point declarations
mc[opAt1, 177777];* IFADM=1
mc[opAt13, 54];* IFADM=13
mc[opAt14, 60];* IFADM=14
mc[opAt15, 64];* IFADM = 15
mc[opAt17, 74];* IFADM = 17
mc[opAt63, 314];* IFADM = 63
mc[opAt70, 340];* IFADM = 70
mc[opAt22, 110];* IFADM = 22
* entry point values for instruction set 3
mc[is3KfaultLocC, 0];
mc[is3FGParityLocC, 4];
mc[is3reschedLocC, 14];
mc[is3notReadyLocC, 34];
mc[is3ramPElocC, 74];
* Base entry point values (ie., the "instruction set bits" have been removed)
mc[KfaultBaseLocC, 0];
mc[FGParityBaseLocC, 4];
mc[ReschedBaseLocC, 14];
mc[notReadBaseLocC, 34];
mc[ramPeBaseLocC, 74];
mc[dispatchLocBaseMask, 77];* base loc = (dispatchAddr) and (dispatchLocBaseMask)
* These are opcode declarations
mc[opPause, 0];
mc[jump0, 21];* jump .
mc[jumpM1, 22];* jump .-1
mc[jump1, 23];* jump .+1
mc[opNoop, 24];* no jump
mc[opNoopL2, 25];* no jump length 2
mc[opNoopL3, 26];* no jump, length 3
mc[jumpL2, 27];* jump .+1, length 2
mc[jumpML2, 30];* jump .-1, length 2
mc[fast1, 31];* one byte, fast
mc[fastJfail, 32];* 2 byte failing jump (resets pcF)
mc[fastJ, 33];* succeed jump (1 or 2 bytes)
mc[fastMJ, 34];* succeed jump to .-
mc[fastHalt,35];* pause instr that invokes "error"
mc[fastExit, 36];* branch to afterDispatch IF CNT=0&-1
mc[fastFetch, 37];* force stack <0, FETCH ← STACK
mc[fastStore, 40];* check that MD=stack, mem[stack]←stack, stack←stack+1
mc[opSign3, 41];* 3 byte, sign, no encoded constant
* June 24, 1979 5:41 PM
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
IFU field declarations
Defines fields mostly for IfuMemory.
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
mc[mos.ifuCmmd, b0];* the bit that causes MOS← to address Ifu rather than junk IO.
set[ifu.InstrSetSize, 2];
set[ifu.SetInstrSetShift, 10];
set[ifu.GetInstrSetShift, 13];
mc[ifu.InstrSetMask, 3];
set[ifu.paShift, 12];
set[ifu.paSize, 1];
set[ifu.AdShift,0];
set[ifu.AdHi2Shift, 10];
set[ifu.AdLow8Shift, 0];
mc[ifu.AdMask,1777];
set[ifu.signShift, 17];
set[ifu.signSize, 1];
set[ifu.pe0Shift, 16];
set[ifu.pe1Shift, 15];
set[ifu.pe2Shift, 14];
mc[ifu.peMask, b1,b2,b3];
set[ifu.ILShift, 12];
set[ifu.ILSize, 2];
mc[ifu.ILMask, 3];
set[ifu.rbSelSize, 1];
set[ifu.rbSelShift, 11];
set[ifu.memBK34Size, 1];
set[ifu.memBK34Shift, 10];
set[ifu.memBShift, 6];
set[ifu.memBLow2Shift, 6];
set[ifu.memBHi2Shift, 10];
mc[ifu.memBMask, 17];
mc[ifu.rbSelMask, b12];
set[ifu.typeShift, 4];
set[ifu.typeSize, 2];
mc[ifu.typeMask, 3];
set[ifu.pauseShift, 5];
set[ifu.pauseSize, 1];
mc[ifu.pauseMask, 1];
set[ifu.jumpShift, 4];
mc[ifu.jumpMask, 1];
set[ifu.jumpSize, 1];
set[ifu.nShift, 0];
mc[ifu.nMask, 17];
set[ifu.nSize, 4];
* June 17, 1979 4:25 PM
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
IFU Memory Construction Macros
These macros aid in the construction of Ifu memory values. Ie., they appear in the microcode where the Ifu memory is being initialized with opcodes. They work by constructing assembly-time values for each field in the Ifu memory. Then they construct a constant (done in composeIfuWd) that gets loaded into RM at run time. The macro endIfuWd understands the calling conventions for the subroutine putIfuWd.
%*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
m[newIfuWd, set[mypa,0] set[myad,0]set[mysign,0]set[mylength,0]set[mymemb,0]set[mypause,0]set[myjump,0]set[myn,0]];
m[ifPa, set[mypa, lshift[#1,ifu.paShift]]];
m[ifAd, set[myad, and[not[#1],ifu.adMask!]]];
m[ifAdHi, set[myad, or[myad, and[and[177400,not[#1]],ifu.adMask!]]]];
m[ifAdLow, set[myad, or[myad, and[and[377,not[#1]],ifu.adMask!]]]];
m[ifSign, set[mysign, lshift[#1,ifu.signShift]]];
m[ifLength, set[mylength, lshift[and[not[#1],ifu.ILMask!],ifu.ILShift]]];
m[ifMemB, set[mymemb, lshift[and[xor[ifu.rbSelMask!, #1],ifu.memBMask!],ifu.memBShift]]];
m[ifPause, set[myPause, lshift[and[not[#1],ifu.pauseMask!],ifu.pauseShift]]];
m[ifJump, set[myJump, lshift[and[not[#1],ifu.jumpMask!],ifu.jumpShift]]];
m[ifN, set[myN, and[#1, ifu.nMask!]]];
m[composeIfuWd,
ilc[(rscr ← and[or[mypa,myad],177400]C)]
ilc[(rscr ← (rscr) or(and[or[mypa,myad],377]C))]
ilc[(rscr2 ← and[177400, or[mysign,mylength,mymemb,mypause,myjump,myn]]C)]
ilc[(rscr2 ← (rscr2) or (and[377, or[mysign,mylength,mymemb,mypause,myjump,myn]]C))]
]
m[endIfuWd,
composeIfuWd[]
ilc[(t←and[#2,377]c)]
ilc[(t←tor (and[lshift[#1,10],1400]C))]
ilc[(call[putIfuWd])]
];
* January 2, 1979 1:46 PM
* These macros support the use of the test register
m[iTick,
ilc[(FGbits ← (#1))]
ife[#0,2,(ilc[(FGBits←(FGbits)OR(lshift[#2, 10]C))]),]
ilc[(call[itTick])]
];
m[iNewPc,
ilc[(FGbits ← (#1))]
ife[#0,2, ilc[(FGBits ← (FGbits) OR (lshift[#2, 10]C) )],]
ilc[(call[itNewPc])]
];
m[iReset,
ilc[(FGbits ← (#1))]
ife[#0,2, ilc[(FGBits ← (FGbits) OR (lshift[#2, 10]C) )],]
ilc[(call[itReset])]
];
m[iJump,
ilc[(FGbits ← (#1))]
ife[#0,2, ilc[(FGBits ← (FGbits) OR (lshift[#2, 10]C) )],]
ilc[(call[itJump])]
];
m[iJumpData,
ilc[(FGbits ← (#1))]
ife[#0,2, ilc[(FGBits ← (FGbits) OR (lshift[#2, 10]C) )],]
ilc[(call[itJumpData])]
];
m[iData,
ilc[(FGbits ← (#1))]
ife[#0,2, ilc[(FGBits ← (FGbits) OR (lshift[#2, 10]C) )],]
ilc[(call[itData])]
];
* Initialize Ifu memory: initIfuM[location, leftHalf, rightHalf]
m[initIfuM,
ilc[(t ← #1c)]
ilc[(rscr←and[#2,177400]c)]
ilc[(rscr←(rscr)OR(and[#2,377]c))]
ilc[(call[putIfuLH])]
ilc[(t ← #1c)]
ilc[(rscr←and[#3,177400]c)]
ilc[(rscr←(rscr)OR(and[#3,377]c))]
ilc[(call[putIfuRH])]
];