Page Numbers: Yes X: 527 Y: -.5" First Page: 19
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Dorado Midas ManualEdward R. Fiala24 June 1983
10. Registers and Memories Known to Midas
Table 4: Memories
MemoryWidthLengthNotesComments
(octal)(octal)
IMBD44100004,5,6Control store (via mufflers, manifold ops.--for testing only)
IMX44100006,7Control store (absolute).
IM10010000Control store (virtual).
TPC20 201,2,6,7Shows CIA for current task.
TLINK20 201,2,6,7Shows Link for selected task.
OLINK20 201,2,3,9Shows address of last call (if any).
ALUFM10 206,70 and 16 smashed and restored by Midas.
RM20 4006,7
STK20 4006,7
STKX20 77= STK[STKP-address]
T20 201,6,7Waystation for A or Mar registers.
RBASE 4 201,6,7Used in read-write of RM.
TIOA10 201,6,7
MEMBASE 5 201,6,7
MD20 201,9
PIPE40 208,9Shows Pipe0 to Pipe5 (all signals high true)
BR30 406,7,11
BRX30 411Shows 4 BR words pointed at by MemBX
ROW-- 10011Shows 4 cols and Victim/NextV of a cache row
CACHEA23 4006,7,11Length is 2000 with 16k cache
CACHED20100006,7,11Length is 40000 with 16k cache
MAP20 2166,11Length is 216 or 218 with larger map ic’s
VM20 2286,11
IFUM40 20006,7,10
DMUX20 2004,9
DHIST54 403,4Discussed in the "DMux" section.
VH40 403,4,9Discussed in the "DMux" section.
$ABSOLUTE10 216Includes all state of microcomputer.
$ABS20 215$ABSOLUTE shown in 20 bit units
MSTAT40 249Low words of $ABSOLUTE shown symbolically
LDR44 2003Holds microinstructions used by Midas.
MDATAund. 103BITS-CHECKED etc. for testing.
MADDR40 143LOOP-COUNT etc. for testing.
TASKN 0 203Symbolic task definitions
DEVICE 0 4003Symbolic device address definitions
1.Task-specific
2.Virtual/absolute stuff applies
3.Fake memory--artifact of stuff in Midas
4.Readout via DMux, so value shown is correct in passive mode.
5.Resets the control section, so "Continue" from b.p. illegal.
6.Appears in Test menu.
7.Appears in TestAll menu.
8.SRN addressed.
9.Read-only to Midas.
10.Resets the IFU, so "Continue" from b.p. illegal.
11.Smashes the fault task pipe entry to access the item, so "Continue" from task 17 b.p. illegal.
Table 5: Registers
RegisterWidthNotesComments
(octal)
CPREG202,3Alto-baseboard interface register, freely smashed by Midas except in passive mode.
MIR442,3,6Microinstruction register, used ubiquitously by Midas.
IMOUT441,6Direct IM outputs
TASK 45Discussed in the "Task-Specific Register" section.
Q202,3Waystation for write of registers on external BMux.
CNT202,3
SHC202,3Special tests for RF←, WF←, and FF-controlled shifts.
MEMBX 22,3
STKP102,3
PROCSRN 42,3,6Must be 0 on a "Go" to operate memory system normally.
MCR202,3,6Several bits are not testable; smashed and restored for memory stuff.
CONFIG201
TESTSYN107Must be 200 (error correction on) or 0 (error correction off) to operate storage normally
PCX201,2,3
INSSET 52,3Shows the ←Id count and instruction set (only the instruction set is writeable)
UPTIME601Time since boot-button pushed from microcomputer
TGLITCH601Time of worst power glitch seen by microcomputer
STROBE205,7Discussed in the "Passive Mode" section.
D1OUT205,7Discussed in the "Passive Mode" section.
EVCNTA201EventCntA register
EVCNTB202,3EventCntB register
ESTAT202,6Read-write error halt enables, read error conditions
AATOVA205Translate absolute address to virtual
1.Read-only to Midas.
2.Appears in Test menu.
3.Appears in TestAll menu.
4.Virtual/absolute stuff applies
5.Fake register--artifact of stuff in Midas
6.Readout via DMux, so value shown is correct in passive mode.
7.Write-only
Most registers and memories listed above correspond to ones discussed in the "Dorado Hardware Manual". Others are discussed in the sections which follow.
MDATA and MADDR memories contain words used to report or control the activity of the "Test" and "TestAll" actions discussed later. MADDR also contains DWATCH (used to control the DMux address for scoping), MIR-PES (error-reporting), and COM-ERRS (error-reporting), which will be discussed later.
TASKN and DEVICE are fake memories used to pass symbolic information from the assembler to Midas in the .mb file, as discussed in the "Dorado Microassembler" document. Their only purpose is to provide symbolic equivalents to task and device numbers for ease of debugging.
For approximately all registers and memories that contain 16-bit quantities, Midas will evaluate input of the form "m,,n", storing the value of "m" into bits 0:7 of the word and the value of "n" into bits 8:15.
On Dorado, the items that accept "m,,n" are RM, Q, CNT, SHC, EVCNTB, T, STK, STKX, CACHED, VM, DMUX, and $ABS.
11. The IM Memory and Virtual Addresses
Because the placement transformations performed by MicroD make it difficult to correlate microstore locations with positions in microprogram source files, the Dorado and Dolphin Midas implementations use a map to transform virtual addresses produced by Micro into absolute microstore locations produced by MicroD.
Two memories, IMX and IM, each show the microstore. IMX is absolutely addressed; IM, virtually addressed. When you fire up Midas, IM is "empty"; when you load a microprogram, IM is filled with consecutive instructions from your source file, irrespective of where MicroD decides to place these; the value displayed for an IM address includes both the absolute address assigned to it, the microinstruction, and some other information discussed in the next section.
In other words, if your microprogram is 10 words long, the meaningful part of IM is only 10 words long. In this case, if you examine IM addresses greater than 7, the printout will show an absolute address of 7777 and zeroes for the rest of the value.
Midas will not allow you to modify the mapping between virtual and absolute addresses interactively--you can only do this by loading a microprogram.
To facilitate dealing with virtual/absolute correspondences, Midas has a mode switch that controls the way in which registers and memories that normally contain microstore addresses are handled. When you fire up Midas, the display is in absolute mode and the "Abs" action appears in the command menu; when you load a microprogram, the display switches to virtual mode and the "Virt" action appears in the command menu. Test actions will switch to absolute mode. The current mode always appears in the command menu.
In virtual mode, the display shows the virtual equivalent for the value in any register that normally contains a microstore address. When the value is outside the virtual memory, it prints as 7777. To find the absolute value in this case, you have to switch to absolute mode.
On Dorado the registers affected by this are CIA, CIAINC, TNIA, BNPC, TPC, TLINK, and OLINK.
A fake register called AATOVA converts absolute addresses to virtual. For example, copying the value in some RM word into AATOVA will show the virtual equivalent; this is useful when return links are saved in RM words.
The general idea is that, if you suspect a hardware problem in the control section, you might work in absolute mode, but in all other situations when a program is loaded you will work in virtual mode, and the complications created by scrambled instruction placement will be concealed.
12. Registers and Memories that Contain Microinstructions
The MIR and IMOUT registers and the IMBD, IMX, IM, and LDR memories all contain microinstructions. A middle-button action over the value will print these symbolically on the comment lines.
The value for an IM address is shown as five fields on the display:
two PE bits (PE020 and PE2141);
Undef and Emu bits;
148-bit absolute address;
bits 0-218 of microinstruction (RSTK, ALUF, BSEL, LC, ASEL);
bits 228-418 of microinstruction (BLOCK, FF, JCN).
A "1" in PE020 indicates a parity error in bits 08-208 of the value; a "1" in the second bit means PE in 218-418. Both bits "1" normally indicates a breakpoint. Midas will store the data with bad parity, if you request it. Note that these are parity-bad bits; on a write, Midas will compute correct parity for each half of the microinstruction and xor that with the parity-bad bit; on a read, Midas will determine whether or not the location has correct parity and report accordingly.
The "Undef" bit is set when no absolute address is assigned to this virtual address--in this case the absolute address should print as 7777. The "Emu" bit tells the pretty-print routine to show the instruction as though it were being executed by the emulator (task 0).
IMX, IMBD, MIR, IMOUT, and LDR have a three-field printout in which the two PE bits are left-most followed by the left and right halves of the microinstruction.
IMX and IMBD each address the microstore absolutely and differ only in the way data is read and written. IMX is read and written by executing multi-cycle microinstructions that write the microstore from the BMux and read the data into Link. This requires that both ContA and ContB boards be present (plus ProcH and ProcL to compute parity). IMBD uses manifold operations to address and directly write the microstore and uses the muffler system to read out the microstore; this requires only ContB; however, the addressing method for IMBD makes continuation from a break impossible, so users should normally display IMX in preference to IMBD.
The IMOUT register contains the 448 DMux signals which are the direct outputs of the microstore, as addressed by the complicated stuff in the control section. At a breakpoint (t0) IMOUT shows the bits that will be loaded into MIR at t2, provided that the state of the branch condition does not change at t1.
The LDR memory is an array in Alto core that contains microinstructions used by Midas when operating the hardware; it should ordinarily be of no interest to users, although the "LDRtest" action allows use of instructions stored in this memory for low-level hardware debugging.
Note that a bit pattern in LDR identical to one in IMX, IM, or IMOUT in general is not the same instruction because the ALUFM memory may contain different contents when the LDR instruction is executed. The pretty-print procedures account for this difference and show different stuff for these two cases. However, if you copy an LDR instruction into IM or IMX, watch out! In debugging regular microcode (i.e., any microcode that doesn’t test ALUFM itself), this incompatibility is usually avoided because ALUFM 0 and 16 are assembled with the "B" and "NOT A" alu operations, which are identical to the operations used by Midas.
Also note that the microinstruction pretty-print procedure does not have available all of the information that the microassembler had when you assembled your program, so the printout is not always beautiful. The following are deficiencies you should be aware of:
From the hardware manual, you will remember that the interpretation of the BLOCK bit depends upon whether or not the task executing the instruction is the emulator, and memory references are interpreted differently for the fault and emulator tasks than for io tasks, so Midas will disassemble this stuff correctly only when it is able to deduce the task that executes the microinstruction. Midas does have available the Emu bit for instructions in IM, and if you pretty-print an IM address or an IMX or IMBD address that also appears in IM, Midas will be able to distinguish between emulator and non-emulator instructions; however, Midas cannot distinguish fault task microinstructions from other non-emulator instructions, so fault-task memory references will be pretty-printed erroneously. However, Midas very cleverly deduces the task for microinstructions in MIR and IMOUT in most cases, so the pretty-print will usually be correct for these.
Midas is not clever enough to figure out what will be in RBASE when an instruction is executed, so RM addresses from your program are not normally pretty-printed; Midas instead uses the generated names R0 to R17 for RM references.
There are many possible assembler macros that you might use to generate constants to control the shifter; for an instruction that does this, Midas will pick one of the forms, probably not the one you used in the source file.
Midas sometimes pretty-prints control clauses differently from the assembler. IFUJump’s and IM/TPC read-write clauses are the same; the decision to print Return or CoReturn, LocBr or LocCall, LongBr or LongCall, GBr or GCall is dependent upon Midas deducing the virtual location for the instruction being printed and finding .+1 in the virtual space at .+1 in the absolute space, so this might be wrong sometimes. Conditional branches are always printed like "LocBr[addr1,addr2,BC]".
Modifying IM words in octal is inconvenient, so you will normally want to use the symbolic method below for patching IM.
Writeable registers and memories that contain microinstructions (MIR, IM, IMX, IMBD, and LDR) evaluate a special form of input as follows: The first character on the input text line should be "(" to change the values of several fields in the instruction without clobbering other fields, or "[" to reconstruct the value beginning with a no-op microinstruction. This is followed by a number of clauses of the form "Field←integer" separated by blanks and/or commas. The legal field names are RSTK, ALUF, BSEL, LC, ASEL, BLOCK, FF, JCN, PE020, PE2141, and EMUL. EMUL, the emulator mode bit affecting pretty-printing of the microinstruction is only defined for IM.
In addition to "field←value" clauses, Midas interprets the standalone clause RETURN, and several other items with "[]" enclosing a following argument. GO[va] (local branch), LONGGO[va] (long branch), and GCALL[va] (global branch) evaluate the argument enclosed in brackets and treat this as a virtual address in virtual mode or an absolute address in absolute mode; then they store a branch of the selected type in the JCN field of the microinstruction; IFUJUMP[n] evaluates n which should result a number in the range 0 to 3, and stores an IFUJump instruction in JCN. When you modify a microstore word (IM, IMX, or IMBD memories), Midas will error-check that the target for GO is, in fact, on the same page; Midas will always error-check that the argument of a GCALL is at a global address. Arguments to GO, LONGGO, and GCALL will usually be simple integers in absolute mode but may be expressions such as FOO+3, where FOO is an IM address, in virtual mode.
13. Task-Specific Registers
Midas treats all task-specific registers (T, RBASE, TLINK, OLINK, TPC, TIOA, MEMBASE, and MD) as 20-word memories. In other words, "T 6" is the T-register for task 6.
In addition, a special kludge allows you to display the 21st word (i.e., "T 20", "RBASE 20", etc.) and have that be interpreted as the register for the currently selected task. The currently selected task is the value in TASK; the TASK register is an artifact of Midas that is initialized to CTASK (i.e., to the "current task") at breakpoints.
In other words, when a microprogram halts at a breakpoint or because of a mouse-abort, CTASK is read from the DMux--suppose that it contains 6. This value is copied into TASK. If "T 20", "TLINK 20", etc. appear on the display, these will show values for task 6. The idea is that you can change the display for all eight task-specific registers by storing a new value into TASK. The task selected by TASK is also the one started by "Go", "SS", etc. as discussed later.
The hardware’s LINK register, suppressed by Midas, is shown as the current task’s TLINK word. The OLINK memory shows the absolute value in TLINK less 1. When microstore addresses are displayed in absolute mode, this is useless. However, in virtual mode OLINK will usually show the location that last did a CALL. This is useful in diagnostics which do BRANCH[ERROR], where ERROR is at a global call location. After one of these branches, OLINK shows the location that made the error branch, while TLINK shows an unrelated location.
14. BR Addressing Kludges
BR 40 is another addressing kludge used to represent the "currently selected" base register, or BR MEMBASE[TASK] (i.e., the BR location pointed at by MEMBASE for the currently selected task).
The BRX memory is another addressing kludge that allows the 4 BR words pointed at by MemBX to be displayed.
15. STKX Kludge
In debugging emulators, it is frequently desirable to view the STK entries relative to STKP rather than relative to STK 0 (i.e., relative to the top-of-stack rather than the bottom-of-stack). To aid in this, Midas defines STKX as an alternate memory for STK. STKX[n] shows STK[STKP-n], where valid values for n are 0 to STKP-1; hence, the top stack entries are STKX 0, STKX 1, etc.
STKX does not allow you to view entries on the wrong side of the stack pointer, and the display will preface those names with "~", indicating unreadable, if they appear on the display.
16. Memory System Registers and Memories
The cache, map, and storage arrangement may vary from one Dorado to another but Midas can deduce the configuration by reading the mufflers and looking at the CONFIG register; Midas does this automatically when you attach to a new machine or when you execute the "Config" action. Midas adjusts to the configuration by varying the lengths of its ROW, CACHEA, CACHED, and MAP memories and adapting its algorithms for reading and writing these.
Midas always uses task 17 (the fault task) and srn 1 (the fault task srn) to access BR, ROW, CACHEA, CACHED, MAP, and VM. Consequently, pipe entry 1 is smashed and (for CACHED and VM) MD is smashed, which may prevent continuing from a breakpoint, as discussed later.
ROW shows the cache flags and address bits in each of the four columns of a cache row and the victim and next-victim for the row on five consecutive lines of a display column. The length of the ROW memory is adjusted to the number of rows in the cache. Displaying an address in ROW is normally the most convenient way to view the cache; you can prettyprint the cache flags and address bits for each column independently, and this also shows the 16 data words in the associated munch (if any).
CACHEA is a memory of length equal to 4 times the number of cache rows; it shows the cache flags and address bits for a single entry in the cache. In a 100-row cache, the entries for the four columns in row i are CACHEA i, CACHEA i+100, CACHEA i+200, and CACHEA i+300. CACHEA is intended primarily for the "Test" and "TestAll" actions; on the display, it will usually be more convenient to look at ROW.
CACHED is a memory containing all the data words in the cache; word m in the munch for row r and column c is at CACHED 208*nrows*c + 208*r + m. CACHED is intended primarily for "Test" and "TestAll".
Addresses in the MAP memory are displayed with the MapPE and PgFault bits in a 2-bit field followed by wp, dirty, and ref bits in a 3-bit field followed by the 16-bit ra field on the display. When a MAP address is written, ref is zeroed and map parity is always written correctly; dirtyb (the copy of dirty) and MapParity are not readable (they appear in CONFIG in other situations).
VM accesses the virtual memory using Fetch← and Store← with the current contents of the map and cache; map and data error faults are not detected or indicated in any way, and the "RunRefresh" and "EnRefreshPeriod" clock enables must be true for storage to work properly. Midas sets the length of VM to the largest limit imposed by the map and cache geometries. Although VM appears in the "Test" menu, the user must setup the cache and map reasonably and select a suitably small sub-range of addresses in LOW-ADDR, HIGH-ADDR, and ADDR-INC before attempting to test VM. Midas uses a user-settable base register called VMBASE, initially 0, to offset the address specified by the user. VMBASE is an address in the fake MADDR memory.
In looking at VM, it is sometimes desirable to determine the MAP and ROW entries through which a VM word is accessed; if you middle-button any VM address, these will be displayed on the comment lines.
Midas does not provide any direct method of accessing storage; the user has to setup CACHEA and MAP with appropriate values and then use VM to do this.
Note: The code for accessing CACHEA and CACHED is complicated and unlikely to work unless the memory system is functional; these can be tested with "Test" and "TestAll" but the more basic "ProcVA" test, which exercises VA paths in the memory system, may be more helpful in isolating problems.
17. Memories and Registers Associated With the DMux
At those times discussed later, the 40008 DMux signals (or mufflers) are read from the hardware and stored in the first 2008 words of a table. These are arranged so that hardware DMux address 0 corresponds to bit 0 of word 0 in Midas’ DMUX memory, hardware address 178 to bit 178 of word 0, .., up to hardware address 37778 in bit 178 of word 1778. Then the value on the BMux and the error status, which can also be read passively, are appended to the table. Finally, table data is rearranged, so that the DMUX memory looks as shown in the tables later.
Inside Midas associated with the DMUX memory are four separate tables, named as follows:
DMuxTabcurrent DMux readout
OldDMuxTabprevious DMux readout when running the simulator
DChecksignals checked by the simulator
DWrongerrors detected during simulation
The last three tables are only significant when the DMux simulator is used by the "SimGo" and "SimTest" actions, as discussed later. In other words, when one of these actions halts, OldDMuxTab holds the t0 DMux readout, DMuxTab the t2 readout, and DWrong the errors that were detected in DMuxTab. DCheck is initialized by Midas to values that are reasonable for the boards that are plugged in, and the "Config" action also initializes DCheck to reasonable values; the user may manually modify DCheck, as discussed below, in order to disable checking of signals that are incorrectly simulated (This won’t be particularly useful after the simulator is thoroughly debugged).
Normally, DMux addresses and registers derived directly from DMux readout (i.e., MIR, IMOUT, MCR, IMBD, DHIST, VH) show values taken from DMuxTab. However, the user may execute the "DMux" action with various button combinations to view the other three tables; the name printed for this action in the command menu will be "DMux", "DWrong", "DChk", or "OldDTab" according to which table is currently viewed. When the action is executed with the right (bottom) mouse button, OldDMuxTab values are viewed; both left and right buttons shows DCheck; middle button shows DWrong. The symbolic names of the first 11 errors in DWrong will also be printed on the comment lines when the middle button is released.
DMUX prettyprinting (middle button over value) of regular (DMuxTab or OldDMuxTab) values works differently from DWrong and DCheck pretty-printing. Regular printout of single-bit items shows symbolic names of "true" signals; "false" signals are not printed. In other words, low-true signals are printed when 0, high-true when 1. Multi-bit items (e.g., foo.0, foo.1, foo.2) are always printed (e.g., foo=3).
You should note that modified printout of DMUX also affects registers whose values are obtained by reading the DMux; this includes MIR, MCR, and IMOUT (but not IMBD). The DMUX memory itself and IMOUT are read-only except when DCheck is being shown. MIR and MCR are writeable when DMuxTab is viewed but read-only when OldDMuxTab or DWrong is viewed; writing modifies DCheck when DCheck is viewed.
The DHIST memory contains a DMUX bit address in bits 408 to 538 (displayed left-most by Midas) and a history of the last 408 values read from the DMux in bits 0 to 378 (displayed as the two right-hand fields by Midas). This memory may be useful in checkout of multi-state stuff in the memory and IFU sections of the machine when the DMux simulator is unable to detect problems. Each time the DMux is read the 408-bit data field of each word in DHIST is left-shifted 1 and the new value brought into the low bit.
The VH memory provides another view of DHIST. Word 0 in VHIST shows the 408 DHIST signals at t0, word 1 at t-1, word 2 at t-2, etc.
When it is done reading the mufflers or done with a manifold operation, Midas loads the DMux address register with the value contained in DWATCH, an address in the MADDR memory. This means that during a "Go" or when Midas is not reading the mufflers, a scope probe attached to the DMux data line on the backpanel will show the DMux signal selected by the low-order 11 bits of DWATCH. However, if DWATCH contains 0, Midas will be turning control of the muffler/manifold system over to the baseboard at regular intervals, and the microcomputer will smash the DMux address.
18. Interface Registers
CPREG is one of the central interface registers used by the Alto in loading information into Dorado. It can be tested, but should not otherwise be of interest except in passive mode. Midas freely smashes the value in this register.
MIR is also special. It is loaded directly from the Alto and read via the DMux; Midas faithfully restores MIR after executing instructions.
19.Config
Midas automatically determines the hardware configuration when it connects to a particular dorado by means of DMux signals that it can read from each board. The configuration consists of the following parameters:
which boards are plugged in--debugging is frequently carried out with some boards disconnected;
Map ic size;
storage ic size;
cache size (4K words or 16K words);
whether the 16th bit in a cache entry is used as a parity bit or an address bit;
number of storage modules.
Midas automatically adjusts its length parameters for VM, CACHEA, CACHED, ROW, MAP, etc., enables and disables various tests in the Test and TestAll actions, and modifies the behavior of SimTest and SimGo according to which boards are plugged in.
The automatic determination of the hardware configuration should not fail, but if it does, the Config action can be executed to manually set the configuration by means of actions in a subsidiary menu. Manually controlling the configuration may also be useful when testing with SimTest or SimGo.
20.SetClk
The baseboard microcomputer presently initializes the clock to a 30 nsec period (= 60 nsec instruction cycle) when the boot button is pushed. The current clock period can be determined by pretty-printing the value of the CLKRUN DMux word which normally appears on the Midas display.
The "SetClk" action allows the clock period of the mainframe to be specified from a subsidiary menu. You will probably be able to continue from a break after changing the clock speed, but Midas warns you that continuation is impossible.
21. Reset
The "Reset" action shows an elaborate subsidiary menu with many options. The options are: run enables for different stuff; parity-error enables for the different data paths that are parity-checked; and initialization of memories.
The general ideas that determined exactly how "Reset" is implemented are as follows: First, memories and registers should be reset only if they have to be for some reason. For example, memories that are parity-checked, such as T, RM, and STK, have to be reset to prevent parity errors when you start running a program; TIOA has to be reset in case some io device has variant behavior when TIOA contains its device number (building an io device that did this would be a poor idea); it is desirable to reset IMX and IFUM before loading a program, so that run-away branches and out-of-control programs will be trapped. However, other memories and registers such as RBASE, MEMBASE, Q, CNT, etc. need not be reset--your microprogram should contain code to initialize these, so Midas doesn’t have to.
Next, memories that require a long time to initialize, such as MAP (9 seconds now, 35 or 140 seconds with larger ic’s in the Map), should be optionally reset so that you won’t have to wait for their initialization unnecessarily.
Also, memories loaded by a microprogram (IM, IFUM, RM, ALUFM, and STK) should be optionally reset, if at all; if they are optional, you will be able to reset other parts of the machine without smashing your program. However, there does not seem to be any advantage in initializing ALUFM, so this memory is never initialized.
Each option is of an on-off form. The current state of the option is shown on the comment lines, while the other state appears in the command menu. The options as originally chosen are reasonable for a total reset, such as you would carry out at the onset of a "RunProg" command file; you may also want to turn on MAP initialization.
To carry out a reset, you bug the sequence of options you want, then bug the "Do-It" menu item.
When you bug "Do-It", initialization is carried out as follows (not exactly in this sequence since some initialization is done twice):
Run enables (RunRefresh and EnRefreshPeriod) are set as chosen;
Parity-error halt enables and MIRDebug are set as chosen; Midas remembers the halt enable settings so that they can be simulated for "SimGO" (discussed later) and remembers the setting of MIRDebug, so that it can warn against continue after breaks with MIRDebug true;
Manifold stuff used for testing IMBD is cleared;
Midas error counters MIR-PES and COMM-ERRS are cleared;
Hold and task simulators are cleared;
ALUFM 0 and ALUFM 16 are loaded with the "B" and "NOT A" alu controls needed by Midas;
The IFU is reset;
TestSyndrome is loaded for normal error-correction;
Several IOFetch←’es are done in task 2 to make sure that Asrn is .ge. 2 after power up;
Tasking is turned on;
Junk io, the fault task, and io devices are reset;
If MAP initialization is selected, each MAP address is loaded with Dirty and a pointer to the corresponding absolute page;
If MD initialization is selected, then CACHEA is loaded to map the first 4k (or 16k) of virtual memory, BR and CACHED are zeroed, and, for each task, the MD tag is reset, T and TIOA are zeroed, TLINK and TPC are loaded with 7777;
RM and STK are optionally zeroed;
If IM initialization is selected, then absolute mode is selected, IM is made empty, and every IMX address is loaded with "Branch[.], Breakpoint" except that 7776 is loaded with "Return, FreezeBC, Breakpoint" for the "Call" action;
If IFUM initialization is selected, then the Reschedule condition is turned off, and each IFUM address is loaded with the descriptor for a two-byte regular opcode with no operand, using MemBase 0 and RBase 1, starting at IMX 0.
MCR is loaded with NoRef and ProcSRN with 0;
The test control stuff BITS-CHECKED, LOW-ADDR, HIGH-ADDR, ADDR-INC are reinitialized;
After the reset is complete, Midas reads the DMux and checks the run-enable initialization, most of the control section initialization, and halt-enable initialization; if any failures are found, the errors are reported on the comment lines.
The "Go" action performs a subset of "Reset" prior to starting at a new address, as discussed later; parity-error halt enables can be modified without resetting anything else by writing an octal number into the ESTAT register.