Page Numbers: Yes X: 527 Y: -.5" First Page: 70
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Dorado Midas ManualEdward R. Fiala24 June 1983
42. Hardware Read/Write Methods
This section discusses the methods Midas uses to read and write each register and memory, so that failing data paths can be identified when Midas reports problems via "Test" or "TestAll". These sequences are included to help maintainers determine what registers or data paths might be malfunctioning when something is found to be non-working.
To understand how the sequences given below communicate information between Midas and the Dorado, you have to understand the lowest-level communication protocols which are discussed in "Dorado Debugging Interface" ([Indigo]<DoradoDocs>DoradoDebugging.press). These primitives are outlined here:
DoradoOutStoring into DoradoOut sends 13d bits of control information over the printer interface to the (connected) Dorado. This information is interpreted by the receiving hardware as a 3-bit address field, 9-bit data field, and 1-bit strobe.
StrobeA strobe operation consists of 3 DoradoOut’s identical except for the strobe bit, which is first off, then on, then off again. Strobe sequences are used to send commands to the Dorado.
Load ClockA register internal to the communication interface that can be loaded with one strobe operation.
Load ControlAnother register internal to the communication interface that can be loaded with one strobe operation.
Load MIRMIR can be loaded by four strobe operations, each loading 9 bits of the microinstruction. Midas computes and sends the parity also.
Load CPRegTwo strobe operations load the 16d-bit CPReg, the register from which Midas usually sends data to the Dorado.
Xct(mic)A microinstruction can be executed by loading it into MIR and single-stepping the Dorado. To get data from Midas to the Dorado, Midas first loads CPReg with data, then executes a microinstruction which does "Q ← Link" or "T ← Link", for example, while the UseCPReg bit in the Clock register is true. This kind of sequence is denoted by "Q ← CPReg(data)" below, which means that the data is routed from CPReg through the multiplexor on the ContA board to the Q or T register. The fact that the B data path is used is not explicitly stated in the microinstruction, but B is the only possible data path; this implicit use of data paths in the examples below is consistent with the conventions of the microprogramming language.
Also, a function called "B ← RWCPReg", solely for use by Midas and the baseboard microcomputer is used to do "Link ← B ← CPReg(data)". This function is needed when reading and writing some registers in the control section.
DoradoInReading from DoradoIn obtains 5 bits of data selected according to bits 0..4 in the last DoradoOut operation; it is not necessary to use a strobe operation for the purposes of DoradoIn. The fifth bit is always the current DMux bit; the first 4 bits can be any of the 4 B nibbles, any of 4 error nibbles, either of two MAReg nibbles or the MASync bit (for communication with the baseboard microcomputer).
Read BReading 16 bits of B is accomplished by a sequence of four DoradoOut/DoradoIn operations to obtain the 4 nibbles of B data. When a microinstruction is executed for the purpose of extracting data on the B, it is written like "B* ← Q"; "*" denotes that Midas captures the B data.
Read DMuxMidas has special microcode to extract all 2048d DMux signals using strobe operations. This is done in about (32+39)/2 * 2048 * .00018 msec = 13 msec. Assembly code uses about 15 msec more appending B and ESTAT to the readout, rearranging certain signals, and computing histories.
SelectTaskComplicated. See "Dorado Debugging Interface".
SingleStepComplicated. See "Dorado Debugging Interface".
RunComplicated. See "Dorado Debugging Interface".
StopComplicated. See "Dorado Debugging Interface".
LoadDMDExecute a "manifold" operation by loading the 11-bit DMux address with a control function and then executing it.
MCXctMCXct is used to communicate with the baseboard microcomputer. Midas first loads CPReg with a command and then interrupts the microcomputer with DoStrobe(Clock+BaseBAtten); a slowed strobing sequence is used because the microcomputer requires it. Then Midas waits for an acknowledge by doing DoradoIn’s until the microcomputer responds with MASync. MCXct can be used while the Dorado is running to extract voltage, current, temperature, and daytime information from the baseboard microcomputer. DoradoIn can be used to get two nibbles of information from the baseboard.
Each sequence below gives the microinstructions or other sequences executed by Midas to read and write each register and memory. These sequences do not include the shifting and masking and other transformations which occur within Midas to position data. Sequences bracketed with "[]" are used to restore registers incidentally smashed on the read or write. The restoration sequences ARE NOT executed when using "Test" or "TestAll"; they ARE executed when registers or memory words appearing in a name value menu are accessed.
D1OUTWrite only. This artificial register allows the user to execute the most primitive control function for the Dorado interactively.
STROBEWrite only by DoStrobe(D), which is equivalent to three D1OUT’s with the strobe bit first off, then on, then off again. This artificial register allows the user to send strobed commands interactively.
CPREGRead by B* ← CPReg;
[Restore MIR].
Write by Midas direct handle.
MIRRead from DMux.
Write by Midas direct handle.
IMOUTArtificial read-only register (part of DMux memory).
QRead by B* ← Q;
[Restore MIR].
Write by Q ← CPReg(new value); Noop;
[Restore MIR; read DMux].
CNTRead by
T ← Cnt;
B* ← T;
[T ← CPReg(SavedT); Noop; restore MIR].
Write by
Q ← CPReg(new value);
Cnt ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
SHCRead by
T ← ShC;
B* ← T;
[T ← CPReg(SavedT); Noop; restore MIR;].
Write by
Q ← CPReg(new value);
ShC ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
MEMBXRead by
T ← Pointers;
B* ← T;
[T ← CPReg(SavedT); Noop; restore MIR].
Write by
MemBX ← <new value>S;
[Restore MIR; read DMux].
STKPRead by
T ← TIOA&StkP;
B* ← T;
T ← Pointers;
B* ← T;
[T ← CPReg(SavedT); Noop; restore MIR]. Note that StkOvf and StkUnd are obtained from Pointers while the value in the register is obtained from TIOA&StkP.
Write by
Q ← CPReg(new value);
StkP ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux]. StkOvf and StkUnd are read-only.
TASKRead returns value saved at breakpoint.
Write with SelectTask;
[Restore MIR; read DMux].
PROCSRNRead by B* ← Config;
[Restore MIR].
Write by Q ← CPReg(new value); ProcSRN ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
MCRRead from DMux.
Write by
T ← CPReg(new value);
MCR ← T;
[T ← CPReg(SavedT); Noop; restore MIR; read DMux].
The MCR register is written only when DMuxTab is selected by the "DMux" action. Writing MCR is illegal when OldDMuxTab or DWrong is selected; and DCheck is written instead when DCheck is selected.
CONFIGRead only by
B* ← Config;
[Restore MIR].
PCXRead only by
B* ← PCX;
[Restore MIR].
INSSETRead by
B* ← IFUMLH’;
[Restore MIR].
Write by
Q ← CPReg(new value);
InsSetOrEvent ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
TESTSYNWrite only by
SelectTask(16B);
T ← CPReg(constant);
MCR ← T;
Q ← CPReg(new value);
Noop;
Store ← T, DBuf ← Q;
LoadTestSyndrome;
[T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); Noop; Q ← CPReg(SavedQ); SelectTask(SavedTask); restore MIR; read DMux].
UPTIMEArtificial read-only register (part of ABSOL memory).
TGLITCHArtificial read-only register (part of ABSOL memory).
EVCNTARead only by B* ← EventCntA’;
[Restore MIR].
EVCNTBRead by B* ← EventCntB’;
[Restore MIR].
Write by
Q ← CPReg(new value);
EventCntB ← Q;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
AATOVAArtificial register.
ESTATActually read by Midas direct handle but treated as part of the DMux memory. This is a register rather than simply another word in the DMux memory so that the error enables can be written.
Write error enables with LoadDMD; write MIRDebug with four LoadDMD’s.
ABSOLRead ABSOL by two MCXct’s followed by, if the Dorado isn’t running, DoStrobe(Clock+UseCPReg).
Write with MCXct(constant+new value) followed by, if the Dorado isn’t running, DoStrobe(Clock+UseCPReg);
TPCRead from a static if address .eq. SavedTask; otherwise,
RdTPC ← CPReg(address);
B* ← Link;
[If address .eq. SavedTask, then done; otherwise, B ← RWCPReg(SavedLink); Noop; restore MIR].
If address eq SavedTask then write static and done;
otherwise, write by
B ← RWCPReg(new value);
LdTPC ← CPReg(address);
Noop;
[B ← RWCPReg(SavedLink); Noop; restore MIR; read DMux].
TLINKRead by
SelectTask(address);
B* ← Link;
[SelectTask(SavedTask); Noop; restore MIR; read DMux]
Write by
SelectTask(address);
B ← RWCPReg(SavedLink);
[SelectTask(SavedTask); Noop; restore MIR; read DMux].
OLINKArtificial memory read and written like TLINK.
IMBDThe setup code common to both the read and the write of IMBD first zeroes BNPC, which is wire-OR’ed with the control store address loaded by manifold operations. This is accomplished by loading TPC for task 17B with 0 and then notifying that task; the notify causes the priority encoder to select task 17B, so BNPC becomes equal to 0.
Read by
SelectTask(0);
RdTPC ← CPReg(17B);
B* ← Link (save old TPC(17B) for restoration later);
B ← RWCPReg(0);
LdTPC ← CPReg(17B);
Noop;
LoadMIR(Notify[17B]); single-step with Freeze off;
B ← CPReg(-1);
three LoadDMD’s to setup the control store address;
LoadDMD(constant);
read DMux to get the IMOUT signals;
four LoadDMD’s to clear IMBD adress again;
[B ← RWCPReg(SavedTPC17B); LdTPC ← CPReg(17B); Noop; B ← RWCPReg(SavedLink); SelectTask(SavedTask); DoStrobe(Clock+UseCPReg+ClrReady); DoStrobe(Clock+UseCPReg); Noop; restore MIR].
Write by
SelectTask(0);
RdTPC ← CPReg(17B);
B ← Link (UseCPReg turned off) to save TPC(17B) for later;
B ← RWCPReg(0);
LdTPC← CPReg(17B);
Noop;
LoadMIR(Notify[17]); single-step with Freeze off;
B ← CPReg(-1);
three LoadDMD’s to setup the control store address;
four LoadDMD’s to load left-half of the instruction;
four LoadDMD’s to load right-half of the instruction;
four LoadDMD’s to clear the Control register;
three more LoadDMD’s to something else;
[B ← RWCPReg(SavedTPC17B); LdTPC ← CPReg(17B); Noop; B ← RWCPReg(SavedLink); SelectTask(SavedTask); DoStrobe(constant); DoStrobe(constant); restore MIR; read DMux;].
IMArtificial form of IMX memory.
IMXRead by
B ← RWCPReg(address);
B* ← ReadIM[0];
B ← RWCPReg(address);
B* ← ReadIM[1];
B ← RWCPReg(address);
B* ← ReadIM[2];
B ← RWCPReg(address);
B* ← ReadIM[3];
[B ← RWCPReg(SavedLink); Noop; restore MIR].
Write by
B ← RWCPReg(address);
IMLHR0POK ← CPReg(new value);
B ← RWCPReg(address);
IMRHBPOK ← CPReg(new value);
[B ← RWCPReg(SavedLink); Noop; Noop; restore MIR; read DMux].
ALUFMRead from static if address is 0 or 16B; otherwise, read by
T ← ALUFM, ALUF[address];
B* ← T;
[T ← CPReg(SavedT); Noop; restore MIR].
Write static if address is 0 or 16B; otherwise, write by
Q ← CPReg(new value);
ALUFMRW ← Q, ALUF[address];
Noop;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
TRead by
SelectTask(address);
B* ← T;
[SelectTask(SavedTask); Noop; restore MIR].
Write by
SelectTask(address);
T ← CPReg(new value);
Noop;
[Restore MIR; read DMux].
RBASERead by
SelectTask(address);
T ← Pointers;
B* ← T;
[T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
SelectTask(address);
T ← CPReg(new value);
Noop;
[SelectTask(SavedTask); restore MIR; read DMux].
TIOARead by
SelectTask(Address);
T ← TIOA&StkP;
B* ← T;
[T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
SelectTask(Address);
Q ← CPReg(new value);
TIOA ← Q;
Noop;
[Q ← CPReg(SavedQ); Noop; SelectTask(SavedTask); restore MIR; read DMux].
MEMBASERead by
SelectTask(address);
T ← Pointers;
B* ← T;
[T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
MemBase ← <address>S;
Noop;
[SelectTask(SavedTask); restore MIR; read DMux].
RMRead by
RBase ← <hiaddress>S;
B ← RB, RStk[lowaddress];
[RBase ← <SavedRBase>S; Noop; restore MIR].
Write by
RBase ← <hiaddress>S;
RB ← CPReg(new value), RStk[lowaddress];
Noop;
[RBase ← <SavedRBase>S; restore MIR; read DMux].
STK and STKXRead by
Q ← CPReg(address);
StkP ← Q;
SelectTask(0);
B ← RB, RStk[0], Blk[1];
[SelectTask(SavedTask); Q ← CPReg(SavedStkP); StkP ← Q; Q ← CPReg(SavedQ); Noop; restore MIR].
Write by
Q ← CPReg(address);
StkP ← Q;
SelectTask(0);
RB ← CPReg(new value), RStk[0], Blk[1];
Noop;
[Q ← CPReg(SavedStkP); StkP ← Q; Q ← CPReg(SavedQ); Noop; SelectTask(SavedTask); restore MIR; read DMux].
PIPERead only by
T ← CPReg(address);
ProcSRN ← T;
B* ← VAhi;*First screen line
B* ← VAlo;
B* ← Pipe2’;*Second screen line
B ← Map’;
B ← Errors’;*Third screen line
B ← Pipe5;
[T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedT); Noop; restore MIR].
BRRead by
MemBase ← <address>S;
T ← CPReg(constant);
MCR ← T;
T ← CPReg(0);
DummyRef ← T;
Noop;
B* ← VAhi;
B* ← VAlo;
[MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
MemBase ← <address>S;
T ← CPReg(constant);
MCR ← T;
T ← CPReg(highdata);
BRhi ← T;
T ← CPReg(lowdata);
BRlo ← T;
Noop;
[MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); restore MIR; read DMux].
For both the read and the write, the cleanup is done by a subroutine shared with other memories. "T ← CPReg(SavedSRN); ProcSRN ← T;" and the "SelectTask(SavedTask)" are extraneous to the requirements of BR.
BRXSame as BR with "MemBaseX ← <address>S" replacing "MemBase ← <address>S".
CACHEARead by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint--this stuff isn’t done automatically at breakpoints because it prevents continuing.);
T ← CPReg(constant+lowaddress);
MCR ← T;
T ← CPReg(hiaddress);
Noop;
TurnOffRefresh with two LoadDMD’s;
DummyRef ← T;
Noop;
B* ← Pipe5;
restore Refresh;
B* ← VAhi;
B* ← VAlo;
[T ← CPReg(DisHold+DisCF+NoWake); MCR ← T; T ← CPReg(SaveBR36!0); BRhi ← T; T ← CPReg(SaveBR36!1); Xct(BRLOFT); MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(OldTask); restore MIR; read DMux].
Write by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hi(address - new flag value));
BRhi ← T;
T ← CPReg(low(address - new flag value));
BRlo ← T;
T ← CPReg(new flag value);
Noop;
Fetch ← T;
Noop;
Fetch ← T;
Noop;
T ← CPReg(constant+lowaddress);
MCR ← T;
T ← CPReg(new flag value);
Noop;
TurnOffRefresh;
DummyRef ← T;
CFlags ← T;
restore Refresh;
Noop;
[T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMemBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; (T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); restore MIR; read DMux].
CACHEDRead by
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
Fetch ← T;
T ← Md;
B* ← T;
[T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
Q ← CPReg(new value);
Store ← T,
DBuf ← Q;
Noop;
[Q ← CPReg(SavedQ); Noop; T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); restore MIR; read DMux].
MAPRead by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
RBase ← 0S;
RB ← CPReg(0), RStk[0];
RMap ← RB, RStk[0];
B* ← Map’;
B* ← Errors’;
B* ← Config’;
[RB ← CPReg(SavedR0), RStk[0]; RBase ← <SavedRBase>S; T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; XctL16T(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
Q ← CPReg(hi new value);
TIOA ← Q;
Q ← CPReg(low new value);
Map ← T, MapBuf ← Q;
Noop;
Q ← CPReg(SavedTIOA);
TIOA ← Q;
Q ← CPReg(SavedQ);
Noop;
[T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); restore MIR; read DMux].
VMRead by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
Fetch ← T;
T ← Md;
B* ← T;
[T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR].
Write by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(Other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(hiaddress);
BRhi ← T;
T ← CPReg(lowaddress);
BRlo ← T;
T ← CPReg(0);
Noop;
Q ← CPReg(new value);
Store ← T, DBuf ← Q;
Noop;
[Q ← CPReg(SavedQ); Noop; T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); restore MIR; read DMux].
IFUMRead by
IFUReset;
Q ← CPReg(F(address));
InsSetOrEvent ← Q;
Q ← CPReg(F(address));
BrkIns ← Q;
Noop;
B* ← IFUMRH’;
B* ← IFUMLH’;
[Q ← CPReg(SavedQ); Noop; restore MIR].
Write by
IFUReset;
Q ← CPReg(hiaddress);
InsSetOrEvent ← Q;
Q ← CPReg(lowaddress);
BrkIns ← Q;
Noop;
Q ← CPReg(new value);
IFUMLH ← Q;
B ← Q;
Q ← CPReg(new value);
IFUMRH ← Q;
B ← Q;
Noop;
[Q ← CPReg(SavedQ); Noop; restore MIR; read DMux].
LDRArtificial memory.
MDATAArtificial memory.
MADDRArtificial memory.
DMUXRead only by the special Alto microcode and software discussed at the beginning of this section, when "current" DMux readout is selected. Old, wrong, or checked tables may be selected for this memory by the "DMux" command action; when DChecked is selected, writes are legal.
DHISTArtificial memory.
VHArtificial memory.
MDRead only by
SelectTask(address);
T ← Md;
B* ← T;
[T ← CPReg(SavedT); SelectTask(SavedTask)].
TASKNArtificial memory which cannot be read or written (used for displaying some values symbolically).
DEVICEArtificial memory which cannot be read or written (used for displaying some values symbolically).
MSTATArtificial form of ABSOL memory.
ABSArtificial form of ABSOL memory.
ROWRead lines 0 to 3 like CACHEA; line 4 (Victim/Next Victim) by
SelectTask(17B);
T ← CPReg(1);
ProcSRN ← T;
MemBase ← 36S;
(other stuff to save BR 36 if not saved yet since breakpoint);
T ← CPReg(constant);
MCR ← T;
T ← CPReg(F(address));
DummyRef ← T;
Noop;
B* ← Pipe5;
[T ← CPReg(constant); MCR ← T; T ← CPReg(SavedBR36!0); BRhi ← T; T ← CPReg(SavedBR36!1); BRlo ← T; MemBase ← <SavedMBase>S; T ← CPReg(SavedSRN); ProcSRN ← T; T ← CPReg(SavedMCR); MCR ← T; T ← CPReg(SavedT); SelectTask(SavedTask); Noop; restore MIR]
Write rows 0 to 3 like CACHEA; row 4 is read-only.