[_CD8_]<doradosource>DoradoMidasManual.dm!10>d1dmux.bravo

0StopCJNK00 0StopAlways
1preStartCyclea 1preStartCycleaAlways
2dStartCycle 2dStartCycleAlways
3Phase0 3Phase0Always
4Phase4 4Phase4Always
5RWTPCorRWIM 5RWTPCorRWIMAlways
6BigBDispatch 6BigBDispatchTn ge 2 & switch’
7Dispatch 7DispatchTn ge 2 & switch’
10WIM’ 10WIM’Always
11RIM’ 11RIM’Always
12WTPC’ 12WTPC’Always
13RTPC’ 13RTPC’Always
14FF=Notify’14:170
15FF=MulStep
16FF=BDispatch
17FF=BigBDispatch

20:37CIAInc[0:15]CIAINC120:37CIAInc[0:15]Tn ge 1

40:57CIA[0:15]CIA240:57CIA[0:15]Tn ge 2

60* CABlockBNT360:730
61:70* bFF[0:7]74:77Bnt[0:3]Tn ge 2
71:74* JCN[0:3]
75:77* bJCN[4:6]

100:117* MIR[1:16]PENC4100:1130
114:117bPEnc[0:3]Always

120:121--TNIA5120:121--
122:137TNIA[2:15]122:137TNIA[2:15]Unless return or IFUJump

140:141--BNPC6140:141--
142:157BNPC[2:15]142:157BNPC[2:15]Never

160CBTempSenseCTASK7160:1730
161bSWd’174:177CTASK[0:3]Tn ge 2
162* IMLH
163* bRSTK.0
164* bdRSTK.0
165* bdIMLH
166* bdIMRH
167* bdJCN.7
170:173CTASK[0:3]
174:177CTD[0:3]

* Midas extracts the 44 MIR and 44 bdIM signals and arranges these as registers (MIR and IMOUT). This information resides in DMuxTab in the peculiar MIR-loading format discussed in the "Dorado Debugging Interface" document, but is viewed by users in the standard IM format.

200:217* bdxx for IM[1:16]NEXT10200:2030
214:217Next[0:3]Always

220:237* bdxx for IM[17:32]CTD11220:2330
234:237CTD[0:3]Tn ge 1

240:243CS[0:3]’BDbRA12240:243CS[0:3]’BDbAlways
244:245RAQuad[0:1]i244:245RAQuad[0:1]iNever
246:257RA[1:10]246:257RA[1:10]Always

260CallTOPE13 2600
261:277ToPE[1:15]261:277ToPE[1:15]Always

300* bJCN.7CJNK114 300CallUsually
301* IMRH 301bSWd’Always
302GND 302GNDAlways
303LocalBr’a 303LocalBr’aAlways
304IFUNext’a 304IFUNext’aAlways
305LongJump’a 305LongJump’aAlways
306Return’a 306Return’aAlways
307CondBr’a 307CondBr’aAlways
310bFFok’c 310bFFok’cAlways
311FA=0’ 311FA=0’Always
312FA=1’ 312FA=1’Always
313bDoCBr 313bDoCBrNever
314FF=UseDMD 314Link←BMuxaTn ge 1
315FF=TOffIsOK 315B←Link’Tn ge 1
316RIMorRTPCdly 316RIMorRTPCdlyTn ge 2
317MulStep 317MulStepTn ge 2 & no switch

320FF=TaskingOnFFEQ15 320FF=TaskingOnAlways
321FF=TaskingOff 321FF=TaskingOffAlways
322FF=MidasOn 322FF=MidasOnAlways
323Link←BMuxa 3230
324FF=WriteLink 324FF=WriteLinkAlways
325FF=Link←CPReg 325FF=Link←CPRegAlways
326FF=ReadLink 326FF=ReadLinkAlways
327B←Link’327:3310
330:333Bnt[0:3] 332FF=UseDMDAlways
334:337bPEnc[0:3] 333FF=TOffIsOkAlways
334FF=Notify’Always
335FF=MulStepAlways
336FF=BDispatchAlways
337FF=BigBDispatchAlways

340:343pNext[0:3]CJNK316340:3430
344Next=0 344Next=0Always
345CTask=0 345CTask=0Always
346PEncGtTrueNext’ 346PEncGtTrueNext’Always
347PEncLtTrueNext’ 347PEncLtTrueNext’Always
350StopTasks 350StopTasksTn ge 2
351PEnc=CT’ 351PEnc=CT’Always
352TPCBypass 352TPCBypassTn ge 2
353PreEmpting’ 353PreEmpting’Always
354bHoldA 354bHoldAAlways
355RepeatCurz 355RepeatCurzAlways
356bSwitch’a 356bSwitch’aTn ge 2
357bSwitchUp’ 357bSwitchUp’Tn ge 2

360--READY17 360--
361:377Ready[1:15]361:377Ready[1:15]

MIR166:171--MIR[0:35] in MIR format

IMOUT172:175--bdIM[0:35] in MIR format

2200:2207ClkRateCLKRUN1102200:2207ClkRateNever
2210ECLup 2210ECLupNever
2211EnRefreshPeriod’ 2211EnRefreshPeriod’Never
2212IOReset’ 2212IOReset’Never
2213RunRefresh 2213RunRefreshNever
2214MASync 2214MASyncNever
2215TBaseTempSense 22150
2216:2217--2216:2217--

ALUB20400:417alubif driven from BMux or from constant

ALUA21420:437aluaTn ge 1 driven from small constant & not shift

ABCON22 440MarMuxAEn’Tn ge 1
441AmuxEn’Tn ge 1
442:443Amux0 to 1Tn ge 1
444IOBoutTn ge 1
445BmuxEn’Tn ge 1
446:447Bmux0 to 1Tn ge 1
450:457=440:447Tn ge 1

PERR23 460EMU’Always
461CkMdParity’Tn ge 2
462:463--
464IOPerrNever
465MdPerrNever
466RmPerrNever
467TmPerrNever
470StkSelaAlways
471StkSelSavedNever
472IOBoutSavedTn ge 2
473←MDSavedNever
474:477=464:467Never

SHMV24500:517shmvPmux odd or shift’

MAR25520:537MAR.0’ to MAR.15’Tn ge 1 driven from processor, no shift,
Tn eq 2 bits 8:15 when driven by IFU,
Tn eq 2 when not driven

--26540:557--

PRFA27 560Last=Curr’Tn ge 2
561Curr=Next’Always
562Shift’Always
563IOBin’Tn ge 1
564:566FA=0’a to FA=2’aAlways
567FA=3’Always
570:577=560:567As above

SCCON30 600--
601RepeatCurrCAlways
602HoldaAlways
603LdTaskSim’Always
604FFshift’Always
605ShcWriteEn’Tn ge 1
606LoadCnt’Always
607PropCnt’if DecCnt is false
610--
611:612= 601:602Always
613LdHoldSim’Tn ge 1
614:616=604:606As above
617DecCnt’Always

QPDCON31 620QshiftL’Tn ge 1
621QshiftR’Tn ge 1
622RmaskEn’Tn ge 1
623LmaskEn’Tn ge 1
624ShiftBitsEn’Tn ge 1
625:627Pmux0 to 2Tn ge 1
630:633=620:623Tn ge 1
634ALUFWriteEn’Always
635:637= 625:627Tn ge 1

ALUCON32 640Pdata.00Tn ge 1 if source is ALU barring shifter
641Pdata.04Tn ge 1 if source is ALU
642TIOAWriteEn’Tn ge 1
643TIOABypassAlways
644MBWriteEn’Tn ge 2
645MBBypassAlways
646:647MBMux0 to 1Tn ge 1
650aluCinNever
651Pdata.08Tn ge 1 if source is ALU
652Pdata.12Tn ge 1 if source is ALU
653:656aluF0 to 3Never
657aluMNever

NEXTCL33660:663LastNext.0’ to .3’Tn ne 1
664:667CurrLast.0’ to .3’Tn ne 1
670:677=660:667Tn ne 1

RADDR34700:703Task2Back.0’ to 3’Tn ge 2
704:707Task3Back.0’ to 3’Tn ge 2
710:713RbWadr.0’ to 3’Sometimes Tn ge 2
714:717RbWadr.4 to 7Tn ge 2

STKRB35 720BCWriteEn’Tn ge 2
721Cnt=Zero’Never**
722IoattaNever**
723ResEqZero’Never**
724ResLtZero’Never**
725ALUCarryNever**
726Overflow’Never**
727RmLtZero’Never**
730RBaseBypass’Tn ge 1
731SelRBaseWadr’Always
732RBaseWriteEn’Tn ge 1
733BumpRBaseAlways
734BumpRSTKAlways
735StkPMux1Always
736StkPWriteEn’Always
737RmOdd’Never**

RTSB36 740ReSchedWrEn’Always
741NextMacroAlways
742RbWriteEn’Tn ge 2
743RbSelMdTn ge 2
744RbBypassDlyNever**
745TbWriteEn’Tn ge 2
746TbSelMdTn ge 2
747TbBypassTn ne 1
750StkPSaveEn’Tn ge 1
751StkErrorNever**
752:757= 742:747As above

PJUNK37 760FFok’aAlways
761--
762NextData’Always
763B←ExtAlways
764FF.0memAlways
765FF.1memAlways
766RisIFdataAlways
767TisIFdataAlways
770FFok’bAlways
771←MDAlways
772←MDIAlways
773B←ExtAlways
774:775SbTskDly.0’ to 1’Never
776RisIFdataAlways
777TisIFdataAlways

1000ProcVA.04PVAH 401000:10030
1001true1004:1017ProcVA.04 to 15Tn ge 2 & no clk
1002WantCHdly’
1003:1017ProcVA.07 to 19

1020MemB.0PVAL 411020:1037ProcVA.16 to 31Tn ge 2 & no clk
1021:1022ProcVA.05 to 06
1023MemB.1
1024:1037ProcVA.20 to 31

1040:1047Aad.0a to 7aMAPAD 421040:10460
1050:1057MapAd.1 to 81047:1057MapAd.0 to 8Never**

1060dVA←Vic
1061ForceDirtyMiss
1062UseMcrV
1063DisBR
1064DisCflags
1065DisHold
1066NoRefHIT 431060:10660
1067MiscPCHP’ 1067MiscPCHP’Tn ge 2
1070:1071ColVic.0 to 11070:1071ColVic.0 to 1Sometimes
1072HitColVA.par 1072HitColVA.par0 on miss
1073HitColDirty 1073HitColDirty0 on miss
1074Hita 1074Hita0 on ForceMiss if Tn ge 2
1075:1077MemB.2 to 41075:10770

1100:1101Victim.0’ to 1’HOLD 441100:11010
1102:1103NextV.0’ to 1’ 1102true
1104MiscHold’ 1103WantCHdly’Tn ge 1
1105MDhold’ 1104MiscHold’Tn ge 2
1106RefHold’ 1105MDhold’Tn ge 2
1107BLretry 1106RefHold’Tn ge 2 & not ForceMiss
1110AwasFree’ 1107BLretryIf forced to 0
1111Dbusy 1110AwasFree’Tn ge 2
1112DbufBusy 1111DbusyTn ge 2
1113AtookST 1112DbufBusyTn ge 2
1114SomeExtHold’ 1113AtookSTTn ge 2
1115Afree’ 1114SomeExtHold’On StkError % CHoldReq
1116StartMap’ 1115Afree’if EcHasA
1117AwantsMapFS’ 1116StartMap’Always
1117AwantsMapFS’Always

1120Store←InAPAIR 45 1120Store←InATn ge 2 % EcHasA
1121IoStoreInA 1121IoStoreInATn ge 2 % EcHasA
1122Map←InPair’ 1122Map←InPair’Tn ge 2
1123FlushInA 1123FlushInATn ge 2 % EcHasA
1124PrefetchInA 1124PrefetchInATn ge 2 % EcHasA
1125IfuRefInA 1125IfuRefInATn eq 2 % EcHasA
1126IoRefInA’ 1126IoRefInA’Tn ge 2 % EcHasA
1127CacheRefInA 1127CacheRefInATn ge 2 % EcHasA
1130MapAd.0 11300
1131PrivRefInPair 1131PrivRefInPairTn ge 2
1132VicInPair’ 1132VicInPair’Tn ge 2 sometimes
1133FSinPair’ 1133FSinPair’Tn ge 2 sometimes
1134bEcHasA 1134bEcHasATn ge 2
1135KillIfuRef 1135KillIfuRefAlways
1136←PrVArow 1136←PrVArowTn eq 2
1137PairFull’ 1137PairFull’Tn ge 2

1140:1143PipeAd.0 to 3PIPEAD 461140:1143PipeAd.0 to 3Tn eq 2
1144:1145CacheConfig[0:1]1144:1145CacheConfig[0:1]Never
1146:1147PageConfig[0:1]1146:1147PageConfig[0:1]Never
1150:1157--1150:1157--

MCR 57 3760dVA←VicNever
3761ForceDirtyMissNever
3762UseMcrVNever
3763:3764Victim[0:1]Never
3765:3766NextV[0:1]Never
3767DisBRNever
3770DisCflagsNever
3771DisHoldNever
3772NoRefNever
3773:37740
3775WakeOnCLNever
3776ReportSE’Never
3777NoWakeupsNever

AAD1613660:36630
3664:3673Aad.0a to 7aNever
3674:36770

MEMB1623700:37120
3713:3717MemB.0 to 5Never

1200SinD.00MEMD0 50 1200SinD.00Never
1201CD.00 1201CD.00Never
1202D0in.00 1202D0in.00
1203D1in.00 1203D1in.00
1204EcSout.00’ 1204EcSout.00’
1205EcInD.01205:12060
1206Dbuf←’
1207-- 1207--
1210D.00 1210D.00
1211dMD.00 1211dMD.00
1212D1BCE’c 1212Fout.00
1213WriteD1’d1213:12170
1214DontWriteMDM
1215:1217Dad1.10b to 12b

1220D0BCE’c
1221:1222Dad.00f to 01fDAD 511220:1221Dad.00f to 01f
1223:1231Dad.02’c to 08’c1222:1230Dad.02’c to 08’c
1232Dad.09’ 1231Dad.09’
1233:1235Dad0.10c to 12c1232:1234Dad0.10c to 12c
1236D0ACE’c1235:1237Dad1.10b to 12b
1237WriteD0’e

1240F←DFD 52 1240F←DTn ge 2
1241D←Dbuf 1241D←DbufTn ge 1
1242Sout←D 1242Sout←DTn ge 1
1243Fout←D 1243Fout←DTn ge 1
1244D←CD 1244D←CDTn ge 1
1245Md←D 1245Md←DTn ge 1
1246MakeMDM←D’ 1246MakeMDM←D’Always
1247bFastD←Dbuf 1247bFastD←DbufAlways
1250Fout.00 1250Dbuf←’Tn ge 1
1251DadH←’ 1251DadH←’Tn ge 2
1252DontLoad1 1252DontLoad1Always
1253GenPh1 1253GenPh1Tn ge 2 & EnEcGen
1254:1257-- 1254DontWriteMDMTn eq 2
1255:1257--

1260:1263MDMad.0’ to 3’EC 531260:12630
1264StartEcChk’ 1264StartEcChk’Always
1265StartEcGen’ 1265StartEcGen’Always
1266D1ACE’c 12660
1267--
1270EcInD.11267:1270EcInD.0 to 1Never
1271WordInError’ 1271WordInError’When DisableEc true
1272DisableEc’ 1272DisableEc’Never**
1273ChkPh1 1273ChkPh1Tn ge 2 & preEcEn
1274ChkPh4’ 1274ChkPH4’
1275ChkLastPh6’ 1275ChkLastPh6’
1276DoubleError’ 1276DoubleError’
1277ChkErrEn’ 1277ChkErrEn’

1300:1306tSyn0 to 6TSYN 541300:1306tSyn0 to 6
1307tSyn7x 1307tSyn7x
1310:1317--1310:1317--

MDMAD 553540:35530
3554:3557MDMad.0’ to 3’Tn ge 2

DADE 56 3560D0ACE’cTwo chip enables always
3561D0BCE’cpredicted false, other two
3562D1ACE’cif (T1Transport & (Tn ge 2))
3563D1BCE’c
3564WriteD0’eTn ge 2
3565WriteD1’dTn ge 1
3566:35770

MAPBUF601400:1417Mapbuf[0:15]Tn ge 2

P34INEC611420:1421Mapbuf.16 to 17Tn ge 2
1422ProcTagInATn ge 2
1423PrivRefInPairAlways
1424:1427Pipe34Ad.0 to 3Tn ge 2
1430WPinEc1Tn ge 2
1431MapTroubleInEc1Tn ge 2
1432TagInEc2Never
1433CacheRefInEc2Never
1434Store←InEc2’Never
1435IFURefInEc2Never
1436MapPEInEc2Never
1437MapTroubleInEc2Tn ge 2

MCDTSK621440:1443MDMtagAd.0 to 3Always
1444:1447CurTask.0 to 3Always
1450ProcTagAlways
1451MDMtag’If CacheRefInPair & (Atask eq CurTask)
1452At=Curt’Always
1453Dt=Curt’Always
1454:1457Dtask[0:3]Never

STA63 1460VictimInSTTn ge 2
1461STIdle’Always
1462StartSTAlways
1463STWait-Mem’Tn ge 2
1464:1467STState[0:3]Tn ge 2
1470STfree’Tn ge 2
1471VictimInAAlways
1472MapRfshDlyTn ge 1
1473RefUsesDInEc1Tn ge 2 & StartEc1
1474AWordRefToDAlways
1475MapWantsPipeTn ge 2
1476MapFreeTn ge 2
1477UseAsrnTn ge 2

APESRN641500:1503Asrn.0 to 3Tn ge 2
1504:1507ProcSrn.0 to 3Tn ge 2
1510MapIs16KNever
1511MapIs64KNever
1512MapIs256KNever
1513RfshAd.0Never
1514:1517Ec2Srn[0:3]Tn ge 2

STOUT65 1520LoadEn’Never
1521EcLoadEn’Never
1522ShiftEn’Tn ge 2
1523EnEcGen’Tn ge 2
1524MapWait-ST’Tn ge 2
1525STPerrNow’Never
1526EnableAllModsNever
1527StartEc1Never
1530PairFullAlways
1531TransportaAlways
1532EcFault’Never
1533MemError’Never
1534--
1535ChipsAre256/16KNever
1536ChipsAre64KNever
1537VicSTPerr-.Never

TAGAT66 1540MemColSelaNever
1541EcHasATn ge 2
1542PtagNever
1543MapWait-Ec2Tn ge 2
1544Dtag’Tn ge 2
1545sHoldAlways
1546MapWait-MemState’Always
1547MapRfshAlways
1550AcanHaveDTn ge 2
1551CacheRefInPair’Tn ge 2
1552EcWordRefToDAlways
1553ChkLastPh6Tn ge 2
1554:1557Atask.0 to .3Tn ge 2

MEMST67 1560MapWait-MemDNever
1561MapWait-MemIOAlways
1562MemIdle’Always
1563MemFreeTn ge 2
1564:1567MemState.0 to 3Tn ge 2
1570FinNextTn ge 2
1571MemRfshTn ge 2
1572StopFinTaskLoadTn ge 2
1573DdataGood’Tn ge 2
1574MakeSout←DTn ge 2
1575:1577MakeTransport[0:2]Never**

--701600:1607--

FLTMEM71* 1620WakeOnCL
* 1621ReportSE’
* 1622NoWakeups
1623ProcSrn←’Tn ge 1
1624FaultsNever
1625LoadFltSrnIf independent of FaultSrn eq 0
1626ReportFaultAlways
1627MapPEInMemNever
1630MapTroubleInMemNever
1631RfshInMemTn ge 2
1632WriteInMem’Tn ge 2
1633MemWPNever
1634IOFetchInMem’Tn ge 2
1635RefUsesD10InMem’Tn ge 2
1636RefUsesDInMemTn ge 2
1637DirtyIOFetchInMemTn ge 2

RFSSRN72 1640STPerrNever
1641MapPerrNever
1642HitPerrNever
1643WantRfshTn ge 2
1644NeedRfshAlways
1645StartMemaTn ge 2
1646StkWakeNever
1647←FaultInfoDly’Never
1650:1653MapSrn.0 to 3Tn ge 2
654:1657MemSrn.0 to 3Tn ge 2

EC1MAKE73 1660StartEc2’Tn ge 2
1661Ec1Free’Tn ge 2
1662Ec1IdleAlways
1663:1664Ec1Func.0 to 1Tn ge 2
1665:1667Ec1State.0 to 2Tn ge 2
1670EcWantsAaTn ge 2
1671FoutNextTn ge 2 usually
1672MakeFout←DTn ge 2 usually
1673MakeD←CDTn ge 2 usually
1674MakeD←DbufAlways
1675MakeF←DAlways
1676MakeMD←DAlways
1677MakeMDM←D’Tn ge 2

MAPCTRL741700:1701MapbufHi.0 to 1Never
1702MapRAS’Tn ge 2 when forced high
1703MapCAS’Tn ge 2 when forced high
1704MapWE’Tn ge 2 % StartMap
1705RefWE’Tn ge 2
1706DirtyWE’Tn ge 2 % StartMap
17070
1710MapWaitAlways
1711WantMapWait’Always
1712ValidMapFltInEc2’Tn ge 2
1713:1714MapFnc.0’ to 1’Tn ge 2
1715:1717MapState.0 to 2Tn ge 2

PEEC751720:1723PEsrn.0 to 3Always
1724:1727Ec1Srn.0 to 3Tn ge 2
1730CacheLoad’Always
1731Ec2FreeTn ge 2
1732Ec2IdleAlways
1733:1734Ec2Func.0 to 1Tn ge 2
1735:1737Ec2State.0 to 2Tn ge 2

INMAP76 1740RefUsesDInMap’DirtyIOFetchInMap % ((Tn ge 2) & StartMap)
1741RefUsesD10InMap’Tn ge 2
1742DirtyIOFetchInMap’Never
1743WriteInMap’Tn ge 2
1744IOFetchInMap’Tn ge 2
1745←MapInMapNever
1746Store←InMap’Tn ge 2
1747EcWantsPipe4’Tn ge 2
1750:1757--

KSTATE100 20000
2001IndexTW
2002SectorTW
2003SeekTagTW
2004RdFifoTW
2005WrFifoTW
2006ReadData
2007WriteData
2010EnableRun
2011DebugMode
2012RdOnlyBlock’
2013WriteBlock’
2014CheckBlock’
2015Active
2016:2017Select[0:1]

KSTAT101 2020SeekInc
2021HeadOvfl
2022DevCheck
2023NotSelected
2024NotOnLine
2025NotReady
2026SectorOvfl
2027FifoUnderflow
2030FifoOverflow
2031ReadDataErr
2032ReadOnly
2033CylOffset
2034IOBParityErr
2035FifoParityErr
2036WriteError
2037ReadError

KRAM1022040:2043RamAddr[0:3]
2044:2057Ram[4:15]

KTAG103 2060DriveTag
2061CylinderTag
2062HeadTag
2063ControlTag
2064Tag.000
2065Tag.00
2066:2077Tag[0:9]

KFIFO104 2100ShiftIn
2101ShiftOut
2102ComputeECC
2103NextBlock
2104LoadTag
2105CntDone’
2106OutRegFull
2107InRegFull
2110:1113FifoWaddr[0:3]
2114:2117FifoRaddr[0:3]

ERX0105 2120PDNew
2121PDOld
2122:2125PDCnt[0:3]
2126PDCntCtrl
2127ReportCollisions
2130RxWakeupsOn
2131EthData.18
2132RxCRCError
2133--
2134RxDataLate
2135RxBusRegFull
2136RxFifoFull
2137RxFifoEmpty

ETX1062140:2142TxState[0:2]
2143TxEOP
2144TxBusRegFull’
2145TxGone
2146TxSREmpty’
2147TxCntDwn’
2150TxCRCEnbl
2151TxGo
2152TxData
2153:2154TxSRCtrl[0:1]
2155PEOutput
2156TxFifoFull
2157TxFifoEmpty

ERX11072160:2162RxState[0:2]
2163RxCollision
2164PDCarrier
2165:2166PDEvent[0:1]
2167RxSRFull’
2170RxEOP
2171RxSync’
2172RxIncTrans
2173RxCRCReset
2174RxCRCClk
2175RxData
2176:2177RxSRCtrl[0:1]

MEMRQ1202400:2407PcF[8:15]Tn eq 2 & Testing’
2410NewFTn eq 2 & Testing’
2411KillResponseTn ge 1 & Testing’
2412PauseTn ge 2 & Testing’ unless IFUM write
2413RefOutstandingNever
2414IncPcFNever
2415IncPcFG’Always
2416WantIfuRef’Always
2417ThreeOutOfFiveAlways

LOADS121 2420ValidRamAlways
2421J←OddFAlways
2422RealPcFG.15Tn eq 2 & Testing’ unless IFUM write
2423FDvTn eq 2 & Testing’ unless IFUM write
2424GDvTn eq 2 & Testing’ unless IFUM write
2425HDvTn eq 2 & Testing’ unless IFUM write
2426JDvTn eq 2 & Testing’ unless IFUM write
2427MDv’Tn eq 2 & Testing’ unless IFUM write
2430EnableFG’Always
2431XLdAlways
2432AlphaXLdAlways
2433BrkLdTn ne 1
2434MLdAlways
2435InstrAddrLdTn ge 2
2436JLdaAlways
2437GLd’Always

HJ1222440:2447H[0:7]Never
2450:2457J[0:7]bTn ge 2 & Testing’ unless IFUM write when no clock or
on J←H the 1’s are checked

MX123 2460TwoAlphaXTn ge 2 & Testing’
2461JFaultTn ge 2 & Testing’ unless IFUM write
2462HFault’Tn eq 2 & Testing’
2463NM=17Tn ge 2 & Testing’
2464TwoAlphaMTn ge 2 & Testing’
2465TypeJumpM’Tn ge 2 & Testing’
2466:2467LengthM[0:1]Tn ge 2 & Testing’
2470:2471DSel[0:1]Tn ge 2 & Testing’ unless XShift with DSel eq 0
2472:2473LengthX[0:1]Tn ge 2 & Testing’
2474:2477NX[0:3]Tn ge 2 & Testing’ when unclocked or NM eq 17

JMPEXC124 2500ExceptionAlways
2501SayNotReadyAlways
2502WantReschedTn ge 2 & Testing’
2503SawRamParityErrOnly during Reset
2504SawFGParityErrOnly during Reset or when testing
2505ReschedPendingTn ge 2 & Testing’
2506KReadyAlways
2507--
2510ZapFGHAlways
2511ZapJAlways
2512NewJTn ge 2 & Testing’ unless IFUM write
2513DoJumpTn ge 2 & Testing’ unless IFUM write
2514TurnOffAluTn even
2515NewGoAlways
2516BMuxEnableTn even
2517FGFaultNever

PCJ1252520:2527PcJ[8:15]Tn eq 2 & Testing’ unless IFUM write
2530MLdDly’Tn ge 2 & Testing’
2531BetaInMTn ge 2 & Testing’
2532FGErrDlyTn ge 2
2533RamErrDlyTn ge 1
2534:2535InstrSetNever**
2536OneByteJumpInJTn ge 2 & Testing’
2537OneByteJumpInJdTn ge 2 & Testing’

FFK126 2540Test←Tn ge 1
2541GenOut←’Tn ge 1
2542NewPC←Tn ge 2 & Testing’
2543IfuResetTn ge 2
2544BrkIns←Tn ge 2 & Testing’
2545TestingTn ge 2
2546SignX’Never
2547BrkPendingTn eq 2 & Testing’
2550:2552--
2553TypeJumpK’Never
2554TypePauseK’Never
2555:2556LengthK[0:1]Never
2557SignKNever

APTRS140 3000ACurrentWCBFlagNever
3001:3007AReaderPtr.1 to 7Never
3010ANextWCBFlagNever
3011:3017AWriterPtr.1 to 7Never

BPTRS141 3020BCurrentWCBFlagNever
3021:3027BReaderPtr.1 to 7Never
3030BNextWCBFlagNever
3031:3037BWriterPtr.1 to 7Never

ITEMS1423040:3047AItem.0 to 7Never
3050:3057BItem.0 to 7Never

SPSIZE1433060:3063AServicePtr.1 to 4Never
3064:3067BServicePtr.1 to 4Never
3070AFifoFullNever
3071BFifoFullNever
3072ASize8Never
3073ASize8-4Never
3074ASize8-4-2Never
3075BSize8Never
3076BSize8-4Never
3077BSize8-4-2Never

RESON144 3100AOnNever
3102BOnNever
3103:3104ARes.0 to 1Never
3105:3106BRes.0 to 1Never
3107OISRcvdDataNever
3110:3117--

TEMP160 3500CBTempNever
3501BaseTempNever
3502ProcHTempNever
3503ProcLTempNever
3504IFUTempNever
3505DskEthTempNever
3506:3517--

BMUX163 --BMux[0:17]if driven from ALUB

ESTAT164 4020PEIMrh
4021PEIMlh
4022MdPE
4023RAMPEen
4024IOBPE
4025RAMPE
4026MemPE
4027MemPEen
4030CIMPErh
4031CIMPElh
4032Stopped
4033MdPEen
4034IMrhPEen
4035IMlhPEen
4036IOBPEen
4037MIRDebugen