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Dorado Hardware ManualTable Of Contents14 September 1981
Table of Contents
1.Introduction
2.Overview 2
2.1Control
2.2Registers, Memories, and Data Paths
2.3Timing
2.4Instruction Fields
2.6Notation
3.Processor Section
3.1RM and STK Memories, RBase and StkP Registers
3.2Cnt Register
3.3Q Register
3.4T Register
3.5BSEL: B Multiplexor Select
3.6ASEL: A Source/Destination Control
3.7ALUF, ALU Operations
3.8LC: Load Control for RM and T
3.9FF: Special Function
3.10Multiply and Divide
3.11Shifter
3.12Hold and Task Simulator
4.Control Section 26
4.1Tasks 26
4.2Task Switching 26
4.3Next Address Generation
4.4Conditional Branches
4.5Subroutines and the Link Register
4.6Dispatches
4.7IFU Addressing
4.8IM and TPC Access
4.9Hold
4.8Program Control of the DMux
5.Memory Section 36
5.1Memory Addressing 36
5.2Processor Memory References
5.3IFU References
5.4Memory Timing and Hold
5.5The Map
5.6An Automatic Storage Management Algorithm
5.7Mesa Map Primitives
5.8The Pipe
5.9Faults and Errors
5.10Storage
5.11The Cache
5.12Initialization
5.13Testing
6.Instruction Fetch Unit 64
6.1Overview of Operation 64
6.2The IFUJump Entry Vector
6.3Timing Summary
6.4Use of MemBX and Duplicate Stk Regions
6.5Traps
6.6IFU Reset
6.7Rescheduling
6.8Breakpoints
6.9Reading and Writing IFUM
6.10Continuing from Processor Faults
6.11IFU Testing
6.12Details of Pipe Operation
6.13Timing Details
7.Slow IO 85
7.1Input/Output Functions 85
7.2IO Opcodes
7.3Wakeup, Block, and Next
7.4SubTasks
7.5Illegal Things IO Tasks Must Not Do
8.Fast IO 90
8.1Transport 90
8.2Wakeups and Microcode 90
8.3Latency
9.Disk Controller 92
9.1Disk Addressing 93
9.2Sector Layout Considerations 93
9.3General Firmware Organization 95
9.4Task Wakeups 96
9.5Control Register 97
9.6Format RAM and Sequence PROMs 97
9.7Tag Register 99
9.8FIFO Register 101
9.9Muffler Input 101
9.10Error Detection and Correction 104
10.Display Controller 109
10.1Operational Overview 109
10.2Video Data Path 110
10.3Horizontal and Vertical Control 113
10.4Pixel Clock System 115
10.5OIS Seven-Wire Video Interface 116
10.6Processor Task Management 117
10.7Slow IO Interface 119
10.8DispM Terminal Interface 121
10.9DDC Initialization Requirements 122
10.10Speed and Resolution Limits 122
11.Ethernet Controller 124
11.1Ethernet Packets 124
11.2Controller Overview 125
11.3Receiver 127
11.4Transmitter 128
11.5Clocks 129
11.6Task Wakeups 129
11.7Muffler Input 130
11.8IOB Registers 131
11.9Control Register 131
11.10Status Register 132
12.Other IO and Event Counters 133
12.1Junk Task Wakeup 133
12.2General IO 133
12.3Event Counters 133
13.Error Handling 136
13.1Processor Errors 137
13.2Control Section Errors 139
13.3IFU Errors 139
13.4Memory System Errors 139
13.5Sources of Failure 140
13.6Error Correction 141
14.Performance Issues 144
14.1Cycle Time 144
14.2Emulator Performance 144
14.3IFU Not-Ready Wait 145
14.4Microstore Requirements 145
14.5Cache Efficiency and Miss Wait 146
14.6Performance Degradation Due to IO Tasks 147
14.7Cache and Storage Geometry 147
15.Glossary 150
List of Tables
1.Memories 3
2.Registers 4
3.Data Paths 5
4.Load Timing 7
5.Instruction Fields 8
6.RSTK Decodes for Stack Operations 11
7.BSEL Decodes 13
8.ASEL Decodes 15
9.ALUFM Control Values 17
10.LC Decodes 19
11.FF Decodes 20
12.ALUF Shift Decodes 25
13.Branch Conditions 30
14.Reserved Locations in the Microstore 33
15.Timing of a Dirty Miss 44
16.Map Configurations 45
17.Fault Indications 54
18.IFUM Fields 65
19.Operand Sequence for ←Id 66
20.IFU FF Decodes 68
21.IO Register Addresses 85
22.Task Assignments 86
23.T-80 Specifications and Characteristics 95
24.OIS Terminal Microcomputer Messages 117
25.DDC Muffler Signals 120
26.Ethernet Muffler Signals 130
27.Error-Related Signals 137
28.Double Error Incidence vs. Repair Rate 143
29.Utilization of the Microstore 145
30.Execution Time vs. Cache Efficiency 146
31.Cache Geometry vs. LRU Behavior 149
List of Figures
1.Dorado: Programmer’s View
2.Card Cage
3.Processor Hardware View
4.Shifter
5.Control Section
6.Next Address Formation
7.Instruction Timing
8.Overall Structure of the Memory System
9.Cache, Map, and Storage Addressing
10.The Pipe and Other Memory Registers
11.Error Correction
12.Instruction Fetch Unit Organization
13.Disk Controller
14.Display Controller
15.Display Controller IO Registers
16.Ethernet Controller
17.Programmers’ Crib Sheet