// D1Ti.bcpl -- T1, T2, T3, and Rep-T2 actions // Last edited: 20 November 1979 get "mcommon.d" manifest [ get "d1regmem.d" ] external [ // OS DoubleAdd; Zero // MINIT0 @MBlock // MASM @WssCSS; PutsCSS; WssCS1 // MDATA @LoopCount // MRGN AddToEveryTimeList; RemoveFromEveryTimeList // MCMD SetAbort; QuitCmdOverlay // MGO @CantContinue; @QuitF; HaltWaitMenu // D1I0 @SaveMIR // D1ACTIONS @LongOne // D1ASM @DoStrobe; ReadDMux; LoadMIR // D1RES ReadAllRegs; RestoreD1Temps // D1GO OneStep // Defined here TiAct; RepT2 ] //Execute the instruction now in MIR through ti, read the DMux after //that clock, and finish off the instruction if at t1 or t3 //Affect as nearly as possible is as though the instruction had been //inserted into the control flow of the program let TiAct(Ti,MBunion,nil) be [ let V = vec 3; MBlock(V,SaveMIR,4) RestoreD1Temps() LoadMIR(V) CantContinue = CantContinue % didTn WssCSS("Clock MIR through t") PutsCSS($0+Ti) WssCSS(", read DMux, and restore") //Turn off UseCPReg, ClrBNT, and Freeze. DoStrobe(Clock) if Ti ge 2 do OneStep(Control+SetRun+SetSS) //Note that StopAtt1 has to stay on until back at even clock again if (Ti & 1) ne 0 do OneStep(Control+StopAtt1+SetRun+SetSS) ReadDMux() if (Ti & 1) ne 0 do //Must continue on to even clock [ DoStrobe(Clock); OneStep(Control+StopAtt1+SetRun+SetSS) ] LoadMIR(V); MBlock(SaveMIR,V,4) //ReadAllRegs(1) reads the machine state without changing the //break or continue address information ReadAllRegs(1) ] and DoT2(nil) be [ DoubleAdd(LoopCount,LongOne); OneStep(Control+SetRun+SetSS) LoadMIR(SaveMIR) ] and RepT2(nil,nil,nil) = valof [ SetAbort(lv HaltRT2,nil) Zero(LoopCount,2) RestoreD1Temps(); LoadMIR(SaveMIR) CantContinue = CantContinue % didTn QuitF = AddToEveryTimeList(DoT2) DoStrobe(Clock) WssCSS("Repeatedly executing MIR through t2 and reloading it...") WssCS1("(Flags in Clock and Control are all false)") resultis HaltWaitMenu ] and HaltRT2(nil,nil,nil) be [ WssCSS("Halted"); RemoveFromEveryTimeList(QuitF); QuitCmdOverlay() ]