//D1Prin5.bcpl	Procedures to prettyprint various registers and memories
//	Last edited: 20 November 1979

get "d1.d"
manifest [ get "d1regmem.d" ]

external [
// MASM
	@WssCSS; PutsCSS; PutsCS1; WssCS1; @OddParity

// MIOC
	DWns

// MCMD
	WnsCSS; WnsCSSD; WnsCS1; WnsCS1D; CmdCommentStream; CmdCS1
	PassiveOnly

// MPRINS
	PrinV0; PrinV1; NWss; NWss1

// MPATTERN
	@PATTERN

// D1MEM
	MGetMemData

// D1RES
	HWShowAddr

// D1CONFIG
	CacheAMask0; CacheAMask1; log2rows

// Defined here
	PrintMAP; PrintCONFIG; PrintPIPE; PrintCACHEA; PrintROW
	PrintINSSET
]


let PrintMAP(X,DVec,AVec,Radix) be
[	PATTERN = DVec!0
	NWss("MapDirtyb ",#40)
	NWss("MapParity ")
	NWss("MapPE ")
	NWss("Ref ")
	NWss("WP ")
	NWss("Dirty ")
	PrinV0("RP[0:15]",DVec!1)
]


//All signals are high-true in DVec
and PrintPIPE(X,DVec,AVec,ExtRadix) be
[	let Extension = ExtRadix<<lh
	let AVec1,T = vec 1,nil
	PATTERN = DVec!0
	switchon Extension into
	[
//Pipe0 and Pipe1
case 0:	PrinV0("VA[4:31]",DVec!0); PutsCSS($ ); WnsCSS(DVec!1)
	HWShowAddr(VMx,DVec); endcase

//Pipe2 and Pipe3
case 1:	T = PATTERN rshift 14
	PrinV0("RefType",T)
	WssCSS(" (=")
	WssCSS(selecton T into
	[ case 0:	"undef.)"
	  case 1:	"storage read)"
	  case 2:	"storage write)"
	  case 3:	"Map_ or non-storage op)"
	] )
	PrinV0(", Subtask",(PATTERN rshift 12) & 3B)
	PrinV0(", Task",PATTERN<<nib1)
	NWss1("Emulator fault, ",#200)
	PrinV1("NumFaults",(PATTERN rshift 4) & 7B)
	PrinV1(", FirstFaultSRN",PATTERN<<nib3)
	PrinV1(", RP",DVec!1); endcase

//Pipe4 and Pipe5
case 2:	NWss("Ref ",#100000)
	NWss("WP ",#20000)
	NWss("Dirty ")
	T = ((PATTERN rshift 10) & 3)+((PATTERN rshift 12) & 4)
	WssCSS(selecton T into
	[ case 0:	"no fault "
	  case 1:	"SE "
	  case 2 to 3:	"DE "
	  case 4 to 5:	"PgFlt "
	  case 6 to 7:	"MapPE "
	] )
	PrinV0("Quadword",(PATTERN rshift 8) & 3)
	T = PATTERN<<rh
	PrinV0(" Syndrome",T)
	switchon T into
	[
case 1:	  PrinChkBit($7); endcase	//Parity bit
case 2:   PrinChkBit($6); endcase
case 4:   PrinChkBit($5); endcase
case 8:   PrinChkBit($4); endcase
case 16:  PrinChkBit($3); endcase
case 32:  PrinChkBit($2); endcase
case 64:  PrinChkBit($1); endcase
case 128: PrinChkBit($0)
case 0:	  endcase
default:  test OddParity(T,0)
	  ifso		//Single error (or odd no. errors)
	  [ let Word = table [ 4; 4; 4; 0; 4; 1; 2; 3 ] ! ((T & 16B) rshift 1)
	    test Word le 3
	    ifso
	    [ //Mirror image left four bits to get bit number
	      let Bit = table [ #0; #10; #4; #14; #2; #12; #6; #16
				#1; #11; #5; #15; #3; #13; #7; #17 ] !
			(T rshift 4)
	      WssCSS(" (= SE in bit "); WnsCSSD(Bit)
	      WssCSS(", word "); WnsCSS(Word); WssCSS(") ")
	    ]
	    ifnot WssCSS(" (**Syndrome word code bad**) ")
	  ]
	  ifnot		//Even no. errors ge 2
	  [ WssCSS(" (= multiple error) ")
	  ]
	]
	PATTERN = DVec!1
	NWss1("MapBufBusy ",#100000)
	NWss1("FlushStore ")
	NWss1("Tag ")
	NWss1("CacheRef ")
	NWss1("Store ")
	NWss1("IFUref ")
	PrinV1("ColVic",(PATTERN & 1400B) rshift 8)
	NWss1(" Dirty",#200)
	NWss1(" Vacant")
	NWss1(" WP")
	NWss1(" BL")
	PrinV1(" NV",(PATTERN rshift 2) & 3)
	PrinV1(" V",PATTERN & 3)
	]
]


and PrinChkBit(Char) be
[	WssCSS(" (= chk bit "); PutsCSS(Char); WssCSS(" bad) ")
]


and PrintCONFIG(X,DVec,AVec,Radix) be
[	PATTERN = DVec!0
	PrinV0("ProcSRN[0:3]",PATTERN<<nib0)
	PrinV0(" Asrn[0:3]",PATTERN<<nib1)
	NWss(" M0",#200)
	NWss(" M1")
	NWss(" M2")
	NWss(" M3")
	WssCS1("Storage IC size = ")
	WnsCS1D(table [ 4; 16; 64; 256 ] ! ((PATTERN rshift 2) & 3))
	PutsCS1($k)
	NWss1(" MapDirtyb",#2)
	NWss1(" MapParity")
]


and PrintCACHEA(X,DVec,AVec,Radix) be
[	let DV1,AV1 = vec 18,vec 1
	AV1!0 = 0; AV1!1 = AVec!1 lshift 4
//Also print the contents of CACHED
	unless PassiveOnly do
	[ for I = 0 to 15 do
	  [ MGetMemData(CACHEDx,DV1+I,AV1); AV1!1 = AV1!1+1
	  ]
	  for I = 0 to 7 do
	  [ DWns(CmdCommentStream,DV1+I,16,0,8,6,$0)
	    PutsCSS($ )
	  ]
	  for I = 8 to 15 do
	  [ DWns(CmdCS1,DV1+I,16,0,8,6,$0); PutsCS1($ )
	  ]
	]
//DVec has zeroes in bits which aren't stored in the cache address
//section so simply add in the row bits.
	DV1!0 = DVec!0 & 7777B
	DV1!1 = DVec!1 + ((AVec!1 & ((1 lshift log2rows)-1)) lshift 4)
	WssCSS(" VA="); DWns(CmdCommentStream,DV1,32,0,Radix)
	PATTERN = DVec!0
	NWss1(" Dirty",#100000)
	NWss1(" Vacant")
	NWss1(" WP")
	NWss1(" BL")
]


and PrintROW(X,DVec,AVec,ExtRadix) be
[	let Extension = ExtRadix<<lh
	test Extension eq 4
	ifso
	[ PrinV0("NextV",DVec!0 rshift 14)
	  PrinV0(" Victim",(DVec!0 rshift 12) & 3)
	]
	ifnot
	[ let AVec1 = vec 1; AVec1!0 = 0
	  AVec1!1 = (AVec!1)+(Extension lshift log2rows)
	  PrintCACHEA(X,DVec,AVec1,ExtRadix<<rh)
	]
]


and PrintINSSET(X,DVec,AVec,Radix) be
[	PrinV0("_Id count",DVec!0 rshift 13)
	PrinV0(", InsSet",(DVec!0 rshift 11) & 3)
]