BUILTIN[M,2];		*Declare macro
BUILTIN[N,3];		*Declare neutral
BUILTIN[MEMORY,4];	*Declare MEMORY[NAME,WORDSIZE,LENGTH,SRCMACRO,
			*SINKMACRO]
BUILTIN[TARGET,5];
BUILTIN[DEFAULT,6];
BUILTIN[FLX,7];		*Declare field
BUILTIN[PF,10];		*Preassign value to field
BUILTIN[SET,11];	*Declare integer and set value
BUILTIN[ADD,12];	*Add up to 8 integers
BUILTIN[IP,13];		*Integer part of adddress
BUILTIN[IFSE,14];	*If string equal
BUILTIN[IFA,15];	*If any bits of field assigned
BUILTIN[IFE,16];	*If integers equal
BUILTIN[IFG,17];	*If integer #1 .gr. integer #2
BUILTIN[IFDEF,20];	*If symbol in symbol table and not unbound address
BUILTIN[IFME,21];	*If memory part of address .eq. string
BUILTIN[ER,22];		*Error message (ER[STRING,ABORTFLAG,INT])
BUILTIN[LIST,23];	*Set listing mode for memory
BUILTIN[INSERT,24];	*Insert file
BUILTIN[NOT,25];	*1's complement
BUILTIN[REPEAT,26];	*Repeat the text #2 #1 times
BUILTIN[OR,27];		*Inclusive or up to 8 integers
BUILTIN[XOR,30];	*Exclusive or up to 8 integers
BUILTIN[AND,31];	*And up to 8 integers
BUILTIN[COMCHAR,32];	*Set comment char for conditional assemblies
*BUILTIN[BITTABLE,33];	*Makes #1 a bit table of length #2 bits
*BUILTIN[GETBIT,34];	*Is the bit in bit table #1 at pos. #2
*BUILTIN[SETBIT,35];	*SETBIT[TABLE,1STBIT,NBITS,DISTANCE,VAL]
*BUILTIN[FINDBIT,36];	*FINDBIT[TABLE,1STBIT,NBITS,DISTANCE,HOPDISTANCE,NHOPS]
*BUILTIN[MEMBT,37];	*MEMBT[MEMORY,TABLE] creates a bit table for memory
BUILTIN[LSHIFT,40];	*Shifts the integer #1 left #2 positions
BUILTIN[RSHIFT,41];	*Shifts the integer #1 right #2 positions
BUILTIN[FVAL,42];	*FVAL[FIELD] is an integer whose value is the
			*current contents of the field
BUILTIN[SELECT,43];	*#1 is an integer .ge. 0 and .le. 7.  Evaluates
			*#2 if #1 = 0, ..., #9 if #1 = 7.  Error if #1 > 7
BUILTIN[SETPOST,44];	*Set post-evaluation macro (SETPOST[MEM,MACRO])
BUILTIN[LISTFIELDS,46];	*LISTFIELDS[mem,word] assembles word as for DEFAULT
			*and the 1-bit denote the right-most bits of
			*fields in the octal listing.
*BUILTIN[SETMBEXT,47];	*Set binary output file extension (default .MB)
BUILTIN[SUB,50];	*SUB[a1,a2,...,an] = a1-a2-...-an (16-bit args)

COMCHAR[~];		*Makes "*~" Work like "%" at beginning of lines

ER[D1DLANG-model1.4/30/80];	*Print release date on .ER file

*Memory declarations must have names and sizes agreeing with Midas.
M[W,];			*Dummy macro required for memory defs.
MEMORY[LDR,44,140,W,W];	*Alto memory holding instructions that will be
			*executed by ramming into MIR (assembled in IM
			*format, not involuted MIR format)
MEMORY[MDATA,44,10,W,W];	*Alto memory for BITS-CHECKED, etc.
MEMORY[MADDR,40,15,W,W];	*Alto memory for LOW-ADDRESS, etc.
MEMORY[DMUX,20,200,W,W];	*DMUX
MEMORY[$ABSOLUTE,10,77777,W,W]; *Wrong length, but Micro can't handle
			*larger lengths (want 200000 here).
MEMORY[$ABS,20,77777,W,W];	***Want 100000 here after Micro fix
MEMORY[MSTAT,40,24,W,W];

LDR[LDRLC,0];		*Location counter for LDR

SET[XTASK,0];

%"TITLE" outputs the file name and the value of ILC on the .ER file
to help correleate errors with source statements.  It also resets
various assembly flags to standard states.
%
M[TITLE,(ER[#1] SET[XTASK,0] TARGET[LDRLC])];
M[END,(ER[Last.location...LDRLC=,0,IP[LDRLC]])];

*LDR memory field definitions
FLX[RSTK,0,3];		*RM address or STK modification
  FLX[RSTK13,1,3];	*RSTK1 is parity bad for IM write
			*RSTK.2 is value for RSTK.0 on IM l.h. write,
			*or value for BLOCK on IM r.h. write.
			*RSTK.3 is 0 for l.h. write, 1 for r.h. write
  FLX[RSTK23,2,3];	*Byte select for READIM
FLX[ALUF,4,7];		*ALU function select (addresses ALUFM)
FLX[BSEL,10,12];	*Source for B
  FLX[BSEL0,10,10];	*High bit of BSEL (indicates constant selected)
FLX[LC,13,15];		*Source (H3,Md) and loading for RM/STK and T
FLX[ASEL,16,20];	*A operation select
  FLX[ASEL0,16,16];
FLX[BLK,21,21];		*Block task (non-emu) -or- StackSelect (emulator)
FLX[FF,22,31];		*Function
  FLX[FA,22,23];	*FF[0:1] used with memory ops
  FLX[F1,22,25];	*FF[0:3] used with constants and FF shifts
  FLX[F2,26,31];	*FF[4:7] "
  FLX[FBC,24,31];	*FF[2:7] used when memory ops done
FLX[JCN,32,41];		*Jump control


%Second arg of LIST controls output as follows:
1 = (TAG) nnnn nnnn nnnn ...
2 = (TAG) F1_3, F2_4, ...
4 = numerically-ordered list of address symbols
10 = alphabetically-ordered list of address symbols
20 = (TAG) 1nnnnn 1nnnnn ... (16-bit rather than 12-bit printout)
%
LISTFIELDS[LDR,RSTK[1] ALUF[1] BSEL[1] LC[1] ASEL[1] BLK[1] FF[1] JCN[1]];
LIST[LDR,25]; LIST[MDATA,25]; LIST[MADDR,25]; LIST[$ABSOLUTE,25];
LIST[,25];


M[FFT,ER[FF.used.twice]];
M[FAT,ER[FA.used.twice]];
M[IMPB,ER[Impossible.B_]];
M[ILLIO,IFE[XTASK,0,,ER[#1.ill.in.io.task]]];
M[ILLEM,IFE[XTASK,0,ER[#1.ill.in.emulator]]];
M[TMARGS,ER[Too.many.args.for.#1]];

*Execute #1 if FF field not used as data, else #2
M[FFOK,IFE[FVAL[BSEL0],1,#2,#1]];

M[FF64,IFA[FBC,(FFT),FBC[#1]]];
M[FF256,IFA[FF,(FFT),FF[#1]]];

*The following macros define B destinations encodable as either
*FF64/FF256 or, if FF encodes an external B source, in BSEL.
*#1 is the value for FF, #2 for BSEL
M[FFBSL1,IFG[FVAL[FF],177,(IMPB),IFG[FVAL[FF],157,BSEL[#1],(IMPB)]]];
M[FFBSEL,IFA[FBC,IFE[FVAL[ASEL0],1,FFBSL1[#2],(IMPB)],FBC[#1]]];
M[FFBSEL256,IFA[FF,IFE[FVAL[ASEL0],1,FFBSL1[#2],(IMPB)],FF[#1]]];

%Three macros define parameters from which constants, small constants,
RM values, or IM data can be constructed:
   MP[NAME,OCTALSTRING] makes a parameter of NAME;
   SP[NAME,P1,P2,P3,P4,P5,P6,P7,P8] makes a parameter NAME equal to the sum
of P1, P2, P3, P4, P5, P6, P7, and P8, where the Pn may be parameters or
addresses.
   NSP[NAME,P1,P2,P3,P4,P5,P6,P7,P8] is ones complement of SP.

The parameter "NAME" is defined by the integer "NAME!", so it is ok
to use "NAME" for a constant as well as a parameter.  However, it is
illegal to define constants, small constants, addresses, etc. with
identical names.

"Literal" constants such as "322C", "177422C", "32400C", or "32377C"
or literal small constants such as "14S", etc. may be inserted in
microinstructions without previous definition.

Alternatively, constants may be constructed from parameters, integers,
and addresses using the following macros:
   MC[NAME,P1,P2,P3,P4,P5,P6,P7,P8] defines name as a constant with value =
sum of parameters P1, P2, P3, P4, P5, P6, P7, and P8;
   NMC[NAME,P1,P2,P3,P4,P5,P6,P7,P8] is the ones complement of MC;
   MSC[NAME,P1,P2,P3,P4] defines a small constant.

NOTE:  MC, NMC, and MSC also defined NAME as a parameter.
%

*Fields for initializaing 16-bit wide memories
FLX[E0,0,3]; FLX[E1,4,17];

*Macro to initialize 16-bit variables in the target memory.  This is
*done by writing 32100V (i.e., as a literal).
M[V,E1[#1] E0[#2]];

M[!,0];
M[MP,SET[#1!,#2]];
M[PX,IFDEF[#1!,#1!,#1]];
M[DPS,ADD[PX[#1],PX[#2],PX[#3],PX[#4],PX[#5],PX[#6],PX[#7],PX[#8]]];
M[SP,IFG[#0,11,TMARGS[#1],SET[#1!,DPS[#2,#3,#4,#5,#6,#7,#8,#9]]]];
M[NSP,IFG[#0,11,TMARGS[#1],SET[#1!,NOT[DPS[#2,#3,#4,#5,#6,#7,#8,#9]]]]];


M[C,IFE[AND[#3#2,177760],0,
  SET[!T1,ADD[LSHIFT[#2,4],RSHIFT[#1,10]]] SET[!T2,AND[#1,377]]
  IFE[!T1,0,BSEL[4]FF256[!T2],
    IFE[!T2,0,BSEL[6]FF256[!T1],
      IFE[!T1,377,BSEL[5]FF256[!T2],
        IFE[!T2,377,BSEL[7]FF256[!T1],ER[Illegal.constant]]
      ]
    ]
  ],ER[Constant.too.big]]B
];

M[-C,SUB[0,#3#2#1]C];

M[MC,IFG[#0,11,TMARGS[#1],
  SP[#1,DPS[#2,#3,#4,#5,#6,#7,#8,#9]] M[#1,ADD[#1!]C]]];

M[NMC,IFG[#0,11,TMARGS[#1],
  SP[#1,NOT[DPS[#2,#3,#4,#5,#6,#7,#8,#9]]] M[#1,ADD[#1!]C]]];

M[S,SET[SCONS,#2#1] SC];

M[MSC,IFG[#0,5,TMARGS[#1],SP[#1,DPS[#2,#3,#4,#5]] M[#1,ADD[#1!]S]]];

%ALU stuff
%

%#1 = before, A, between,
#2 = after B,
#3 = ALUF value,
#4 = text to get A source selected
%
%*Arithmetic (slow) ALU ops use this one
M[SDEFOP,M[#1RB#2,(ALUF[#3]PD,#4,B_RB)]
	M[#1T#2,(ALUF[#3]PD,#4,B_T)]
	M[#1B#2,(ALUF[#3]PD,#4)]
	M[#1MD#2,(ALUF[#3]PD,#4,B_MD)]
	M[#1Q#2,(ALUF[#3]PD,#4,B_Q)]
];

*Logical (fast) ALU ops use this one
M[DEFOP,M[#1XB#2,(ALUF[#3]#5PD,#4)]
	SDEFOP[#1,#2,#3,#4,#5]
];

M[ALUOP,DEFOP[#1RB#2,#3,#4,A_RB]
	DEFOP[#1T#2,#3,#4,A_T]
	DEFOP[#1ID#2,#3,#4,A_ID]
	DEFOP[#1MD#2,#3,#4,A_MD]
	DEFOP[#1A#2,#3,#4]
	DEFOP[#1Q#2,#3,#4,A_Q]
	DEFOP[#1SC#2,#3,#4,A_SC]
]

*Operations of one arg which can use either A or B are defined by both
*"ABOPA" and "ABOPB".  They prefer B for RB, T, MD, and Q.
*#1 = before A
*#2 = after A
*#3 = ALUF value

M[ABOPA,M[#1T#2,#1(IFA[BSEL,A_T,B_T])#2]
	M[#1ID#2,#1(A_ID)#2]
	M[#1SC#2,#1(A_SC)#2]
	M[#1A#2,ALUF[#3]PD]
];

M[ABOPB,M[#1RB#2,#1(IFA[BSEL,A_,B_]RB)#2]
	M[#1MD#2,#1(IFA[BSEL,A_,B_]MD)#2]
	M[#1Q#2,#1(IFA[BSEL,A_,B_]Q)#2]
	M[#1B#2,ALUF[#3] PD]
	M[#1XB#2,ALUF[#3] PD]
];
%

M[BOP,M[#1B#2,ALUF[#3]PD]
	M[#1XB#2,ALUF[#3]PD]
	M[#1T#2,#1(B_T)#2]
	M[#1RB#2,#1(B_RB)#2]
	M[#1MD#2,#1(B_MD)#2]
	M[#1Q#2,#1(B_Q)#2]
];

M[AOP,	M[#1T#2,#1(A_T)#2]
	M[#1RB#2,#1(A_RB)#2]
	M[#1ID#2,#1(A_ID)#2]
	M[#1MD#2,#1(A_MD)#2]
	M[#1Q#2,#1(A_Q)#2]
	M[#1SC#2,#1(A_SC)#2]
	M[#1A#2,ALUF[#3]PD]
];

BOP[PD_,,0,25];	*B control in loc. 0
AOP[NOT,,16,1];	*NOT A control in loc. 16

%The various sources and destinations connected by "_" reduce to the
following source and destination classes:
%
N[?];	*Illegal as source or destination
N[RB];	*Feed A, B, or shifter
N[T];	*Feed A or B
N[MD];	*Feed R, T, A, or B
N[B];	*B
N[XB];	*External B
N[A];	*A
N[Q];	*Feeds B (BSEL) or A (FF64)
N[ID];	*Feed A (ASEL or FA with mem ops) or B
N[PD];	*ALU ops, _INPUT, ALUFMEM, POINTERS, CNT, SHC, or TIOA&STKP
N[SC];	*Small constants

*Destinations expecting small constant as source (also RBASE_B,
*MEMBASE_B, and CNT_B)
N[RBASE_]; N[CNT_]; N[MEMBASEX_]; N[MEMBASE_]; N[MEMBX_];

N[RB_];		N[T_];		N[B_];		N[PD_];		N[A_];
N[FETCH_];	N[STORE_];	N[MM_];

*Connection macros
M[B_B,B];	M[B_XB,XB];
M[MAPBUF_,B_];	M[DBUF_,B_];
M[A_A,A];	M[PD_PD,PD];


%The following macros fix up the LC field according to the R_ and T_
selections.  T_R_MD is a special case requiring LC[5] and TGETSMD function.
%
M[RERR,ER[Illegal.R_]];
M[RMD,SELECT[FVAL[LC],PF[LC,4],LC[5],RERR,LC[5]FF64[75],,,RERR,RERR]];
M[RPD,SELECT[FVAL[LC],PF[LC,6],LC[7],,LC[2],RERR,RERR,,]];

M[RB_MD,MD(RMD)];
M[RB_B,PD_B(RPD)];	M[RB_XB,PD_XB(RPD)];
M[RB_T,PD_T(RPD)];
M[RB_RB,PD_RB(RPD)];
M[RB_A,PD_A(RPD)];
M[RB_ID,PD_ID(RPD)];
M[RB_PD,PD(RPD)];
M[RB_Q,PD_Q(RPD)];
M[RB_SC,PD_SC(RPD)];

M[TERR,ER[Illegal.T_]];
M[TMD,SELECT[FVAL[LC],PF[LC,3],TERR,,,LC[5]FF64[75],TERR,LC[2],TERR]];
M[TPD,SELECT[FVAL[LC],PF[LC,1],,TERR,TERR,LC[5],,LC[7],]];

M[T_MD,MD(TMD)];
M[T_B,PD_B(TPD)];	M[T_XB,PD_XB(TPD)];
M[T_T,PD_T(TPD)];
M[T_RB,PD_RB(TPD)];
M[T_A,PD_A(TPD)];
M[T_ID,PD_ID(TPD)];
M[T_PD,PD(TPD)];
M[T_Q,PD_Q(TPD)];
M[T_SC,PD_SC(TPD)];

M[EMCHK,BLK[1]RSTK13[#1]ILLIO[Stack.op]];
M[UEMCHK,BLK[1]RSTK[#1]ILLIO[Stack.op]];

*No StkP=0 underflow check on read because pointer will go negative.
*If also writing STK, write macro will impose the StkP_0 underflow check.
M[STACK&-4,RB(EMCHK[4])];
M[STACK&-3,RB(EMCHK[5])];
M[STACK&-2,RB(EMCHK[6])];
M[STACK&-1,RB(EMCHK[7])];

*StkP=0 underflow check is required
M[STACK,RB(UEMCHK[10])];
M[STACK&+1,RB(UEMCHK[11])];
M[STACK&+2,RB(UEMCHK[12])];
M[STACK&+3,RB(UEMCHK[13])];

*These modify StkP after writing, so no check for StkP_0 required
M[STACK&-4_,RB(EMCHK[4])];
M[STACK&-3_,RB(EMCHK[5])];
M[STACK&-2_,RB_(EMCHK[6])];
M[STACK&-1_,RB_(EMCHK[7])];
M[STACK&+1_,RB_(EMCHK[1])];
M[STACK&+2_,RB_(EMCHK[2])];
M[STACK&+3_,RB_(EMCHK[3])];

*These modify StkP before writing, so must check for StkP_0 when
*decrementing StkP and must use ModStkPBeforeW function.
M[STACK-4_,RB_(UEMCHK[14],FF64[27])];
M[STACK-3_,RB_(UEMCHK[15],FF64[27])];
M[STACK-2_,RB_(UEMCHK[16],FF64[27])];
M[STACK-1_,RB_(UEMCHK[17],FF64[27])];
M[STACK_,RB_(UEMCHK[10])];

M[STACK+1_,RB_(EMCHK[1],FF64[27])];
M[STACK+2_,RB_(EMCHK[2],FF64[27])];
M[STACK+3_,RB_(EMCHK[3],FF64[27])];

*For STKP change without reference
M[STKP-4,?(EMCHK[4])];
M[STKP-3,?(EMCHK[5])];
M[STKP-2,?(EMCHK[6])];
M[STKP-1,?(EMCHK[7])];
M[STKP+1,?(EMCHK[1])];
M[STKP+2,?(EMCHK[2])];
M[STKP+3,?(EMCHK[3])];

%Block
%
M[BLOCK,ILLEM[BLOCK]BLK[1]];

%Shifter stuff:
Result of a 0-masking Shift is
	[(ALU) & NOT (LMask U RMask)].
Result of an Md-masking Shift is
	[((ALU) & NOT (LMask U RMask))U(MD & (LMask U RMask)].
For these normally ALU_A_Shifter.  The Shifter output is complemented,
so normally the "NOT A" ALU operation is used.

Compound shift expressions of the forms:
  LSH[X,shiftcount,Y]	RSH[X,shiftcount,Y]
  LDF[X,size,pos,Y]	DPF[X,size,pos,Y]
  RCY[U,V,cyclecount]	LCY[U,V,cyclecount]
where X may be an RM address or T, shiftcount an integer in the range 0 to
17, Y either MD or 0 (defaulted to 0 if omitted), U and V are an RM address
and T in either order.
%
M[DOSF,(ASEL[7]BSEL[#1] PD,IFA[FF,(FFT),F1[#2] F2[#3]])];

M[DOLDF,(DOSF[IFSE[#1,T,7,4],SUB[20,#2],AND[17,SUB[20,#3]]],#1)];
M[DORSH,(DOSF[IFSE[#1,T,7,4],#2,AND[17,SUB[20,#2]]],#1)];
M[DODPF,(DOSF[IFSE[#1,T,7,4],SUB[20,#2,#3],#3],#1)];
M[DOLCY,IFSE[#1,T,
  (IFSE[#2,T,DOSF[7,0,#3],(DOSF[6,0,#3],#2)]),
  (IFSE[#2,T,DOSF[5,0,#3],(DOSF[4,0,#3],#2)],#1)
]];

*RCY reverses args of left cycle unless count = 0
M[RCY,ALUF[0] IFE[#3,0,DOLCY[#1,#2,0],DOLCY[#2,#1,SUB[20,#3]]]];
M[LCY,ALUF[0] DOLCY[#1,#2,#3]];
M[RSH,ALUF[IFSE[#3,MD,12,2]] DORSH[#1,#2]];
M[LDF,ALUF[IFSE[#4,MD,12,2]] DOLDF[#1,#2,#3]];
M[LSH,ALUF[IFSE[#3,MD,14,4]] (DOSF[IFSE[#1,T,7,4],0,#2],#1)];
M[DPF,ALUF[IFSE[#4,MD,16,6]] DODPF[#1,#2,#3]];

M[XRCY,ALUF[1] IFE[#3,0,DOLCY[#1,#2,0],DOLCY[#2,#1,SUB[20,#3]]]];
M[XLCY,ALUF[1] DOLCY[#1,#2,#3]];
M[XRSH,ALUF[IFSE[#3,MD,13,3]] DORSH[#1,#2]];
M[XLDF,ALUF[IFSE[#4,MD,13,3]] DOLDF[#1,#2,#3]];
M[XLSH,ALUF[IFSE[#3,MD,15,5]] (DOSF[IFSE[#1,T,7,4],0,#2],#1)];
M[XDPF,ALUF[IFSE[#4,MD,17,7]] DODPF[#1,#2,#3]];

*Shifter ops assembled as ALU outputs
M[SHFTOP,(ALUF[#1] ASEL[7] PD, #2)];

M[SHIFTNOMASK,SHFTOP[0,#1]];
M[SHIFTLMASK,SHFTOP[2,#1]];
M[SHIFTRMASK,SHFTOP[4,#1]];
M[SHIFTBOTHMASKS,SHFTOP[6,#1]];
M[SHMDNOMASK,SHFTOP[10,#1]];	*Pretty useless--same as SHIFTNOMASK
M[SHMDLMASK,SHFTOP[12,#1]];
M[SHMDRMASK,SHFTOP[14,#1]];
M[SHMDBOTHMASKS,SHFTOP[16,#1]];

M[XSHIFTNOMASK,SHFTOP[1,#1]];
M[XSHIFTLMASK,SHFTOP[3,#1]];
M[XSHIFTRMASK,SHFTOP[5,#1]];
M[XSHIFTBOTHMASKS,SHFTOP[7,#1]];
M[XSHMDNOMASK,SHFTOP[11,#1]];
M[XSHMDLMASK,SHFTOP[13,#1]];
M[XSHMDRMASK,SHFTOP[15,#1]];
M[XSHMDBOTHMASKS,SHFTOP[17,#1]];

%Stuff for ASEL field
%
M[A_RB,IFE[FVAL[ASEL],7,FF64[20],ASEL[4]] A];
M[A_ID,ASEL[5] ILLIO[ID] A];
M[A_T,IFE[FVAL[ASEL],7,FF64[21],ASEL[6]] A];
*ASEL=7 is shifts, defined earlier
M[A_MD,FF64[22] A];
M[A_Q,FF64[23] A];
M[A_SC,IFG[20,SCONS,FF64[SCONS],ER[Illegal.A_SC]] A];

M[PRISRC,IFE[FVAL[BSEL0],1,,IFA[FA,(FAT),PF[FA,3]]] A];
M[SECSRC,IFA[FA,(FAT),FA[#1]]];
M[SREF0,ASEL[0] IFA[FA,(FAT),FA[#1]] MM_];
M[SREF1,ASEL[1] IFA[FA,(FAT),FA[#1]] MM_];

*Illegal use of an FF > 77 to the left of a Fetch_/Store_ with
*RM/T as source is not detected as an error.
M[FETCH_RB,ASEL[1] PRISRC];
M[FETCH_T,ASEL[3] PRISRC];
M[FETCH_MD,ASEL[3] SECSRC[0] A];
M[FETCH_ID,ASEL[3] SECSRC[1] A];
M[FETCH_Q,ASEL[3] SECSRC[2] A];
M[FETCH_SC,ASEL[1] SECSRC[3] A_SC];

M[STORE_RB,ASEL[0] PRISRC];
M[STORE_T,ASEL[2] PRISRC];
M[STORE_MD,ASEL[2] SECSRC[0] A];
M[STORE_ID,ASEL[2] SECSRC[1] A];
M[STORE_Q,ASEL[2] SECSRC[2] A];
M[STORE_SC,ASEL[0] SECSRC[3] A_SC];

M[PREFETCH_,SREF0[0]];
M[MAP_,ILLIO[MAP_]SREF0[1]];
*MAP_ with READMAP FF decode (only legal source is RM)
M[RMAP_,ILLIO[RMAP_] ASEL[0] FF256[131] MM_];
M[IOFETCH_,ILLEM[IOFETCH_]SREF0[1]];
M[LONGFETCH_,SREF0[2]];
M[DUMMYREF_,SREF1[0]];
M[FLUSH_,ILLIO[FLUSH_]SREF1[1]];
M[IOSTORE_,ILLEM[IOSTORE_]SREF1[1]];
M[IFETCH_,ILLIO[IFETCH_]SREF1[2]];

M[MM_A,A];
M[MM_RB,A];
M[MM_T,FF64[21] A];
M[MM_MD,FF64[22] A];
M[MM_Q,FF64[23] A];
M[MM_SC,A_SC];


%Stuff for BSEL
%
M[B_MD,BSEL[0] B];
M[B_RB,BSEL[1] B];
M[B_T,BSEL[2] B];
M[B_Q,IFG[FVAL[BSEL],3,IFE[FVAL[ASEL],7,,ER[BSEL.already.set]],BSEL[3]] B];
*BSEL = 4,5,6,7 are (0,,FF), (377,FF), (FF,,0), and (FF,,377)

%Stuff for 100 functions and branch conditions:
%

*FF= 0 TO 17 are A_small constants, given earlier
*FF=20 to 23 select A sources, defined with ASEL stuff

M[XORCARRY,FF64[24] ?];
M[XORSAVEDCARRY,FF64[25]?];
M[CARRY20,FF64[26] ?];
*27 is MODSTKPBEFOREW, used implicitly
*30 undefined
*31 is READMAP, used implicitly in RMAP_
M[INPUT,FF64[32] PD];
M[INPUTNOPE,FF64[33] PD];
M[RISID,ILLIO[RISID]FF64[34] ?];
M[TISID,ILLIO[TISID]FF64[35] ?];
M[OUTPUT_,FF64[36] B_];
M[FLIPMEMBASE,FF64[37]?];

*40 to 57 supply RSTK for write, used implicitly
*60 to 67 are fast branches defined with control

M[BIGBDISPATCH_,FF64[70] B_];	*256-way B dispatch
M[BDISPATCH_,FF64[71] B_];	*8-way B dispatch
M[MULTIPLY,FF64[72] ?];
M[Q_,FFBSEL[73,3] B_];
*74 undefined
*75 is TGETSMD, used implicitly
M[FREEZEBC,FF64[76]?];
M[NOFF,FF[77] ?];	*No operation, used only for IM default


M[PCF_,FF256[100] B_];	*PCF_B and start IFU
M[IFUTEST_,FF256[101] B_];
M[IFUTICK,FF256[102] ?];
M[RESCHEDULENOW,FF256[103] ?];
*104 undefined
M[MEMBASE_B,FF256[105] B];	M[MEMBASE_RB,MEMBASE_(B_RB)];
  M[MEMBASE_T,MEMBASE_(B_T)];	M[MEMBASE_MD,MEMBASE_(B_MD)];
  M[MEMBASE_Q,MEMBASE_(B_Q)];
M[RBASE_B,FF256[106] B];	M[RBASE_RB,RBASE_(B_RB)];
  M[RBASE_T,RBASE_(B_T)];	M[RBASE_MD,RBASE_(B_MD)];
  M[RBASE_Q,RBASE_(B_Q)];
M[POINTERS_,FF256[107] B_];

*110-117 undefined

*120-121 undefined Mar sources
M[CFLAGS_,FF256[122] A_];	*Source stable on Mar during preceding cycle
M[BRLO_,FF256[123] A_];
M[BRHI_,FF256[124] A_];
M[LOADTESTSYNDROME,FF256[125] ?];	*Loads from DBuf, ties up Mar
M[LOADMCR,(FF256[126] A_#1,B_#2)];	*Some bits from Mar, some from B
M[PROCSRN_,FF256[127] B_];

M[INSSETOREVENT_,FF256[130] B_];	M[MOS_,FF256[130] B_];
M[EVENTCNTB_,FF256[131] B_];		M[GENOUT_,FF256[131] B_];
M[RESCHEDULE,FF256[132] ?];
M[NORESCHEDULE,FF256[133] ?];

M[IFUMRH_,FF256[134] B_];
M[IFUMLH_,FF256[135] B_];
M[IFURESET,FF256[136] ?];
M[BRKINS_,FF256[137] B_];	*BRKINS_B[0:7] & set BRKPENDING

M[USEDMD,FF256[140] ?];
M[MIDASSTROBE_,FF256[141] B_];
M[TASKINGOFF,FF256[142] ?];
M[TASKINGON,FF256[143] ?];
M[STKP_,FF256[144] B_];

M[RESTORESTKP,FF256[145] ?];
M[CNT_B,FF256[146] B];	M[CNT_RB,CNT_(B_RB)];
  M[CNT_T,CNT_(B_T)];	M[CNT_MD,CNT_(B_MD)]; M[CNT_Q,CNT_(B_Q)];
M[LINK_,FF256[147] B_];

M[Q LSH 1,FF256[150] ?];
M[Q RSH 1, FF256[151] ?];
M[TIOA_,FF256[152] B_];
*153 undefined
M[HOLD&TASKSIM_,FF256[154] B_];
M[WF_,FF256[155] A_];
M[RF_,FF256[156] A_];
M[SHC_,FF256[157] B_];

*External B
M[XBOK,IFA[BSEL,ER[Multiple.B.sources],FF256[#1]]];

*From memory
M[FAULTINFO',XBOK[160] XB];
M[PIPE0,XBOK[161] XB];	M[VAHI,XBOK[161] XB];
M[PIPE1,XBOK[162] XB];	M[VALO,XBOK[162] XB];
M[PIPE2',XBOK[163] XB];
M[PIPE3',XBOK[164] XB];	M[MAP',XBOK[164] XB];
M[PIPE4',XBOK[165] XB];	M[ERRORS',XBOK[165] XB];
M[CONFIG',XBOK[166] XB];
M[PIPE5,XBOK[167] XB];		M[PREF,XBOK[167] XB];

*From IFU
M[PCX',XBOK[170] B];
M[EVENTCNTA',XBOK[171] XB];
M[IFUMRH',XBOK[172] XB];
M[IFUMLH',XBOK[173] XB];
M[EVENTCNTB',XBOK[174] XB];

M[DBUF,XBOK[175] XB];	*From memory

*From Control
M[RWCPREG,XBOK[176] XB];
M[LINK,XBOK[177] XB];
  M[CPREG,XBOK[177] XB]; *Synonym for LINK

%Stuff for small constant functions
%
M[SCFN,IFG[#1,SCONS,FF256[ADD[#2,SCONS]],ER[Illegal.arg.for.#3]] ?];

M[RBASE_SC,SCFN[20,200,RBASE_]];
*220-237 are change-RBase-for-write, unused by Midas
M[TIOA,SCFN[10,240,TIOA]];
M[MEMBASEX_SC,SCFN[4,250,MEMBASEX_]];
M[MEMBX_SC,SCFN[4,254,MEMBX_]];

*260-261 undefined
N[ALUFMRW_]; M[ALUFMRW_B,FF256[262] PD];
  M[ALUFMRW_MD,ALUFMRW_(B_MD)]; M[ALUFMRW_T,ALUFMRW_(B_T)];
  M[ALUFMRW_RB,ALUFMRW_(B_RB)]; M[ALUFMRW_Q,ALUFMRW_(B_Q)];
M[ALUFMEM,FF256[263] PD];
M[CNT,FF256[264] PD];
M[POINTERS,FF256[265] PD];
M[TIOA&STKP,FF256[266] PD];
M[SHC,FF256[267] PD];

M[PD RSH 1,FF256[270] PD];	*PD[0]_0
  M[T RSH 1,FF256[270] PD_T];
  M[RB RSH 1,FF256[270] PD_RB];
  M[A RSH 1,FF256[270] PD_A];
  M[ID RSH 1,FF256[270] PD_(A_ID)];
  M[B RSH 1,FF256[270] PD_B];
  M[MD RSH 1,FF256[270] PD_MD];
  *Q RSH 1 through the ALU has to be written (B_Q) LSH 1

M[PD RCY 1,FF256[271] PD];	*PD[0]_ALU[17]
  M[T RCY 1,FF256[271] PD_T];
  M[RB RCY 1,FF256[271] PD_RB];
  M[A RCY 1,FF256[271] PD_A];
  M[ID RCY 1,FF256[271] PD_(A_ID)];
  M[B RCY 1,FF256[271] PD_B];
  M[MD RCY 1,FF256[271] PD_MD];
  M[Q RCY 1,FF256[271] PD_(B_Q)];

M[PD BRSH 1,FF256[272] PD];	*PD[0]_ALUcarry
  M[T BRSH 1,FF256[272] PD_T];
  M[RB BRSH 1,FF256[272] PD_RB];
  M[A BRSH 1,FF256[272] PD_A];
  M[ID BRSH 1,FF256[272] PD_(A_ID)];
  M[B BRSH 1,FF256[272] PD_B];
  M[MD BRSH 1,FF256[272] PD_MD];
  M[Q BRSH 1,FF256[272] PD_(B_Q)];

M[PD ARSH 1,FF256[273] PD];	*PD[0] unchanged
  M[T ARSH 1,FF256[273] PD_T];
  M[RB ARSH 1,FF256[273] PD_RB];
  M[A ARSH 1,FF256[273] PD_A];
  M[ID ARSH 1,FF256[273] PD_(A_ID)];
  M[B ARSH 1,FF256[273] PD_B];
  M[MD ARSH 1,FF256[273] PD_MD];
  M[Q ARSH 1,FF256[273] PD_(B_Q)];

M[PD LSH 1,FF256[274] PD];	*PD[17]_0
  M[T LSH 1,FF256[274] PD_T];
  M[RB LSH 1,FF256[274] PD_RB];
  M[A LSH 1,FF256[274] PD_A];
  M[ID LSH 1,FF256[274] PD_(A_ID)];
  M[B LSH 1,FF256[274] PD_B];
  M[MD LSH 1,FF256[274] PD_MD];
  *Q LSH 1 through the ALU has to be written as (B_Q) LSH 1

M[PD LCY 1,FF256[275] PD];	*PD[17]_ALU[0]
  M[T LCY 1,FF256[275] PD_T];
  M[RB LCY 1,FF256[275] PD_RB];
  M[A LCY 1,FF256[275] PD_A];
  M[ID LCY 1,FF256[275] PD_(A_ID)];
  M[B LCY 1,FF256[275] PD_B];
  M[MD LCY 1,FF256[275] PD_MD];
  M[Q LCY 1,FF256[275] PD_(B_Q)];

M[DIVIDE,FF256[276] ?];		*Q[15]_ALU carry
M[CDIVIDE,FF256[277] ?];	*Q[15]_ALU carry'

M[MEMBASE_SC,SCFN[40,300,MEMBASE_]];
M[CNT_SC,IFE[SCONS,20,FF256[340] ?,IFE[SCONS,0,ER[Illegal.CNT_],
  SCFN[20,340,CNT_]]]];
M[NOTIFY,FF256[ADD[360,PX[#1]]]];

%Control stuff:
%

%Branch conditions are irrelevant ?
*Use FBC BC if available.
M[BRC,IFA[FBC,JCN[#2],FBC[#1]]]; **Doesn't work**

*REGULAR BC'S
M[~ALU=0,BRC[60,0]];
M[~ALU<0,BRC[61,1]];
M[~CARRY',BRC[62,2]];
M[~CNT=0&-1,BRC[63,3]];
M[~R<0,BRC[64,4]];
M[~R ODD,BRC[65,5]];
M[~IOATTEN',ILLEM[IOATTEN']BRC[66,6]];
M[~RESCHEDULE,ILLIO[RESCHEDULE]BRC[66,6]];
M[~OVERFLOW,FF64[67]];
M[~,];
%

M[RETURN,JCN[107]?];
M[LOCBR,JCN[ADD[200,#1]]?];
M[LONGBR,JCN[AND[#1,17]] FF[RSHIFT[#1,4]]?];
M[GCALL,JCN[ADD[300,RSHIFT[#1,6]]] ?];
M[IFUJUMP,JCN[ADD[47,LSHIFT[#1,3]]] ?];

%IM read/write to/from LINK.
%
M[IMLHR0POK_,RSTK13[3] JCN[177] B_];
M[IMLHR0PBAD_,RSTK13[7] JCN[177] B_];
M[IMLHR0'POK_,RSTK13[1] JCN[177] B_];
M[IMLHR0'PBAD_,RSTK13[5] JCN[177] B_];
M[IMRHBPOK_,RSTK13[2] JCN[177] B_];
M[IMRHBPBAD_,RSTK13[6] JCN[177] B_];
M[IMRHB'POK_,RSTK13[0] JCN[177] B_];
M[IMRHB'PBAD_,RSTK13[4] JCN[177] B_];

M[READIM,JCN[167] RSTK23[#1] ?];


%TPC read/write from LINK, address from B[14:17]
%
M[LDTPC_,JCN[157] B_];
M[RDTPC_,JCN[147] B_];


DEFAULT[LDR,(NOFF, PD_B, ASEL[4] BSEL[1] LC[0] RSTK[0] LOCBR[1])];