*----------------------------------------------------------------------------
Title[EtherDefs.Mc...December 6, 1980  8:05 PM...Taft];
* Dorado Ethernet definitions
*----------------------------------------------------------------------------


*----------------------------------------------------------------------------
* Hardware definitions
*----------------------------------------------------------------------------

* TIOA assignments
Device[EData, 15];	* Input and output data
Device[EControl, 16];	* Control and status

* Receiver status bits in end-of-packet word (EData).  Assignments are
* Alto-compatible (except RxCollision, which the Alto doesn't have)
MC[RxCollision, 200];	* Receiver-detected collision
MC[RxDataLate, 40];	* Input data late
MC[RxCRCError, 10];	* CRC bad
MC[EInCmd, 4];		* Input command issued	** Not in hardware:	   **
MC[EOutCmd, 2];		* Output command issued	** for Alto emulation only **
MC[RxIncTrans, 1];	* Incorrectly terminated packet

* Transmitter and general interface status bits (EControl)
* Left byte is Ethernet host address.
MC[RxOn, 200];		* Receiver on
MC[TxOn, 100];		* Transmitter on
MC[LoopBack, 40];	* Loop-back mode on
MC[TxCollision, 20];	* Transmitter-detected collision
MC[NoWakeups, 10];	* Task wakeups enabled if 0, disabled if 1
MC[TxDataLate, 4];	* Output data late
MC[SingleStep, 2];	* Single-step mode on
MC[TxFifoPE, 1];	* Transmitter-detected IOB or Fifo parity error

* Status masks useful for Alto emulation
MC[EISMask, RxCollision, RxDataLate, RxCRCError, RxIncTrans]; * Input status
MC[EOSMask, TxDataLate, TxCollision, TxFifoPE]; * Output status
MC[ECmdBits, EInCmd, EOutCmd]; * Command bits

* Control bits (EControl) -- Transmitter control (bits 0-3)
MC[TxCmdEnbl, 007777];	* Bit 0 = 0 enables decoding of output commands
MC[STxOn, 40000];	* Turn on output if 1, off if 0
MC[STxEOP, 20000];	* Send end of packet if 1
MC[STxCntDown, 10000];	* Generate countdown wakeup if 1

MC[TurnOffTx, TxCmdEnbl];
MC[TurnOnTx, TxCmdEnbl, STxOn];
MC[CountDown, TxCmdEnbl, STxOn, STxCntDown];
MC[SendEOP, TxCmdEnbl, STxOn, STxEOP];

* Control bits (EControl) -- Receiver control (bits 4-7)
MC[RxCmdEnbl, 170377];	* Bit 4 = 0 enables decoding of input commands
MC[SRxOn, 2000];	* Turn on input if 1, off if 0
MC[SRxBOP', 1000];	* Wait for beginning of next packet if 0

MC[TurnOnRx, RxCmdEnbl, SRxOn, SRxBOP'];
MC[TurnOffRx, RxCmdEnbl];
MC[WaitForBOP, RxCmdEnbl, SRxOn];

* Control bits (EControl) -- Test control (bits 8-15)
MC[TestCmdEnbl, 177400]; * Bit 8 = 0 enables decoding of test commands
MC[SLoopBack, 100];	* Turn on loop-back mode if 1, off if 0
MC[SSingleStep, 40];	* Turn on single-step mode if 1, off if 0
MC[SNoWakeups, 20];	* Enable task wakeups if 0, disable if 1
MC[SEtherClk, 10];	* Generate one EtherClk if 1 (SSingleStep must be 1)
MC[SCollision', 4];	* Cause a collision indication if 0
MC[SPDInput, 2];	* Set flop that ORs a 1 into the received data if 1 
MC[SReportCollisions, 1]; * Report receiver detected collisions

*----------------------------------------------------------------------------
* R-registers
*----------------------------------------------------------------------------

* In the Alto emulation, we could assume that the input and output tasks
* never run at the same time and can share R-registers, since the emulated
* Alto interface is half-duplex.  However, the PrincOps version of the
* microcode runs input and output tasks independently, so separate R-registers
* are required.

* The input and output R-registers have to be in separate banks because
* the two tasks share task-independent subroutines that need to reference
* task-specific registers and temporaries.  However, we don't need very
* many R-registers in either bank, so these banks may be shared with
* other tasks.

SetRMRegion[EIRegs];	* Used by input task -- first 3 must parallel EORegs
:If[Not[AltoMode]];	******** PrincOps version ********
	RVN[EICB];	* Pointer to IOCB being worked on
:EndIf;			**********************************
	RVN[EIPtr];	* Input main loop pointer/count
	RVN[EITemp1];	* Input temporaries
	RVN[EITemp2];

SetRMRegion[EORegs];	* Used by output task -- first 3 must parallel EIRegs
:If[Not[AltoMode]];	******** PrincOps version ********
	RVN[EOCB];	* Pointer to IOCB being worked on
:EndIf;			**********************************
	RVN[EOPtr];	* Output main loop pointer/count
	RVN[EOTemp1];	* Output temporary
:If[AltoMode];		********** Alto version **********
	RVN[MinPktSpc];	* Minimum inter-packet spacing (units of 0.595 us)
:Else;			******** PrincOps version ********
	RVN[EOTemp2];	* Output temporary
:EndIf;			**********************************
	RVN[EOTime];	* Time at end of last packet successfully transmitted
	RVN[RNum];	* State for random number generator
	RVN[RConst];	* Constant (13849) for random number generator

* Region-independent R-register definitions
:If[Not[AltoMode]];	******** PrincOps version ********
RVRel[ExCB, And[IP[EICB], 17]];
:EndIf;			**********************************
RVRel[ExPtr, And[IP[EIPtr], 17]];
RVRel[ExTemp1, And[IP[EITemp1], 17]];

*----------------------------------------------------------------------------
* Memory base registers
*----------------------------------------------------------------------------

% -- Defined in ADefs.mc --
BR[EIBR, ?];		* Input base register
BR[EOBR, ?];		* Output base register
BR[ECBR, ?];		* Command base register  {EmuBrHi,,600} -- Alto only
%

:If[AltoMode];		********** Alto version **********
*----------------------------------------------------------------------------
* Control block addresses (for Alto emulation, relative to ECBR = 600)
*----------------------------------------------------------------------------

MSC[EPLoc, 0];		* Post location
MSC[EBLoc, 1];		* Interrupt bit mask
MSC[EELoc, 2];		* Ending word count
MSC[ELLoc, 3];		* Load mask
MSC[EICLoc, 4];		* Input count
MSC[EIPLoc, 5];		* Input pointer
MSC[EOCLoc, 6];		* Output count
MSC[EOPLoc, 7];		* Output pointer
MSC[EHLoc, 10];		* Host address

*----------------------------------------------------------------------------
* Microcode post codes (small integer in lh, ones in rh for XOR).
*----------------------------------------------------------------------------

MC[InDone, 377];	* Input done
MC[OutDone, 777];	* Output done
MC[InBufOverflow, 1377]; * Input buffer overflowed
MC[LoadOverflow, 1777];	* Load overflow
MC[CountZero, 2377];	* Word count zero in input or output command
MC[CmdAbort, 2777];	* Command aborted (by SIO)
:EndIf;			**********************************
(1552)