%
Page Numbers: Yes First Page: 1
Heading:
kernel2.mcSeptember 22, 1986 5:41 PM%
* INSERT[D1ALU.MC];
* TITLE[KERNEL2];
* INSERT[PREAMBLE.MC];
* Link test corrected by Frank Vest November 1, 1984 10:01 AM
* September 22, 1986 5:42 PM. Added noops after labels: AfterTioa and
* afterLink to avoid some confusion.
top level;
beginKernel2:
%
January 20, 1978 3:13 PM
%
%
TESTCONTENTS
cntRWread and write CNT
cntFFrwread and write CNT, load from FF
cntFcntest CNT=0&+1 fast branch
NotAtesttest alu op, NOT A
NotBtesttest alu op, NOT B
AandBtesttest alu op, A AND B
AorBtesttest alu op, A OR B
LINKRWread and write LINK
callTestglobal and local subroutine calls
QtestRWread and write Q, q lsh 1, q rsh 1
tioaTestload and read tioa from FF and from bmux
STKPtestRWread and write STKP, perform TIOA&STKP
rstkTest0write different RM address from one read
%
%
January 18, 1979 2:07 PM
Add tioaTest
%
* October 19, 1978 5:22 PM
%
TEST ALL THE BITS IN CNT: REMEMBER THAT CNT CAN BE LOADED FROM
BOTH B AND FF.
%
cntRW:
t ← cnt ← r0;* test loading cnt w/ 0
rscr ← cnt;
t ← t # (rscr);* t ← bits read from cnt # expected bits
skpif[ALU=0];
cntErr1:* t = bad bits, rscr = expected
error;* value of cnt
t ← cnt ← rm1;* test loading cnt w/ -1
rscr ← cnt;
t ← t # (rscr);* t ← bits read from cnt # expected bits
skpif[ALU=0];
cntErr2:* t = bad bits, rscr = expected
error;* value of cnt
t ← cnt ← r01;* test loading cnt w/ alternating 01
rscr ← cnt;
t ← t # (rscr);* t ← bits read from cnt # expected bits
skpif[ALU=0];
cntErr3:* t = bad bits, rscr = expected
error;* value of cnt
t ← cnt ← r10;* test loading cnt w/ alternating 10
rscr ← cnt;
t ← t # (rscr);* t ← bits read from cnt # expected bits
skpif[ALU=0];
cntErr4:* t = bad bits, rscr = expected
error;* value of cnt
* October 19, 1978 8:33 PM
cntFFrw:* TEST FF BITS FOR LOADING cnt
cnt←1S;
t←cnt;
t←t#(r1);* we set it to 1; check the val.
skpif[ALU=0];
cntFFrw1:* t=bad bits, 1=expected value
error;
cnt ← 2s;
t←cnt;
t ← t # (2c);
skpif[ALU=0];
cntFFrw2:* t = bad bits, 2 = expected value
error;
cnt ← 4s;
t ← cnt;
t ← t # (4c);
skpif[ALU=0];
cntFFrw3:* t = bad bits, 4 = expected
error;
cnt ← 10s;
t ← cnt;
t ← t # (10c);
skpif[ALU=0];
cntFFrw4:* t = bad bits, 10c = expected
error;
* October 30, 1978 1:54 PM
%
TEST cnt BY LOOPING FOR ALL VALUES OF cnt
AT POINTS TESTED, cnt AND rscr SHOULD BE EQUAL.
rscr←cnt←-1;-- test cnt for maximum iterations
WHILE cnt NE 0 DO
cnt←cnt-1;
IF rscr=0 THEN ERROR;
rscr←rscr-1;
ENDLOOP;
IF rscr NE 0 THEN ERROR
%
cntFcn:
t ← rscr←cm1;* t ← rscr ← initial value into cnt
cnt←t;* cnt ← initial value
cntFcnIL:
branch[cntFcnXitIL, cnt=0&-1], PD ← rscr;
skpUnless[ALU=0], PD←rscr;
cntFcnErr1:* value of rscr suggests we
error;* should have exited
branch[cntFcnIL], rscr←(rscr)-1;
cntFcnXitIL:
skpif[ALU=0];
cntFcnErr2:* rscr#0. value of rscr suggests we
error;* should not have exited.
cnt ← r0;* test cnt for initial value = zero
skpif[cnt=0&-1];
cntFcnErr3:* didn’t notice first value we loaded
error;* was zero
* August 31, 1977 12:48 PM
% Test not A, not B
%
NotAtest:
t←not(A←r0);
t←t#(rm1);
skpif[ALU=0];
error;* ~RO # RM
NotAb:
t←not(A←rm1);
t←t#(r0);
skpif[ALU=0];
error;* ~rm1 # r0
NotAc:
t←not(A←r01);
t←t#(r10);
skpif[ALU=0];
error;* ~r01 # r10
NotAd:
t←not(A←r10);
t←t#(r01);
skpif[ALU=0];
error;* ~r10 # r01
NotAe:
rscr←177776C;
t←not(A←r1);
t←t#(rscr);
skpif[ALU=0];
error;* ~r1 # 177776
NotBtest:
t←not(B←r0);
t←t#(rm1);
skpif[ALU=0];
error;* ~RO # RM
NotBTestb:
t←not(B←rm1);
t←t#(r0);
skpif[ALU=0];
error;* ~rm1 # r0
NotBTestc:
t←not(B←r01);
t←t#(r10);
skpif[ALU=0];
error;* ~r01 # r10
NotBTestd:
t←not(B←r10);
t←t#(r01);
skpif[ALU=0];
error;* ~r10 # r01
NotBTeste:
rscr←177776C;
t←not(B←r1);
t←t#(rscr);
skpif[ALU=0];
error;* ~r1 # 177776
%
Test A AND B
Assume a,b source dont matter. Ie.,
t←(b←t) and (a←r) =
t←(a←t) and (b←r)
%
AandBtest:
t←rm1;
t←tAND(rm1);
t←t#(rm1);
skpif[ALU=0];
error;* (rm1 AND rm1) #rm1
t←r01;
t←tAND(r10);
skpif[ALU=0];
error;* (r01 AND r10)
t←r0;
t←tAND(rm1);
skpif[ALU=0];
error;* r0 AND rm1
%
Test A orB.
Assume same as AandB test.
%
AorBtest:
t←rm1;
t←tOR(r0);
t←t#(rm1);
skpif[ALU=0];
error;* (rm1 OR r0) # rm1
AorBtestb:
t←r01;
t←tOR(r10);
t←t#(rm1);
skpif[ALU=0];
error;* (r01 OR r10) # rm1
AorBtestc:
t←rm1;
t←tOR(rm1);
t←t#(rm1);
skpif[ALU=0];
error;* (rm1 OR rm1) # rm1
AorBtestd:
t←r01;
t←tOR(r01);
t←t#(r01);
skpif[ALU=0];
error;* (r01 OR r01) # r01
AorBteste:
t←r10;
t←tOR(r10);
t←t#(r10);
skpif[ALU=0];
error;* (r10 OR r10) # r10
AorBtestf:
t←(r0)OR(r0);
t←t#(r0);
skpif[ALU=0];
error;* (r0 OR r0) # r0
* February 17, 1978 8:51 AM
%
LINK READ/WRITE TEST + MINOR TEST OF CALL
FOR I IN[0..7777B] DO
LINK←I;
CHECK←LINK;
CHECK ← BITAND[CHECK,7777B];
IF CHECK NE LINK THEN ERROR;
ENDLOOP;
minor test of LINK, call
%
linkRW:
rscr←7777C;* BEGIN W/ MAX LINK VALUE & COUNT DOWN
linkL:
link ← rscr;
t ← link;
t ← t and (77777C);* ISOLATE 15 BITS ’CAUSE OF DMUX DATA
t←t#(rscr);
skpif[alu=0];
linkErr1:
error;* LINK DOESN’T HAVE THE VALUE WE LOADED
rscr←(rscr)-1;
dblBranch[afterLink,linkL, alu<0];
afterLink:
noop;
* November 3, 1978 6:40 PM
%
TEST Q: READ AND WRITE
FOR I IN [0..177777B] DO
Q←I;
t←Q XOR I;
IF T #0 THEN error;
ENDLOOP;
then test q lsh 1, q rsh 1 w/ selected values
%
QtestRW:
rscr←r0;
QRWL:
Q←(rscr);
t←(A←rscr)#(B←Q);
skpif[ALU=0];
QrwErr:
error;
rscr←(rscr)+1;
dblBranch[.+1,QRWL,ALU=0];
* now check rsh1, lsh1
q ← r0;
q lsh 1;* q ← 0 lsh 1
PD ← q;
skpif[ALU=0];
qr0Lerr:* r0 lsh 1 should be zero
error;
q ← r01;
q lsh 1;* q ← r01 lsh 1
(q) # (r10);
skpif[alu=0];
qr10Lerr:* r10 lsh1 should be r01. (zero fill)
error;
q ← rm1;
q lsh 1;
t ← cm2;
(q) # t;
skpif[ALU=0];
qrm1Lerr:* -1 lsh1 w/ zero fill should be -2
error;
q ← rhigh1;
q lsh 1;* q ← 100000B lsh 1
PD ← q;
skpif[ALU=0];
qrhigh1Lerr:* rhigh1 (100000B) lsh1 w/ zero fill should
error;* zero
q ← r0;
q rsh 1;* zero rsh1 should be zero
PD ← q;
skpif[ALU=0];
qr0Rerr:
error;* zero rsh1 should be zero
q ← r10;
q rsh 1; * q ← r10 rsh 1
(q) # (r01);
skpif[ALU=0];
qr10Rerr:* r10 rsh 1 w/ zero fill
error;* should be r01
q ← rm1;
q rsh 1;* q ← -1 rsh 1;
t ← 77777c;
(q) # t;
skpif[ALU=0];
qrm1Rerr:* -1 rsh 1 w/ zero fill should be 77777B
error;
q ← rhigh1;
q rsh 1;* q ← 100000B rsh 1
t ← 40000C;
(q) # t;
skpif[ALU=0];
qrhigh1Rerr:* rhigh1 rsh1 should be 40000B
error;
* January 18, 1979 1:29 PM
%
tioaTest
Test the processor’s ability to read and write TIOA. Write TIOAk from both FF constants and from RM.
%
tioaTest:
t ← 377c;
cnt ← t;
rscr2← t-t;
tioaL:
tioa ← rscr2;* RSCR2 = value we load into Tioa
call[getTioa];* rtn Tioa, still left justified, in t
rscr ← (rscr2) # t;
skpif[ALU=0];
tioaErr1:* We wrote tioa w/ contents of rscr2, got
error;* back the value in t. Bad bits in rscr.
loopUntil[cnt=0&-1, tioaL], rscr2 ← (rscr2) + (b7);* increment rscr2
* Here are device ddeclarations to keep micro happy. We use them to set Tioa directly from FF.
device[dvc5, b13!]; device[dvc6, b14!]; device[dvc7, b15!];
mc[tioa.0thru4C, b0,b1,b2,b3,b4];
mc[tioa.mask, 177400];
tioa ← r0;* zero all the bis of tioa
tioa[dvc7];* should set tioa[5:7] to 1
call[getTioa];
rscr ← (t) # (b7);* only one bit should be set
skpif[ALU=0];
tiaErr2:* tioa should be 1, (= 1 lshift 8 = 400)
error;* t = value of tioa, rscr = bad bits.
tioa[dvc6];* should set tioa[5:7] to 2
call[getTioa];
rscr ← t # (b6);* tioa should be 2, (= 1 lshift 9 = 1000)
skpif[ALU=0];
tioaErr3:
error;* rscr = bad bits, t = tioa left justified
tioa[dvc5];* tioa should be 4 (= 1 lshift 10 = 2000)
call[getTioa];
rscr ← t # (b5);
skpif[ALU=0];
tioaErr4:
error;* rscr = bad bits, t = tioa left justified
tioa ← rm1;* all ones into tioa
tioa[dvc7];
call[getTioa];
rscr ← tioa.0thru4C;
rscr ← (rscr) or (b7);* only should have set tioa[5:7];
rscr ← t # (q←rscr);* q = expected value
skpif[ALU=0];
tioaErr5:
error;* t = tioa, left justified; rscr = bad bits, q = expected value
tioa[dvc6];
call[getTioa];* set tioa[5:7] to 2
rscr ← tioa.0thru4C;
rscr ← (rscr) or (b6);* only should have set tioa[5:7];
rscr ← t # (q←rscr);* q = expected value
skpif[ALU=0];
tioaErr6:* q = expected value
error;* t = tioa, left justified; rscr = bad bits
tioa[dvc5];
call[getTioa];* set tioa[5:7] to 4
rscr ← tioa.0thru4C;
rscr ← (rscr) or (b5);* only should have set tioa[5:7];
rscr ← t # (q←rscr);* q = expected value
skpif[ALU=0];
tioaErr7:* q = expected value
error;* t = tioa, left justified; rscr = bad bits
branch[afterTioa];
getTioa: subroutine;
t ← TIOA&STKP;
return, t ← t and (177400C);* isolate left byte
top level;
afterTioa:
noop;
* October 19, 1978 8:54 PM
%
TEST STKP: READ AND WRITE
FOR I IN[0..377B] DO
STKP←I;
t←TIOA&STKP[]
t←t and (stkpMask);
t←t XOR I;
IF T # 0 THEN error;
ENDLOOP;
%
STKPtestRW:
t←r0;
rscr←t;* rscr = values loaded into stackp
rscr2 ← t←377C;* MASK TO ISOLATE STACKP
cnt←t;* mask just happens to be count, too
stkpL:
STKP←rscr;* LOAD STKP FROM rscr
t ← (TIOA&STKP);
t←t AND (rscr2);* READ AND MASK THE VALUE
t←t#(rscr);
skpif[ALU=0];
stkpErr:
error;* error: DIDN’T READ WHAT WE LOADED
dblBranch[.+1,stkpL,CNT=0&-1],rscr←(rscr)+1;
* October 26, 1978 12:03 PM
%
rstkFFTest the FF operation that replaces rstk with a value from the FF field during rm Writing. Test each bitpath only.
%
rstkFF:
q ← rmx0;* save rmx0
rmx0 ← t-t;* background test rm location w/ zero
t ← rmx7 ← cm1;* KEEP -1 IN RMX7, AND T
rmx0 ← rmx7;* write into RM w/ rstk from FF field
t # (rmx0);* compare target RM w/ expected value
skpif[alu=0];
rstkFF0Err:* can’t write into rstk0 w/ ff
error;
rmx0 ← q;* restore old value
q ← rmx1;* save rmx1
rmx1 ← t-t;* background test rm location w/ zero
rmx1 ← rmx7;* write into RM w/ rstk from FF field
t # (rmx1);* compare target RM w/ expected value
skpif[ALU=0];
rstkFF1Err:* can’t write into rstk1 w/ ff
error;
rmx1 ← q;* restore old value
q ← rmx2;* save rmx2
rmx2 ← t-t;* background test rm location w/ zero
rmx2 ← rmx7;* write into RM w/ rstk from FF field
t # (rmx2);* compare target RM w/ expected value
skpif[ALU=0];
rstkFF2Err:* can’t write into rstk2 w/ ff
error;
rmx2 ← q;* restore old value
q ← rmx4;* save rmx4
rmx4 ← t-t;* background test rm location w/ zero
rmx4 ← rmx7;* write into RM w/ rstk from FF field
t # (rmx7);* compare target RM w/ expected value
skpif[ALU=0];
rstkFF4Err:* can’t write rstk4 w/ ff
error;
rmx4 ← q;* restore old value
q ← rmx10;* save rmx10
rmx10 ← t-t;* background test rm location w/ zero
rmx10 ← rmx7;* write into RM w/ rstk from FF field
t # (rmx10);* compare target RM w/ expected value
skpif[ALU=0];
rstkFF10Err:* can’t write rstk10 w/ ff
error;
rmx10 ← q;
* October 26, 1978 6:14 PM
%
rbaseFFtest the facility that changes the value of rbase when rm storing occurs.
%
* sibling[FoosBrotherInRegion5, 5, foo]* declare FoosBrotherInRegion5 as an RM
* location in rmRegion 5 with its rstk value the same as the one for foo. Eg., if foo is
* located at rm addr 17,,12 (rbase = 17, rstk = 12) then FoosBrotherInRegion5 is located
* at rm addr 5,,12
m[sibling,
rm[#1, add[lshift[#2,4], and[17,ip[#3]]]]
];
sibling[rb0rm0, 0, rmx0];sibling[rb1rm1, 1, rmx1];sibling[rb2rm2, 2, rmx2];
sibling[rb4rm4, 4, rmx4]; sibling[rb10rm10, 10, rmx10];
rbaseFF:
rbase ← rbase[defaultRegion];
q ← rmx0;* save current value for "source" rm
rb0rm0 ← t-t;* zero "destination" rm
rmx0 ← cm1;* t ← "source rm" ← -1
rb0rm0 ← rmx0;* "destin" rm (different rbase)← source rm
rbase ← 0s;* check the result. First fetch the value in
t ← rmx0, RBASE ← rbase[defaultRegion];* the destination rm, then compare it to
t # (rmx0);* the source rm. An error means we didn’t
skpif[ALU=0];
rbaseFF0Err:* succeed in writing rm with rbase←0 from
error;* ff field. t = real val, rmx0=expected val.
rmx0 ← q;* restore old value
q ← rmx1;* save current value for "source" rm
t ← rmx1 ← cm1;* t ← "source rm" ← -1
rb1rm1 ← t-t;* zero "destination" rm
rb1rm1 ← rmx1;* "destin" rm (different rbase)← source rm
RBASE ← 1s;* check the result. First fetch the value in
t ← rmx1, RBASE ← rbase[defaultRegion];* the destination rm, then compare it to
t # (rmx1);* the source rm. An error means we didn’t
skpif[ALU=0];
rbaseFF1Err:* succeed in writing rm with rbase←0 from
error;* ff field. t = real val, rmx0=expected val.
rmx1 ← q;* restore old value
q ← rmx2;* save current value for "source" rm
t ← rmx2 ← cm1;* t ← "source rm" ← -1
rb2rm2 ← t-t;* zero "destination" rm
rb2rm2 ← rmx2;* "destin" rm (different rbase)← source rm
RBASE ← 2s;* check the result. First fetch the value in
t ← rmx2, RBASE ← rbase[defaultRegion];* the destination rm, then compare it to
t # (rmx2);* the source rm. An error means we didn’t
skpif[ALU=0];
rbaseFF2Err:* succeed in writing rm with rbase←0 from
error;* ff field. t = real val, rmx0=expected val.
rmx2 ← q;* restore old value
q ← rmx4;* save current value for "source" rm
t ← rmx4 ← cm1;* t ← "source rm" ← -1
rb4rm4 ← t-t;* zero "destination" rm
rb4rm4 ← rmx4;* "destin" rm (different rbase)← source rm
RBASE ← 4s;* check the result. First fetch the value in
t ← rmx4, RBASE ← rbase[defaultRegion];* the destination rm, then compare it to
t # (rmx4);* the source rm. An error means we didn’t
skpif[ALU=0];
rbaseFF4Err:* succeed in writing rm with rbase←0 from
error;* ff field. t = real val, rmx0=expected val.
rmx4 ← q;* restore old value
q ← rmx10;* save current value for "source" rm
t ← rmx10 ← cm1;* t ← "source rm" ← -1
rb10rm10 ← t-t;* zero "destination" rm
rb10rm10 ← rmx10;
RBASE ← 10s;* check the result. First fetch the value in
t ← rmx10,RBASE ← rbase[defaultRegion];* the destination rm, then compare it to
t # (rmx10);* the source rm. An error means we didn’t
skpif[ALU=0];
rbaseFF10Err:* succeed in writing rm with rbase←0 from
error;* ff field. t = real val, rmx0=expected val.
%
Test RSTK destination function:
FOR I IN [0..7] DO
FOR J IN [0..7] DO
RBASE[I]←RBASE[J];
t←RBASE[I];
IF T#RBASE[J] THEN error;
ENDLOOP; ENDLOOP;
Of course, this code is "expanded" inline rather than in a loop
%
*FOR I IN [0..7] DO RBASE[0] ← RBASE[I]; (EXCEPT FOR ←RBASE[0])
rstkTest0:
rscr←3C;
rscr2←4C;
Q←r0;
t←r0←r1;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
error;
skpif[ALU=0];
error;
t←r0←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
rstkTest02:
error;
skpif[ALU=0];
error;
t←r0←r01;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
error;
skpif[ALU=0];
error;
t←r0←r10;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
rstkTest04:
error;
skpif[ALU=0];
error;
t←r0←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
error;
skpif[ALU=0];
error;
t←r0←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
rstkTest06:
error;
skpif[ALU=0];
error;
t←r0←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(r0);
error;
skpif[ALU=0];
error;
r0←Q;
*FOR I IN [0..7] DO RBASE[1] ← RBASE[I]; (EXCEPT FOR ←RBASE[1])
rstkTest1:
Q←r1;
t←r1←r0;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
error;
skpif[ALU=0];
error;
t←r1←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
rstkTest12:
error;
skpif[ALU=0];
error;
t←r1←r01;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
error;
skpif[ALU=0];
error;
t←r1←r10;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
rstkTest14:
error;
skpif[ALU=0];
error;
t←r1←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
error;
skpif[ALU=0];
error;
t←r1←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
rstkTest16:
error;
skpif[ALU=0];
error;
t←r1←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(r1);
error;
skpif[ALU=0];
error;
r1←Q;
*FOR I IN [0..7] DO RBASE[2] ← RBASE[I]; (EXCEPT FOR ←RBASE[2])
rstkTest2:
Q←rm1;
t←rm1←r0;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
error;
skpif[ALU=0];
error;
t←rm1←r1;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
rstkTest22:
error;
skpif[ALU=0];
error;
t←rm1←r01;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
error;
skpif[ALU=0];
error;
t←rm1←r10;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
rstkTest24:
error;
skpif[ALU=0];
error;
t←rm1←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
error;
skpif[ALU=0];
error;
t←rm1←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
rstkTest26:
error;
skpif[ALU=0];
error;
t←rm1←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(rm1);
error;
skpif[ALU=0];
error;
rm1←Q;
*FOR I IN [0..7] DO RBASE[3] ← RBASE[I]; (EXCEPT FOR ←RBASE[3])
rstkTest3:
Q←r01;
t←r01←r0;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
error;
skpif[ALU=0];
error;
t←r01←r1;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
rstkTest32:
error;
skpif[ALU=0];
error;
t←r01←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
error;
skpif[ALU=0];
error;
t←r01←r10;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
rstkTest34:
error;
skpif[ALU=0];
error;
t←r01←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
error;
skpif[ALU=0];
error;
t←r01←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
rstkTest36:
error;
skpif[ALU=0];
error;
t←r01←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(r01);
error;
skpif[ALU=0];
error;
r01←Q;
*FOR I IN [0..7] DO RBASE[4] ← RBASE[I]; (EXCEPT FOR ←RBASE[4])
rstkTest4:
Q←r10;
t←r10←r0;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
error;
skpif[ALU=0];
error;
t←r10←r1;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
rstkTest42:
error;
skpif[ALU=0];
error;
t←r10←r01;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
error;
skpif[ALU=0];
error;
t←r10←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
rstkTest44:
error;
skpif[ALU=0];
error;
t←r10←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
error;
skpif[ALU=0];
error;
t←r10←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
rstkTest46:
error;
skpif[ALU=0];
error;
t←r10←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(r10);
error;
skpif[ALU=0];
error;
r10←Q;
*FOR I IN [0..7] DO RBASE[5] ← RBASE[I]; (EXCEPT FOR ←RBASE[5])
rstkTest5:
Q←rhigh1;
t←rhigh1←r0;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
error;
skpif[ALU=0];
error;
t←rhigh1←r1;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
rstkTest52:
error;
skpif[ALU=0];
error;
t←rhigh1←r01;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
error;
skpif[ALU=0];
error;
t←rhigh1←r10;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
rstkTest54:
error;
skpif[ALU=0];
error;
t←rhigh1←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
error;
skpif[ALU=0];
error;
t←rhigh1←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
rstkTest56:
error;
skpif[ALU=0];
error;
t←rhigh1←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(rhigh1);
error;
skpif[ALU=0];
error;
rhigh1←Q;
*FOR I IN [0..7] DO RBASE[6] ← RBASE[I]; (EXCEPT FOR ←RBASE[6])
rstkTest6:
Q←rscr;
t←rscr←r0;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
error;
skpif[ALU=0];
error;
t←rscr←r1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
rstkTest62:
error;
skpif[ALU=0];
error;
t←rscr←r01;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
error;
skpif[ALU=0];
error;
t←rscr←r10;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
rstkTest64:
error;
skpif[ALU=0];
error;
t←rscr←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
error;
skpif[ALU=0];
error;
t←rscr←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
rstkTest66:
error;
skpif[ALU=0];
error;
t←rscr←rscr2;
t#(Q);
skpUnless[ALU=0], t←t#(rscr);
error;
skpif[ALU=0];
error;
rscr←Q;
*FOR I IN [0..7] DO RBASE[7] ← RBASE[I]; (EXCEPT FOR ←RBASE[7])
rstkTest7:
Q←rscr2;
t←rscr2←r0;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
error;
skpif[ALU=0];
error;
t←rscr2←r1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
rstkTest72:
error;
skpif[ALU=0];
error;
t←rscr2←r01;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
error;
skpif[ALU=0];
error;
t←rscr2←r10;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
rstkTest74:
error;
skpif[ALU=0];
error;
t←rscr2←rhigh1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
error;
skpif[ALU=0];
error;
t←rscr2←rscr;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
rstkTest76:
error;
skpif[ALU=0];
error;
t←rscr2←rm1;
t#(Q);
skpUnless[ALU=0], t←t#(rscr2);
error;
skpif[ALU=0];
error;
rscr2←Q;
goto[afterKernel2];