Title[RastDefs.mc...May 23, 1989 2:14:09 pm PDT...Rumph];Device[SelCmd, 320];Device[AddrCmd, 321];Device[DataCmd, 322];Device[TaskCmd, 323];TaskN[WT, 13];		* same as DWTTaskN[LT, 3];		* same as DHTSetRMRegion[LTRegion];RVN[LTSavedCnt];RVN[LTSavedQ];RVN[LTLineState];RVN[LTIndexToStore];RVN[LTMRBAddrHi];RVN[LTMRBAddrLo];RVN[LTNextSTBAddrHi];RVN[LTNextSTBAddrLo];RVN[LTSTBLines];RVN[LTFlags];RVN[LTStatus];RVN[LTScratch];RVN[LTCursorCtl];RVN[LTModeCtl];RVN[LTHalftoneCtl];RVN[LTSelCtl];SetRMRegion[RastRMForA];RVN[aAddress];RVN[aCount];RVN[aNextCount];RVN[aNextAddrLo];RVN[aNextAddrHi];RVN[aNextRCBAddrLo];RVN[aNextRCBAddrHi];RVN[aCCR];RVN[aLines];RVN[aStatus];RVN[aStatusToStore];RVN[aIndexIntoBuffer];RVN[aCCRTemp];RVN[aLineRepeatCount];RVN[aRCBLineRepeatCount];RVN[aWordsPerLine];SetRMRegion[RastRMForB];RVN[bAddress];RVN[bCount];RVN[bNextCount];RVN[bNextAddrLo];RVN[bNextAddrHi];RVN[bNextRCBAddrLo];RVN[bNextRCBAddrHi];RVN[bCCR];RVN[bLines];RVN[bStatus];RVN[bStatusToStore];RVN[bIndexIntoBuffer];RVN[bCCRTemp];RVN[bLineRepeatCount];RVN[bRCBLineRepeatCount];RVN[bWordsPerLine];SetRMRegion[RastRMForC];RVN[cAddress];RVN[cCount];RVN[cNextCount];RVN[cNextAddrLo];RVN[cNextAddrHi];RVN[cNextRCBAddrLo];RVN[cNextRCBAddrHi];RVN[cCCR];RVN[cLines];RVN[cStatus];RVN[cStatusToStore];RVN[cIndexIntoBuffer];RVN[cCCRTemp];RVN[cLineRepeatCount];RVN[cRCBLineRepeatCount];RVN[cWordsPerLine];SetRMRegion[RastRMForD];RVN[dAddress];RVN[dCount];RVN[dNextCount];RVN[dNextAddrLo];RVN[dNextAddrHi];RVN[dNextRCBAddrLo];RVN[dNextRCBAddrHi];RVN[dCCR];RVN[dLines];RVN[dStatus];RVN[dStatusToStore];RVN[dIndexIntoBuffer];RVN[dCCRTemp];RVN[dLineRepeatCount];RVN[dRCBLineRepeatCount];RVN[dWordsPerLine];MC[GoodSTBSeal, 177570];MC[GoodMRBSeal, 177574];MC[GoodRCBSeal, 177573];MC[WTBeginLineFlag, 100000];MC[LTStatus.badSTBSeal, 10000];MC[LTStatus.ABadWake, 4000];MC[LTStatus.ABadRCBSeal, 2000];MC[LTStatus.AFinishedRCB, 1000];MC[LTStatus.BBadWake, 400];MC[LTStatus.BBadRCBSeal, 200];MC[LTStatus.BFinishedRCB, 100];MC[LTStatus.CBadWake, 40];MC[LTStatus.CBadRCBSeal, 20];MC[LTStatus.CFinishedRCB, 10];MC[LTStatus.DBadWake, 4];MC[LTStatus.DBadRCBSeal, 2];MC[LTStatus.DFinishedRCB, 1];MC[protoBadRCBSeal, LTStatus.DBadRCBSeal];MC[protoFinishedRCB, LTStatus.DFinishedRCB];MC[AddressMask, 3];MC[NLCBTailNAddr, 10];MC[ChanWantsWT, 100000];MC[DontSwapBuffers, 40000];MC[ItemOnThisLine, 20000];MC[NoItemOnThisLine, 157777];MC[WTShutUp, 100000];MC[LTShutUp, 40000];MC[RastAllShutUp, WTShutUp, LTShutUp];MC[InitialCCR, 17000];MC[BadStatus, 77400];MC[RCBComplete, 1];MC[SetStoreStatus, 100000];MC[ClearStoreStatus, 77777];MC[ClearStateMask, 177770];MC[StateMask, 7];MC[InterruptMaskAddr, 14];MC[LTStatusAddr, 15];MC[NextRCBAddrAddr, 1];MC[HandshakeAddr, 6];MC[BufferIndexAddr, 13];MC[StatusAddr, 14];MC[CursorCtlAddr, 15];MC[AllFirstTime, 0];MC[FirstTime, 0];MC[NewRCB, 1];MC[NewLine, 2];MC[RepeatingLine, 3];MC[InactiveChannel, 4];MC[nChannels, 3];		* actually nChannels-1MC[AChannelRBase, 10];MC[AddressXOR, AChannelRBase, AddressMask];MC[nlcbExtra, 3];MC[STBCountNLCB, 1];MC[STBStateNLCB, 2];MC[nStates, 17];  Z  RastDefs.mcCopyright Ó 1986, 1987, 1988, 1989 by Xerox Corporation.  All rights reserved.Dave Rumph, May 23, 1989 2:14:22 pm PDTRaster controller hardware, RM and BR definitionsIO AddressesTask DefsLine Task RM definitionsA Channel RM definitionsB Channel RM definitionsC Channel RM definitionsD Channel RM definitionsConstants Êù  ˜ ™IcodešœN™NK™'—J˜ ˜9J™1—J˜ šÏb™J˜J˜J˜J˜—J˜ š	™	J˜J˜—J˜ š™J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜—J˜ š™J˜J˜J˜J˜J˜J˜J˜J˜J˜
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