Addr Title Use 0 L[0] Local Frame (indexed by MemBX) 1 G[0] Global Frame (indexed by MemBX) 2 SD System Dispatch table 3 PDA, RQBR Base of Process Data Area (also Ready Queue) 4 L[1] Local Frame (indexed by MemBX) 5 G[1] Global Frame (indexed by MemBX) 6 ZCTBR Pointer to ZCT 7 WPBR Cached version of ZCT.wp 10 L[2] Local Frame (indexed by MemBX) 11 G[2] Global Frame (indexed by MemBX) 12 13 BRforCPA Base for xfer and monitor entry stats 14 L[3] Local Frame (indexed by MemBX) 15 G[3] Global Frame (indexed by MemBX) 16 NSIBR 10MB Ethernet Input base register 17 NSOBR 10MB Ethernet Output base register 20 AChannelBR DispY A Channel BR for DWT 21 TChannelBR DispM BR for AWT 22 BBDstBR BitBlt Destination Base Register 23 BBSrcBR BitBlt Source Base Register 24 BChannelBR DispY B Channel BR for DWT 25 MapBitsBR VM "Vacant" Extra-Bit Array (in DMesaMiscOps.mc) 26 ScratchBR Emulator General Purpose Scratch (also RQBR) 27 PCHistBR Base of Histogram for PC Sampling 30 DiskBR Disk Task Base Register 31 IOBR IO Region (first 64K) Base Register 32 EIBR 3MB Ethernet Input Base Register 33 EOBR 3MB Ethernet Output Base Register 34 LPtr, MLBR Long Pointer, Monitor Lock Base Register 35 BR35, CVBR Condition Variable Base Register 36 MDS Alto and Mesa MDS Base Register 37 Code IFU Code BR ΌCedarBRAssignments.tioga Copyright c 1985 by Xerox Corporation. All rights reserved. Last modified by Rumph, June 28, 1985 10:49:54 am PDT Willie-Sue, May 23, 1986 10:36:10 am PDT Κ¨˜™Icodešœ Οmœ1™