MODEL 1: preamble.mcMay 18, 1981 1:29 PM%1%May 18, 1981 1:29 PMFix getRandom to use a new random number generatorFebruary 5, 1981 1:20 PMAdapt to current d1lang.mcSeptember 19, 1979 10:42 AMTry undoing zeroHold fix -- found a different bug that probably accounts for the behavior.September 18, 1979 5:55 PMTry to make zeroHold more reliable: apparently 3 in a row is not enough.June 17, 1979 5:11 PMChange holdValueLoc to accommodate ifu entry pointsApril 17, 1979 10:45 PMAdd sim.holdMask, sim.taskMask, sim.holdShift, sim.taskShift.January 25, 1979 11:05 AMChange simTaskLevel to 12B.January 18, 1979 5:10 PMAdd currentTaskNum.%TITLE[PREAMBLE];%NAMING CONVENTIONS:LABELS BEGIN W/ THE OPERATION BEING TESTED:Aplus1cntFcnaluLT0lsh => Left shiftrsh => Right shiftlcy => Left Cyclercy => Right CycleRegister Read/write tests are suffixed with RW:cntRWshcRWLOOP LABELS ARE SUFFIXED AS INNER (IL) AND OUTER(OL) LOOPS (L).cntFcnIL* INNER LOOPcntFcnOL* OUTER LOOPcntFcnXITIL* LABEL FOR EXITING INNERLOOPcntFcnXITOL* LABEL FOR EXITINGOUTER LOOPAplus1L* ONLY LOOP%RMREGION[DEFAULTREGION];rv[r0,0];rv[r1,1];rv[rm1,177777];rv[r01,52525];rv[r10,125252];rv[rhigh1,100000];rv[rscr,0];rv[rscr2,0];rv[rscr3,0];rv[rscr4,0];rv[stackPAddr, 0];rv[stackPTopBits, 0];rv[klink, 0];rv[hack0,0];rv[hack1, 0];rv[hack2,0];rvrel[rmx0, 0];rvrel[rmx1, 1];rvrel[rmx2, 2];rvrel[rmx3, 3];rvrel[rmx4, 4];rvrel[rmx5, 5];rvrel[rmx6, 6];rvrel[rmx7, 7];rvrel[rmx10, 10];* Constants from FFHfpX.2BN bq `_2 ]\ ZYZ WUH TyR3 QqO= NiL KaI HY F EQBI@+#?A#=#<8:9076(3 /#1#0-?#+3 #*3 #( ; '#%| ; # #"s3  cpqpq+pq pqpq+pq [pqpq+pq pqp q+p q Spq +  pqpq+pq Cpqpq+pq pqpq+pq  D^(MODEL 1: preamble.mcMay 18, 1981 1:29 PM%2nsp[PNB0,100000];nsp[PNB1,40000];nsp[PNB2,20000];nsp[PNB3,10000];nsp[PNB4,4000];nsp[PNB5,2000];nsp[PNB6,1000];nsp[PNB7,400];nsp[PNB8,200];nsp[PNB9,100];nsp[PNB10,40];nsp[PNB11,20];nsp[PNB12,10];nsp[PNB13,4];nsp[PNB14,2];nsp[PNB15,1];mc[B0,100000];mc[B1,40000];mc[B2,20000];mc[B3,10000];mc[B4,4000];mc[B5,2000];mc[B6,1000];mc[B7,400];mc[B8,200];mc[B9,100];mc[B10,40];mc[B11,20];mc[B12,10];mc[B13,4];mc[B14,2];mc[B15,1];mc[NB0,PNB0];mc[NB1,PNB1];mc[NB2,PNB2];mc[NB3,PNB3];mc[NB4,PNB4];mc[NB5,PNB5];mc[NB6,PNB6];mc[NB7,PNB7];mc[NB8,PNB8];mc[NB9,PNB9];mc[NB10,PNB10];mc[NB11,PNB11];mc[NB12,PNB12];mc[NB13,PNB13];mc[NB14,PNB14];mc[NB15,PNB15];mc[CM1,177777];mc[C77400,77400]; mc[C377,377];mc[CM2,-2];mc[getIMmask, 377];* isolate IM data after getIm[]!m[noop, BRANCH[.+1]];m[skip, BRANCH[.+2]];m[error, ILC[(BRANCH[ERR])]];m[skiperr, ILC[(BRANCH[.+2])] ILC[(BRANCH[ERR])]];m[skpif, BRGO@[TS@] JMP@[.+2,#1,#2] ];m[skpUnless, BRGO@[TS@] DBL@[.+1,.+2,#1,#2] ];m[loopChk, BRGO@[TS@] DBL@[#1,.+1,#2,#3] ];m[loopUntil, BRGO@[TS@] DBL@[.+1,#2,#1,#3]];* if #1 then goto .+1 else goto #2m[loopWhile, BRGO@[TS@] DBL@[#2,.+1,#1,#3]];* if #1 then goto #2 else goto .+1HfpX.2BN bqpq `pqpq+pq _pqpq+pq ]pqpq+pq \pqpq+pq Zpqpq+pq Wpq Upqpq+pq Typqpqpq Rpqpqpq Qqpqpqpq Opqpqpq Lpq Kapqpq+pq Ipqpq+pq HYpqpq+pq Fpqpq+pq EQpqpq+pq BIpq pq pqpq @pq =pq <8pq :pq 90pq) 7pq 6(pq# 4pq" 3 pqC 1pqC /6Y8::MODEL 1: preamble.mcMay 18, 1981 1:29 PM%3* May 18, 1981 1:36 PMrmRegion[rm2ForKernelRtn];knowRbase[rm2ForKernelRtn];rv[chkSimulatingRtn, 0];rv[fixSimRtn, 0];rv[chkRunSimRtn, 0];rv[currentTaskNum, 0];rmRegion[randomRM];knowRbase[randomRM];rv[rndm0, 134134];rv[rndm1, 054206];rv[rndm2, 036711];rv[rndm3, 103625];rv[rndm4, 117253];rv[rndm5,154737];rv[rndm6, 041344];rv[rndm7, 006712];* rm below not used for simple random number generator.rv[randV,0];* current value from random number generatorrv[randX,0];* current index into random number jump tablerv[oldRandV,0];* saved valuerv[oldRandX,0];* saved valueknowRbase[defaultRegion];mp[flags.conditionalP, 200];* bit that indicates conditional simulatingmp[flags.conditionOKp, 100];* bit that indicates conditional simulating is okset[holdValueLoc, 3400];mc[holdValueLocC, holdValueLoc];mc[flags.taskSim, b15];* NOTE: The "flags" manipulation codemc[flags.holdSim, b14];* works only so long as there are no moremc[flags.simulating, flags.taskSim, flags.holdSim];set[simTaskLevel, 12]; mc[simTaskLevelC, simTaskLevel];mc[sim.holdMask, 377]; set[sim.holdShift, 0];mc[sim.taskMask, 177400]; set[sim.taskShift, 10];m[lh, byt0[ and[rshift[#1,10], 377] ] byt1[ and[#1, 377]]];* assemble data for left half of IMm[rh, byt2[ and[rshift[#1,10], 377] ] byt3[ and[#1, 377]]];* assemble data for right half of IMm[zeroHold, ilc[(#1 _ A0)]ilc[(hold&tasksim _ #1)]ilc[(hold&tasksim _ #1)]ilc[(hold&tasksim _ #1)]];HfpX.2BN bq_]ZpqYpqWp qUp qTyROpq #pq Nipq #pq Lpq #pqKapq #pq I7HYpq,Fpq-EQpq# Cpq# @=pq++<8pq+190p q#7p q#%6(p q#)4pqp q3 p q p q0p q p q.p qp q +pq4*# (pq4'$ #pq"s k ;=KMODEL 1: preamble.mcMay 18, 1981 1:29 PM%4* December 11, 1978 3:20 PM%subroutine entry/exit macros%m[saveReturn, ilc[(t _ link)]top level[]ilc[(#1 _ t)]];m[saveReturnAndT, ilc[(#2 _ t)]ilc[(t _ link)]top level[]ilc[(#1 _ t)]];m[returnUsing, subroutine[]ilc[(RBASE _ rbase[#1])]ilc[(link _ #1)]ilc[(return, RBASE _ rbase[defaultRegion])]];m[returnAndBranch, subroutine[]ilc[(RBASE_rbase[#1])]ilc[(link_#1)]ilc[(RBASE_rbase[defaultRegion])]ilc[(return, PD_#2)]];m[pushReturn, subroutine[]ilc[(stkp+1)]top level[]ilc[(stack _ link)]];* notice that this macro doesn't clobber T !!!m[pushReturnAndT, subroutine[]ilc[(stkp+1)]ilc[(stack&+1 _ link)]top level[]ilc[(stack_t)]];m[returnP, subroutine[]ilc[(link_(stack&-1))]ilc[(return)]];m[pReturnP,ilc[(stkp-1)]subroutine[]ilc[(link_(stack&-1))]ilc[(return)]];m[returnPAndBranch, subroutine[]ilc[(link_(stack&-1))]ilc[(return, PD_#1)]];m[pReturnPAndBranch, subroutine[]ilc[(stkp-1)]ilc[(link_(stack&-1))]ilc[(return, PD_#1)]];*m[getRandom, ilc[(RBASE _ rbase[randX])]*ilc[(randX _ (randX)+1, Bdispatch _ randX)]HfpX.2BN bq `_ ] \p qZ Y W Typ qRQq O Ni Kap q IHYF+EQ Cpq BI@ ?A!=<8 :p q 90 7 6(4. 3 pq 1 0. - + *pq (' %| #p"sq  k c pq [S pq K C pq 3+ +^MODEL 1: preamble.mcMay 18, 1981 1:29 PM%5*ilc[(call[random], RBASE _ rbase[rndm0])]*ilc[(RBASE _ rbase[defaultRegion])]*];* Returns random number in T, leaves RBASE= defaultRegionm[getRandom, ilc[(RBASE_ rbase[rndm0])]ilc[(call[random])]ilc[(RBASE_ rbase[defaultRegion])]];knowRbase[defaultRegion];HfpX.2BN bq) `# _: ]pq\Z"Y U. T26@postamble.mcJuly 11, 1984 3:13 PM %1TITLE[POSTAMBLE];TOP LEVEL;%July 11, 1984Fix assembly problem in notifytask - bigDBispatch was inside a subroutineMay 18, 1981 1:37 PMFix random number generator to use a better algorithm. Modify restart code, and the various subroutinesassociated with random numbers. Add setRandV, cycleRandV.February 1, 1980 6:24 PMFix goto[preBegin], described below, into goto[restartDiagnostic]. Postamble already defines and usespreBegin.February 1, 1980 11:52 AMFix restart to goto[preBegin]. This allows each diagnostic to perform whatever initialization it wants.September 19, 1979 9:18 PMFix another editing bug in chkSimulating, used the wrong bit to check for flags.conditionOK -- just did itwrong.September 19, 1979 9:08 PMFix bug in chkSimulating wherein an edit lost a carriage return and a statment became part of a comment.Unfortunately, automatic line breaks made the statement look as if it were still there rather than making it look likepart of the comment line.September 19, 1979 4:23 PMFix placement errors associated with bumming locations from makeholdvalue and from checksimulating.September 19, 1979 3:48 PMBum locations to fit postamble with current os/microD: reallyDone, checkFlags global, make checkFlagscallers exploit FF, eliminate noCirculate label, make others shorter..September 19, 1979 10:41 AMchange callers of getIM*, putIM* to use FF field when calling them.September 19, 1979 10:18 AMCreate zeroHoldTRscr which loops to zero hold-- called by routines that invoke resetHold when the holdsimulator may be functioning. Make getIM*, putIM* routines global.September 16, 1979 1:27 PMBum code to fix storage full problem that occurs because OS 16/6 is bigger than OS 15/5: remove kernelspecific patch locations (patch*).August 1, 1979 3:28 PMAdd scopeTrigger.June 17, 1979 4:48 PMMove IM data locations around to accommodate Ifu entry pointsApril 26, 1979 11:03 AMMake justReturn global.April 19, 1979 5:03 PMRemove calls to incTask/HoldFreq from enable/disableConditionalTask.April 18, 1979 3:24 PMRemove DisplayOff from postamble.April 18, 1979 11:11 AMRename chkTaskSim, chkHoldSim, simControl to incTaskFreq, incHoldFreq, makeHoldValue; clean upsetHold.April 17, 1979 10:51 PMSimControl now masks holdFreq and taskFreq & shifts them w/ constants defined in Postamble.April 11, 1979 3:49 PMAdd breakpoint to "done", and fix, again, a bug associated with task simulation. Set defaultFlagsP (whenpostamble defines it) to force taskSim and holdSim.-fp .+XN bq ` ^ \w ZI YoWh Vg: TVRf QN O=Mh KJ#j H FE h Cv B ?>mc <\:f 9TF 7B5C 32)f 0C .,f *" ('i %X#= ! ? .D ! ^  f[ U i M3 C]postamble.mcJuly 11, 1984 3:13 PM %2March 7, 1979 11:42 PMSet RBASE to defaultRegion upon entry to postamble. thnx to Roger.February 16, 1979 2:54 PMModify routines that read IM to invert the value returned in link if b1 from that value =1 (this implies thewhole value was inverted).January 25, 1979 10:41 AMChange taskCirculate code to accommodate taskSim wakeups for task 10D, 12BJanuary 18, 1979 5:13 PMModify checkTaskNum to use the RM value, currentTaskNum, and modify taskCircInc to keep the copy incurrentTaskNum.January 15, 1979 1:25 PMadd justReturn, a subroutine that just returnsJanuary 9, 1979 12:07 PMbreakpoint on xorTaskSimXit to avoid midas bug%%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++TABLE of CONTENTS, by order of Occurencedonelocation where diagnostics go when they are finished --gives control to postamble codethe increments iterations, implements hold and task simulation and task circulation.reallyDoneLocation where postamble inits 2 rm locations then performs "GoTo BEGIN"restartReinit diagnostic state, then restart the diagnostic.incTaskFreqIncrement the task frequency counterincHoldFreqIncrement the hold frequency countermakeHoldValueCounstruct the "Hold&TaskSim" value from holdFreq and taskFreq, given that each isenabled in FlagschkRunSimulatorsCause Hold or Task sim to happen, if requiredchkSimulatingReturn ALU#0 if some sort of simulating occuringtaskCirculateImplement task circulationincIterationsIncrement iterations counter (>16 bits)resetHoldReset Hold&TaskSim to its previous value.setHoldSet hold&task sim, notifying task simulator to do it.simInitEntry point for initialization in task simulator codetestTaskSimSubroutine that tests task simulatorfixSimRun Hold&TaskSim given current holdFreq and taskFreqreadByte3Return byte 3 of an IM locationgetIMRHReturn right half of an IM locationgetIMLHReturn left half of an IM locationputIMRHWrite Right half of an IM locationputIMLHWrite Left half aof an IM locationcheckFlagsReturn Alu result & t based on entry mask & current flagscheckTaskNumReturn "currentTaskNum" # expectedTaskNumnotifyTaskAwaken take in TtopLvlPostRtnCode that returns through mainPostRtnscopeTriggerGlobal subroutine that performs TIOA_0,TIOA_177777justReturnglobal subroutine that returns onlyrandomreturn random numbers, used w/ getRand[] macro.saveRandStateSave random number generator's staterestoreRandStateRestore old state to random number generatorgetRandVPart of random number linkagexorFlagsXor Flags w/ txorTaskCirctoggle flags.taskCircxorHoldSimtoggle flags.holdSimxorTaskSimtoggle flags.taskSimdisableConditionalTaskdisable conditional taskingenableConditionalTaskenable conditional tasking-fp .+XN bq`B ^]l [ YoWp q6 VgTp q1p q S_ QNOp q NFL. K> H2 Gb E p( BqV A.T ?p qH >&pq5

m*+ ;e2 97h 6$421y .qx ,a )y (` %XC "Pz U H2 d\ +-TL  D  yD]postamble.mcJuly 11, 1984 3:13 PM %5knowRbase[rm2ForKernelRtn];* defined in preamble because of macros* that reference randV, randXknowRbase[defaultRegion];-fp .+XN`q+' _Z X7M#postamble.mcJuly 11, 1984 3:13 PM %6* February 1, 1980 6:24 PMPOSTAMBLE CONTROL CODERBASE _ rbase[defaultRegion], breakpoint;* set RBASE incase user's is different.call[incTaskFreq];call[incHoldFreq];call[makeHoldValue];call[taskCirculate];call[incIterations];call[checkFlags]t_flags.testTasks;* bookkeeping is done. switch tasks if requiredskpif[ALU#0];branch[preBegin];* xit if not running other taskstaskCircInit:* now that bookkeeping is done, switch tasks if requirednoop;* for placement.call[checkTaskNum];rscr _ t;* rscr _ nextTaskt _ preBeginLocC;* link _ t _ preBeginLocsubroutine;taskCirc:zeroHold[rscr2];* turn off hold-task sim during LdTpc_, wakeuplink _ t;t _ rscr;top level;ldTPC _ t;* tpc[nextTask] _ preBeginLoccall[notifyTask];* wakeup nextTask: task num in tset[xtask, 1];block;set[xtask, 0];preBegin: noop,at[preBeginLoc];call[chkRunSimulators];* check for simulator conditions and run if requiredreallyDone:* LOOP TO BEGINt_RSCR_a1;goto[begin], RSCR2_t;restart:* restart diagnostics from "initial" staterndm0 _ t-t;* restart random number generatorrandX _ t-t;rscr _ t-t;* restart hold/task simulator stuffcall[putIMRH], t _ holdFreqLocC;rscr _ t-t;call[putIMRH], t_taskFreqLocC;rscr _ t-t;call[putIMRH], t _ holdValueLocC;rscr _ t-t;* restart iterations countcall[putIMRH], t _ itrsLocC;branch[restartDiagnostic];* special entry point so each diagnostic* can perform whatever special initialization that it wants to perform-fp .+XN bq+_)+']\ZYWTy"+/R Qq+ Nip +q8L+KaI+F+EQ CpBIq+.@?A= <8 +:+ 90 7 6( 3 pq+1+4 .p +p-q + (p+q*' +!%| "s +# k c ! +SK+( F @Xpostamble.mcJuly 11, 1984 3:13 PM %7* January 18, 1978 1:51 PM%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++This code sets the taskSim value with the next value if flags.testTasks is true. Otherwise 0 is used.IF flags.taskSim THENBEGIN-- when hardware counts to 17 it awakenstaskFreq _ (taskFreq + 1) or 10b;-- simTaskIF taskFreq > 15 THEN taskFreq _ 12;-- always wait min=2 cyclesENDELSE taskFreq _ 0;IF flags.holdSim THENBEGINholdFreq _ holdFreq+1;IF holdFreq >376 THEN holdFreq _ 0;END;ELSE holdFreq _ 0;%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++incTaskFreq: subroutine;t _ link;mainPostRtn _ t;top level;call[checkFlags], t_flags.taskSim;* see if taskSim enabledbranch[writeTaskSim, alu=0],t_r0;* use 0 if not enabledt_taskFreqLocC;* incrment next taskSimcall[readByte3];t_(r1)+(t);t-(156C);* Use [1..156). 156 => max wait,skpif[alu<0];* 1 = > min wait. Beware infinite hold!t_r1;* see discussion at simInit, simSet codenoop;writeTaskSim:rscr _ t;call[putIMRH], t_taskFreqLocC;* update IM locationtaskSimRtn:goto[topLvlPostRtn];incHoldFreq: subroutine;* see if holdSim enabledt _ link;mainPostRtn _ t;top level;call[checkFlags], t_flags.holdSim;branch[noHoldSim, alu=0],t_r0;* use zero if hold not enabledt_holdFreqLocC;call[readByte3];t_t+(r1);t-(377c);* IF holdFreq >376skpif[alu<0];t_r1;* THEN holdFreq _ 1;noop;* here for placement-fp .+XN bq _2 ][:e X2V+(U*!+ S$+R"P OMLJ#I F C2 B% @p q ?=< 9 "+7!+6+42 1y+/ +'.q+(, )p q(`&+ #p "Pq tp q +l "\+TL+  D+ +~ yC]postamble.mcJuly 11, 1984 3:13 PM %8noHoldSim:rscr _ t;* rewrite IMcall[putIMRH], t _ holdFreqLocC;holdSimRtn:goto[topLvlPostRtn];-fp .+XN bq`+ _ \p Zq W:'Q+postamble.mcJuly 11, 1984 3:13 PM %9* April 17, 1979 10:51 PM%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++This code actually controls the task and hold loading. It is responsible for initializing T for the task at simTaskLevel,and it is responsible for initializing HOLD.The code proceeds by constructing the current value to be loaded into hold and placing it in IM atholdValueLoc. Kernel loads HOLD as its last act before looping to BEGIN.hold&tasksim_ requires hold value in left byte, task counter value in right byte.%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++makeHoldValue: subroutine;* construct holdValuesaveReturn[mainPostRtn];call[chkSimulating];skpif[alu#0];branch[simCtrl0];t_holdFreqLocC;* rscr2 _ holdFreqcall[readByte3], t_holdFreqLocC;rscr2 _ t;call[readByte3], t_taskFreqLocC;* t _ taskFreqt_lsh[t, sim.taskShift];* position hold and task valuest_t and (sim.taskMask);rscr2 _ lsh[rscr2, sim.holdShift];rscr2 _ (rscr2) and (sim.holdMask);rscr2 _ (rscr2) and (377c);rscr2 _ (t) + (rscr2);* taskFreq,,holdFreqrscr _ rscr2;% now, save combined taskSim, holdSim values in IM. Last thing done before exiting postamble is to set HOLD ifsimulating.%simCtrlWHold:* may branch here from simCtrl0call[putIMRH], t _ holdValueLocC;* write holdValue into holdValueLocbranch[simCtrlRtn];simCtrl0:branch[simCtrlWHold], rscr _ t-t;* write zero into holdValueLocsimCtrlRtn:goto[topLvlPostRtn];-fp .+XN bq `2 _ \y [:,X2b VH SQ R"2 P Op q +MJI GD}+BAu >m+ ;e+98]"6#5U2L+0 /D -m ,< * )4p +q'!+#&, #$p!q!+ p q uCMpostamble.mcJuly 11, 1984 3:13 PM %10* September 19, 1979 9:09 PM%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++IF chkSimulating[] THEN fixSimulator[];* cause hold or task simulator to run, if required%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++chkRunSimulators: subroutine;saveReturn[chkRunSimRtn];call[chkSimulating];dblBranch[chkRunsimXit, chkRunSimDoIt, alu=0];chkRunSimDoIt:* run the simulatornoop;call[fixSim];noop;chkRunSimXit:returnUsing[chkRunSimRtn];* September 19, 1979 9:19 PM%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++chkSimulating: PROCEDURE RETURNS[weAreSimulating: BOOLEAN] =BEGINweAreSimulating _ FALSE;IF flags.Simulating THENIF ~(flags.Conditional) OR (flags.Conditional AND flags.ConditionOK) THENweAreSimulating _ TRUE;END;%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++chkSimulating: subroutine;saveReturn[chkSimulatingRtn];call[checkFlags], t_flags.simulating;* check for taskSim OR holdSimbranch[chkSimNo, alu=0];t _ flags.conditional;* We're simulating. checkcall[checkFlags], t _ flags.conditional;dblbranch[chkSimYes, chkSimCond, alu=0];chkSimCond:* conditional simulation. check for okt _ flags.conditionOK;call[checkFlags];skpif[alu=0];branch[chkSimYes];* conditionOK is set, do it!branch[chkSimNo];chkSimYes:* run the simulatort _ (r0)+1;* rtn w/ alu#0chkSimRtn:returnAndBranch[chkSimulatingRtn, t];chkSimNo:branch[chkSimRtn], t _ r0;* rtn w/ alu=0-fp .+XN bq _2 ]\' Y2 X22 V Rpq QNONF. Lp +qK>I H6 E-p Cq ? =2 < :p q.9 764I21y /!2 - ,p q *)%+'& +$(#( !}p +q&t l+ dp +q + \p q% Tpq+  CYpostamble.mcJuly 11, 1984 3:13 PM %11* January 25, 1979 10:44 AM%This code controls task circulation for the diagnostics: when flags.testTasks is set, postamble causes successivetasks to execute the diagnostic code when the current task has completed. If flags.taskSim is true the diagnostic isusing the taskSimulator to periodically awaken the simulator task; consequently, that task (simTaskLevel) must notexecute the diagnostic -- otherwise the advantage of the simulator for testing the effects of task switching will be lost.IF ~flags.testTasks THEN RETURN;temp _ getTaskNum[] + 1;-- increment the current numberIF flags.taskSim THENIF temp = simTaskLevel THEN temp _ temp+1;IF temp > maxTaskLevel THEN temp _ 0;putTaskNum[temp];-- remember it in IM%taskCirculate: subroutine;saveReturn[mainPostRtn];call[checkFlags], t _ flags.testTasks;branch[taskCircRtn, ALU=0];* Don't bother if not task circulating.noop;call[checkTaskNum];* Increment the current task number.t _ t + (r1);* Current value came back in t.q _ t;* Remember incremented value in Q.call[checkFlags], t _ flags.taskSim;skpif[ALU#0], t _ q;* Now, see if using task simulator.branch[taskCircChk];* If not task simulating, check for max size.t - (simTaskLevelC);* Since we're task simulating, avoidskpif[ALU#0];* we must avoid simTaskLevel.t _ t+1;* Increment over simTask if required.noop;taskCircChk:t - (20C);* See if tasknum is too big.skpif[ALU#0];t _ t-t;* We wraparound to zero.currentTaskNum _ t;* keep it in both RM and IMrscr _ t;call[putIMRH], t _ nextTaskLocC;noop;* for placementtaskCircRtn:goto[topLvlPostRtn];-fp .+XN bq `^q ]u [\r q Yz W Vg+ TR* P% O=+ M L5p q JI-&G+'F$C+$A +@+"= $;+#:+-6+$5x +3+%2p /hp -q +,_ *+'+&O$#G+ ?p q: DKpostamble.mcJuly 11, 1984 3:13 PM %12* January 18, 1978 1:57 PMincIterations: subroutine;* maintain double precision count at incItrsLoct _ link;mainPostRtn _ t;top level;call[getIMRH], t _ itrsLocC;* increment iteration count at tableloc+1rscr _ (t)+1;rscr2 _ rscr;* copy new itrsrscr2 _ (t) #(rscr);* see if new b0 # old b0rscr2 _ (rscr2) AND (b0);skpif[alu#0];branch[incItrs2], q _ r0;* new b0 = old b0. remember in q and writet and (B0);* see if b0 went from 0 to 1 or 1 to 0 (carry)skpif[alu=0], q_r0;* skpif old b0 = 0q _ r1;incItrs2:call[putIMRH], t _ itrsLocC;* T = addr, rscr = valuerscr2 _ q;branch[incItrsRtn,alu=0];* goto incItrsRtn if no carryincItersHi16:link _ t;* read hi byte of hi 16 bitscall[getIMLH];rscr _ (t)+1;call[putIMLH], t _ itrsLocC;* T = addr, rscr = valuenoop;* help the instruction placer.incItrsRtn:goto[topLvlPostRtn];-fp .+XN bq _p q +/]\Z W+)U R +Qq+NiL Ka+*I +.HY+F EQpBIq+@ ?A+ <8p q:+90 7 6(+4+ 1p 0qV .M;9postamble.mcJuly 11, 1984 3:13 PM %13* March 20, 1978 1:51 PM KERNEL - COMMON SUBROUTINESresetHold: subroutine;* special subroutine called by IM manipulating* code. This subr saves t, rscr, rscr2 and causes hold to be initialized to the value in* holdValueLocC. It restores the RM and T values before returning.oldT _ t;t _ link;resetHoldRtn _ t;top level;t _ rscr;oldrscr _ t;t _ rscr2;oldrscr2 _ t;* link, t, rscr, and rscr2 are now saved.t _ HoldValueLocC;* READ RIGHT HALF, HoldValueLocCsubroutine;link _ t;top level;readim[3];* read low order bytesubroutine;t _ link;* low byte in tt and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.t _ not(t);t _ t and (getIMmask);* isolate the byterscr _ HoldValueLocC;subroutine;link _ rscr;top level;readim[2];* read hi order bytesubroutine;rscr2 _ link;* hi byte in rscr2(rscr2) and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.rscr2 _ not(rscr2);rscr2 _ (rscr2) and (getIMmask);* isolate the bytetop level;noop;rscr2 _ lsh[rscr2, 10];* left shift hi bytet _ t and (377C);* isolate low bytet _ t OR (rscr2);* add hi bytecall[setHold];knowRbase[rmForKernelRtn];* restore link, t, rscr, rscr2, then returnRBASE _ rbase[rmForKernelRtn];t _ oldrscr;rscr _ t;t _ oldrscr2;rscr2 _ t;subroutine;link _ resetHoldRtn;return, t _ oldt, RBASE _ rbase[defaultRegion];-fp .+XN bq+ _p q +. ]Y \BZYWU TyR Qq O +)L+Ka IHY F +EQ C+BI +-@ +#?A =+:90 7 6( 4 +3 1 +0+-. +#-++( '%|+#+"s+  ++c [ S  K/ ;Xpostamble.mcJuly 11, 1984 3:13 PM %14* June 23, 1978 10:22 AMsetHold: subroutine;* ENTER w/ T = HOLD value* clobber t, rscr, rscr2zeroHold[rscr2];* kill hold-task sim before polyphas instrs xqtrscr2 _ q;* SAVE Qq _ t;* save hold value, then save rtn linkt _ link;setHoldRtn _ t;taskingon;t _ simInitLocC;* defined w/ postamble constants OR in* some user specific code (eg., memSubrsA where RM values are defined). This* convention allows users to specify their own code to run when the simulator task runs.link _ t;* cause task taskSimLevel to puttop level;ldTPC _ simTaskLevelC;* proper hold value in T for refreshnotify[simTaskLevel];* after task switch occurs. Remember* taskSim is a counter. refresh it!noop;* wakeup will happen soonnoop;rbase _ RBASE[rmForKernelRtn];t_ setHoldRtn, rbase _ RBASE[defaultRegion];Q _ rscr2;* restore Qsubroutine;link _ t;return;* This code actually causes T to be set properly and branches to the code that sets HOLD.set[xtask, 1];simInit:t _ q,at[initTloc];simSet:hold&tasksim_t;* T init'd at simInitnoop;* this noop doesn't cause hold to countsimBlock:branch[simSet], block;* count hold, block%Note: if t = 14, then hold = 16 when the simulator blocks. The preempted task will execute one instruction, then thetask simulator will waken the simulator task.%set[xtask, 0];* November 6, 1978 12:07 PMMIDAS SUBROUTINE for testing the task simulatortestTaskSim: subroutine;rscr _ link;* save return in case we later want ittop level;t _ lsh[t, 10];* ENTER w/ T = task sim val NOT shiftedq _ t;* simInit expects q = hold valuesubroutine;t _ initTlocC;link _ t;top level;LDTPC _ simTaskLevelC;notify[simTaskLevel];-fp .+XN bq `pq + _\+/Z +Y+%WUR Qq+&OLNiXL+Ka I+$HY+$+F#EQ+CBI@,?A + = <8: 7Y4 1pq0+ .pq-+++' *pq(+ ' %|t #- "sk c+/ p q [ +& S+'+ C  ;   3r D^postamble.mcJuly 11, 1984 3:13 PM %15noop;t _ t - t;* t _ 0branch[., alu=0], t_t;* this shouldn't changetestTaskErr:branch[.], breakpoint;subroutine;link _ rscr;return;fixSim: subroutine;t_link;* save return in fixSimRtnfixSimRtn _ t;top level;call[makeHoldValue];* compose holdValue and set hardwarecall[getIMRH], t _ holdValueLocC;call[setHold];returnUsing[fixSimRtn];zeroHoldTRscr: subroutine;t_4c;rscr_a0;zeroHoldTRscrL:Hold&TaskSim_rscr;t_t-1, Hold&TaskSim_rscr;loopUntil[alu<0, zeroHoldTRscrL];return;-fp .+XN`q_ +]+ \p ZqW U Ty Qqpq O+Ni L I+$HY!F C @p q ?A= <8p q:907!6( 2652ypostamble.mcJuly 11, 1984 3:13 PM %16* January 18, 1979 5:18 PM* READ/WRITE IM%The subroutines that read and write IM turn OFF hold simulator before touching IM. Before they return tothe caller, the invoke "resetHold" to reset the hold register to the contents of "holdValueLoc". By convention, thecurrent value of the two simulator registers is kept in "holdValueLoc" for this express purpose. Zeroing and resettinghold is done because of hardware restrictions: hold and polyphase instructions don't mix.ReadIM[] instructions are followed by a mask operation with getIMmask because of the interaction betweenDWATCH (Midas facility) and LINK[0].%readByte3: subroutine;* CLOBBER T, RSCR!zeroHold[rscr];rscr _ link;* this routine assumes t points to IMlink _ t;* it reads the least significan byte in IMtop level;* read byte 3readim[3];subroutine;t_link;* t = byte3t and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.t _ not(t);t _ t and (getIMmask);* isolate the bytetop level;* reset value of hold and returncall[resetHold];subroutine;link _ rscr;return;* return w/ byte in tgetIMRH: subroutine, global;* CLOBBER T, RSCR, RSCR2!zeroHold[rscr];* disable task/hold Sim before touching IMrscr _ link;* ENTER w/ T pointing to IM locationlink _ t;top level;* read hi byte of right halfreadim[2];subroutine;rscr2 _ link;* rscr2 = high byte(rscr2) and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.rscr2 _ not(rscr2);rscr2 _ (rscr2) and (getIMmask);* isolate the bytelink _ t;* read low byte of right halftop level;readim[3];subroutine;t _ link;* t = low byte, rscr2 = hi bytet and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.t _ not(t);t _ t and (getIMmask);* isolate the byterscr2 _ lsh[rscr2, 10];t _ t + (rscr2);* RETURN w/ T = IMRH-fp .+XN bq+ `_h ]s \v ZYWh U$ Ty Qqpq +OL +%Ka+*HY + F EQ C+ BI +-@ +#?A =+: +907 6( 4+ 1pq+0+*- +$+( +' %| # +"s+- +#k++[  S +K +- +#C +  3+b D^postamble.mcJuly 11, 1984 3:13 PM %17top level;call[resetHold];subroutine;link _ rscr;return;getIMLH: subroutine, global;* CLOBBER T, RSCR, RSCR2!zeroHold[rscr];* disable task/hold Sim before touching IMrscr _ link;* ENTER w/ T pointing to IM locationlink _ t;top level;* read hi byte of left halfreadim[0];subroutine;rscr2 _ link;* rscr2 = hi byte(rscr2) and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.rscr2 _ not(rscr2);rscr2 _ (rscr2) and (getIMmask);* isolate the bytelink _ t;* read low byte of left halftop level;readim[1];subroutine;* CLOBBER T, RSCR, RSCR2!t _ link;* t = low byte, rscr2 = hi bytet and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.t _ not(t);t _ t and (getIMmask);* isolate the byterscr2 _ lsh[rscr2, 10];t _ t + (rscr2);* RETURN w/ T = IMLHtop level;call[resetHold];subroutine;link _ rscr;return;putIMRH: subroutine, global;* T = addr, RSCR = value, clobberr RSCR2rscr2 _ link;link _ t;zeroHold[t];* disable task/hold Sim before touching IMtop level;t _ rscr;IMRHB'POK _ t;call[resetHold];subroutine;link _ rscr2;return;-fp .+XN`q _] \ Z Wpq+U+*R +$QqNi +L Ka I +HY+-F +#EQC+@+?A = <8 +:+90 +-7 +#6( 4+10+- +* ( ' #pq+("s   +* [ K  C x:Ypostamble.mcJuly 11, 1984 3:13 PM %18putIMLH: subroutine, global;* T = addr, RSCR = value, Clobber RSCR2rscr2 _ rscr;rscr _ link;link _ t;zeroHold[t];* disable task/hold Sim before touching IMtop level;t _ rscr2;IMLHR0'POK _ t;call[resetHold];subroutine;link _ rscr;return;checkFlags: subroutine, global;* CLOBBER T, RSCR, RSCR2rscr _ link;* this routine assumes t has a bit maskzeroHold[rscr2];* disable task/hold Sim before touching IMrscr2 _ flagsLocC;* it reads the flags word in IMlink _ rscr2;* and performs t_tANDflagtop level;readim[3];subroutine;rscr2 _ link;(rscr2) and (b1);* see if the data is inverted. If so, b1 willskpif[ALU=0];* 1, and we must reinvert the data.rscr2 _ not(rscr2);rscr2 _ (rscr2) and (getIMmask);* isolate the bytetop level;call[resetHold];subroutine;link _ rscr;return, t _ t AND(rscr2);* returnee can do alu=0 fast branchcheckTaskNum: subroutine;* enter: T=expected task num,rscr_t, RBASE _ rbase[currentTaskNum];* return: T=current task num, branch conditiont _ currentTaskNum, RBASE _ rbase[defaultRegion];* clobber rscr, rscr2return, t#(rscr);* rtn w/ branch condition, t=current task* number, rscr = expected task number.-fp .+XN bq+'` _ ]Z +*W U TyQqO Ni L Ip q+HY +'EQ+*BI+@ +?A = <8 : 90+-7 +#6(4+1 0. - ++# (p q +'&+.%|15"s+) & $N bq ` _ ] \p Zq1Y Wp 1Uq Typ 1Rq Qqp Oq Nip Lq Kap 1Fq'1EQ1C1@1?A1=1:190 1716(13 11 101.1+1*1(1%|1#1"s1k 1 1c1( [1 S1 K pq1  Cpq1' 1  ;pq1' 1 ' 1 3   +^kernel.mcOctober 9, 1986 3:32 PM%2l4:noop,at[dbgTbls,6];noop,at[dbgTbls,7];noop,at[dbgTbls,10];branch[l4],at[dbgTbls,11];l5:noop,at[dbgTbls,12];noop,at[dbgTbls,13];noop,at[dbgTbls,14];noop,at[dbgTbls,15];branch[l5],at[dbgTbls,16];l6:noop,at[dbgTbls,17];noop,at[dbgTbls,20];noop,at[dbgTbls,21];noop,at[dbgTbls,22];noop,at[dbgTbls,23];branch[l6],at[dbgTbls,24];END;,fp(X>N bq1' 1`' 1_'1]  \pq1'1Z'1Y'1W'1U  Typq1'1R'1Qq'1O'1Ni'1L  Il I#uxkernel1.mcSeptember 22, 1986%1* INSERT[D1ALU.MC];* TITLE[PROG1];* INSERT[PREAMBLE.MC];%September 22, 1986 5:18 PMRemoved comments for scope loops that did not exist. Removed several double labels for the samemicroinstruction.September 21, 1981 10:53 AMAdd comments for various Scope (midas) files.May 18, 1981 11:08 AMChange "bypass" to save and restore values in RBase 0. Need this because of a change in versions of d1lang.diagnostic now uses "standard" d1lang.May 8, 1979 11:40 AMAdd RoddByPass tests at enbd of xorBypassMarch 26, 1979 10:58 AMAdd overflow testMarch 10, 1979 6:43 PMAdd tst of branch conditions when reschedule is ON.January 18, 1979 5:23 PMRemove checkTaskNum, a temporary kludge that caused reschedTest to fail during task circulation.January 9, 1979 10:44 AMadd reschedTest%%CONTENTSTESTDESCRIPTION(singlestep)Chec RM to T, T to RM movementaluEQ0check the fast branch codealuLT0check the fast branch coderEvencheck the fast branch coderGE0check the fast branch codereschedTestcheck the reschedule/noreschedule fast branchesxorNoBypasstest XOR alu opbypasstest bypass decision logicxorBypasstest XOR alu op, ALLOW BYPASS; R odd bypass test here, too.(alu ops)Test various alu operations (A+1, A+B, A-1,A-B)CarryTest carry fast branch(resched+branches)test effect of resched upon fast branches.freezeBCtestTest Freeze BC function (emulator only)overflowTestTest the overflow fast branch function%fp +X=vN bq ` _ ] \1Z_ Y W1U- Ty1Rl Qq& O1Ni) L1Ka I1HY3 FH1D` B1A. ? <; 8 5   3  2  0  .  -z  / +   *r  ( ; 'i / %  $a * "  ( !Y  &  BKkernel1.mcSeptember 22, 1986%2* September 15, 1978 10:18 AM%SINGLE STEP THIS CODE:A AND B MULTIPLEXORSThe point is to determine if it is possible to move data values thruthe alu into different registers.%top level;kernel1:IM0:T_RM1;*TEST ALL ONES, ALL ZEROS, ALTER. 01, 10NOOP;* USE NOOP TO AVOID BYPASS LOGICIM2:RSCR_T;NOOP;IM4:T_R0;* TEST 0NOOP;IM6:RSCR _ T;NOOP;* NOW MOVE IT THRU A MUXIM14:T_A_RM1;* TEST ALL ONESNOOP;IM16:RSCR _A_ T;NOOP;IM20:T_A_R0;* TEST ALL ZEROSNOOP;IM22:RSCR_ A_T;* CHECK B MUX THRU FF FIELD: SINGLE STEP THIS CODEIM23:T_B0;* check that FF,0 worksIM24:T_77400C;IM25:T_B15;* check that 0,FF worksIM26:T_376C;fp +X=vN bq ^B \+[:D Y! X2 TV R QN+(O+ NFL K>+I H6F C @+? = < :+9  7 42 1y+ / .q+ ,| (=?Akernel1.mcSeptember 22, 1986%3* September 21, 1981 10:54 AM%END SINGLE STEPPING !!!GIVEN SIMPLE A AND B PATHS, VALIDATE:RESULT=0RESULT<0R>=0R EVENCNT=0&+1%%TEST ALU=0 BY CHECKING EVERY BIT IN THE WORD: GET CONSTANTS FROMFF AND CHECK THEM FOR =0. USE BYPASS LOGIC!!These tests assume that there is no difference between amux source and bmux source for fast branches. ACTUALLY,the initial set of tests will check amuxsources too!T contains the value received.%aluEQ0FF:t_B0;skpUnless[ALU=0],rscr_(A_t);* check it thru Amuxerror;* Thinks bit0 is zeroskpUnless[ALU=0];error;* Thinks bit0 is zerot_B1;skpUnless[ALU=0],rscr_(A_t);* check it thru AmuxaluEq0FFB1:error;* Thinks bit1 is zeroskpUnless[ALU=0];error;* Thinks bit1 is zeronoop;*here for placement.t_B2;skpUnless[ALU=0],rscr_(A_t);* check it thru AmuxaluEq0FFB2:error;* Thinks bit2 is zeroskpUnless[ALU=0];error;* Thinks bit2 is zerot_B3;skpUnless[ALU=0],rscr_(A_t);* check it thru Amuxerror;* Thinks bit3 is zeroskpUnless[ALU=0];error;* Thinks bit3 is zerot_B4;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB4:error;* Thinks bit4 is zeroskpUnless[ALU=0];error;* Thinks bit4 is zerofp +X=vN bq _^BY%X2VU*SR" P LA K>, H6o F( E- B% ? =pq<:+9 +76+21y+ /p q.q+,+i+(`+&%X+ #p q"P+ H+@+8+0+(+  p q+  +| LE\kernel1.mcSeptember 22, 1986%4t_B5;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit5 is zeroskpUnless[ALU=0];error;* Thinks bit5 is zeronoop;* here for placement.t_B6;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB6:error;* Thinks bit6 is zeroskpUnless[ALU=0];error;* Thinks bit6 is zerot_B7;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit7 is zeroskpUnless[ALU=0];error;* Thinks bit7 is zerot_B8;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB8:error;* Thinks bit8 is zeroskpUnless[ALU=0];error;* Thinks bit8 is zerot_B9;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit9 is zeroskpUnless[ALU=0];error;* Thinks bit9 is zeronoop;* here for placement.t_B10;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB10:error;* Thinks bit10 is zeroskpUnless[ALU=0];error;* Thinks bit10 is zerot_B11;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit11 is zeroskpUnless[ALU=0];error;* Thinks bit11 is zerot_B12;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB12:error;* Thinks bit12 is zeroskpUnless[ALU=0];error;* Thinks bit12 is zerot_B13;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit13 is zeroskpUnless[ALU=0];fp +X=vN`q_+]+\Z+W+UTy+ Rp qQq+ONi+KaI+HY+FEQ+BI@+ ?Ap q=+<8:+76(+4+3 1+.+-++ *p q(+'%|+"s +k+c+[+ Sp q+K+ ;+ + 3 ,j^5kernel1.mcSeptember 22, 1986%5error;* Thinks bit13 is zeronoop;* here for placement.t_B14;skpUnless[ALU=0], rscr_(A_t);* check it thru AmuxaluEq0FFB14:error;* Thinks bit14 is zerorscr_(A_t);* check it thru AmuxskpUnless[ALU=0];error;* Thinks bit14 is zerot_B15;skpUnless[ALU=0], rscr_(A_t);* check it thru Amuxerror;* Thinks bit15 is zeroskpUnless[ALU=0];error;* Thinks bit15 is zero% TEST ALU=0 BY PASSAGE THRU RM AND PASSAGE THRU TFor all the alu=0 tests, an error implies the wrong branch was taken.The known values in RM are used to test the branchAVOID BYPASS LOGIC!%aluEq0RT:t_r0;skpif[alu=0];error;* Thinks r0 is zerorscr_t;skpif[alu=0],t_r1;error;skpUnless[alu=0];error;* Thinks r1 is zerorscr_t;skpUnless[alu=0],t_rm1;error;aluEq0RTM1:skpUnless[alu=0];error;* Thinks rm1 is zerorscr_t;skpUnless[alu=0],t_r1;error;skpUnless[alu=0];error;* Thinks r1 is zerorscr_t;skpUnless[alu=0],t_r01;error;aluEq0RT01:skpUnless[alu=0];error;* Thinks r01 is zerorscr_t;skpUnless[alu=0],t_r10;fp +X=vNbq+_+]\+ Zp qY+W +UTy+QqO+Ni+LKa+ F EQ1BIE@2= <8 90pq76( 4+3 10-++*(' #p q"s +kc[+SK Cp q ;+  3 ,j^kernel1.mcSeptember 22, 1986%6error;skpUnless[alu=0];error;* Thinks r10 is zerorscr_t;skpUnless[alu=0],t_rhigh1;error;skpUnless[alu=0];error;* Thinks rhigh1 is zerorscr_t;skpUnless[alu=0];error;fp +X=vNbq_]+\ZYUTy+RQqO L-FmCkernel1.mcSeptember 22, 1986%7% TEST RESULT <0For all the alu<0 tests, an error implies the wrong branch was taken.The known values in RM are used to test the branchAVOID BYPASS LOGIC%aluLT0RT:t_rhigh1;skpif[alu<0];error;* Thinks rhigh1 >=0rscr_t;skpif[alu<0];error;* Thinks T (=RIGH1) >=0t_r10;skpif[alu<0];aluLT0RT10:error;* Thinks r10 >= 0rscr_t;skpif[alu<0];error;* Thinks T (=r10) >=0t_r1;skpUnless[alu<0];aluLT0RT1:error;* Thinks r1<0rscr_t;skpUnless[alu<0];error;* Thinks T (=r1) >=0t_r01;skpUnless[alu<0];aluLT0RT01:error;* Thinks r10 >= 0rscr_t;skpUnless[alu<0];error;* Thinks T (=r10) >=0* TEST FOR RESULT EVENrEven:skpif[r even], t_r0;error;* thinks r0 oddskpUnless[r even], t_r1;error;* Thinks r1 EVENskpif[r even], t_rhigh1;error;* Thinks rhigh1 ODDskpUnless[r even], t_r01;error;* Thinks r01 EVENskpif[r even], t_r10;fp +X=vN `q _\EZ2W U TypqRQq O+NiL Ka+HYF EQp qC+BI@ ?A+<8: 90pq7+ 6(43 +0. -p q++*('+  pqc+S+K+ ;+ 3@ 0^kernel1.mcSeptember 22, 1986%8error;* Thinks r10 ODDfp +X=vNbq+4 ^* <kernel1.mcSeptember 22, 1986%9rGE0:skpif[r >=0],t_r1;error;* Thinks r1 <0skpif[r>=0],t_r01;error;* Thinks r01 <0skpif[r>=0],t_r0;error;* Thinks r0 <0skpUnless[r>=0],t_rm1;error;* Thinks RM1>=0skpUnless[r>=0],t_rhigh1;* Thinks rhigh1 >=0error;fp +X=vN `q_]+ ZY+UTy+ QqO+L+Ka I,IuIkernel1.mcSeptember 22, 1986%10* April 9, 1982 3:22 PM%jcnBRThe preceeding tests checked that ff decodes work properly and that the alu bit slice doesn't drop any bits.Now we check that jcn conditional branch opcodes work properly.This test forces the assembler to use the jcn field to encode the fast branch condition. It does this by forcingthe FF field to be used for a constant (B_0C) in the same instruction where the conditional branch occurs.Since the other tests make sure that the actual branch condition is correctly detected (eg., is ALU=0 or not),this test serves to checkout the jcn decoders and a small amount of other circuitry. Consequently is is not necessary totest for both values of the fast branch: we need only check that when the branch condition is true it gets taken whenusing jcn encoding.True condtions for fast branches:ALU=0, ALU<0, noCarry, CNT=0, R<0, R odd, noIOattn (noIoattn is tested in resched test)%jcnBR:Pd_ r0;skpif[ALU=0], B_0c;* use FF field for a constantjcnBREq0:error;* jcn encoded ALU=0 didn't work okPd_ rm1;skpif[ALU<0], B_0c;* use FF field for a constantjcnBRLt0:error;* jcn encoded ALU<0 didn't work okt_ (r0)+(r0);skpUnless[carry], B_0C;jcnBRCarry:error;* jcn encoded carry didn't workcnt_r0;branch[.+2,cnt=0&-1], B_0C;jcnBrCntEq0:error;* jcn encoded cnt=0 didn't workskpif[r<0], rm1, B_0C;jcnBrRLt0:error;* jcn encoded R<0 didn't workskpif[r odd], r1, B_ 0c;jcnBrRodd:error;* jcn encoded R odd didn't workfp +X=vN bq ` _p\ql Z?Wq UjRn Qqy Ov Ni Ka!IW HY FpEQqC+ BIpq@+"=<8+ :pq90+"6( 4 3 p q1+.- +p q*+' %|p #q+  kpq+ ENFkernel1.mcSeptember 22, 1986%11* September 21, 1981 11:01 AM%reschedTestSet and clear resched; see if we can branch on its value.%reschedTest:call[checkTaskNum], t_t-t;skpif[ALU=0];branch[reschedXit];noreschedule[];skpif[reschedule'];reschedErr1:* we just cleared resched, yeterror;* branch condition thinks it is set.skpif[reschedule'], B_0C;reschedErr1a:error;* jcn encoded br didn't workreschedule[];skpif[reschedule];reschedErr2:* we just set resched, yet theerror;* branch condition doesn't realize it.noreschedule[];reschedXit:noop;fp +X=vN bq `_p ]q9 Z Yp WqU TyQqO Nip +qL+$Ka Ip HYq+EQ C BIp +q@+&?A =p <8q :m5--zkernel1.mcSeptember 22, 1986%12% September 15, 1978 10:56 AM TEST XOR USING ALU=0. USE NOOP TO AVOID BYPASS.Generally, T _ RSCR_ someFFconstant;T _ T#(RSCR)IF T is non zero, there was an error: one bits in T indicatethe problem.%xorNoBypass:t_(rscr)_B0;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B0 xor (RSCR) ) NE 0t_(rscr)_B1;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B1 xor (RSCR) ) NE 0xorNoBypassB2:t_(rscr)_B2;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B2 xor (RSCR) ) NE 0t_(rscr)_B3;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B3 xor (RSCR) ) NE 0t_(rscr)_B4;noop; t_t#(rscr);skpif[alu=0];xorNoBypassB4:error;* (T _ B4 xor (RSCR) ) NE 0t_(rscr)_B5;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B5 xor (RSCR) ) NE 0xorNoBypassB6:t_(rscr)_B6;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B6 xor (RSCR) ) NE 0t_(rscr)_B7;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B7 xor (RSCR) ) NE 0xorNoBypassB8:t_(rscr)_B8;noop; t_t#(rscr);skpif[alu=0];fp +X=vN bq ` _0\$Z Y<W Ty Qqp qO NiL Ka+HY FEQ C+ @p q?A =<8 :+7 6(4 3 +0 .- +p q*+' %|# "s+ kp q c [+S K + p q ;   3  1>^kernel1.mcSeptember 22, 1986%13error;* (T _ B8 xor (RSCR) ) NE 0t_(rscr)_B9;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B9 xor (RSCR) ) NE 0xorNoBypassB10:t_(rscr)_B10;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B8 xor (RSCR) ) NE 0t_(rscr)_B11;noop; t_t#(rscr);skpif[alu=0];error;* (T _ B10 xor (RSCR) ) NE 0t_(rscr)_B12;noop;t_t#(rscr);skpif[alu=0];xorNoBypassB12:error;* (T _ B12 xor (RSCR) ) NE 0t_(rscr)_B13;noop;t_t#(rscr);skpif[alu=0];error;* (T _ B13 xor (RSCR) ) NE 0xorNoBypassB14:t_(rscr)_B14;noop;t_t#(rscr);skpif[alu=0];error;* (T _ B14 xor (RSCR) ) NE 0t_(rscr)_B15;noop;t_t#(rscr);skpif[alu=0];error;* (T _ B15 xor (RSCR) ) NE 0fp +X=vNbq+] \Z Y+ Up qTy RQq O+L KaI HY+EQ CBI @p q?A+<8 :90 7+ 4p q3 10 .++ *( '+ %51Bkernel1.mcSeptember 22, 1986%14* May 18, 1981 11:12 AM% bypassThis code checks the decision portion of the bypass circuitry. There are at least two different issues associatedwith bypass: 1) should a bypass be done, and 2) do the bypass data paths work. This test addresses point 1.%rvrel[rmx10, 10];bypass:RBASE _ 0s;q_ rmx0;t_rmx0_cm1;* this is the old, stable versionrmx0_t-t;* this is the new versiont_rmx0;* should use bypassed version of rmx0skpif[alu=0], rmx0_q;* RESTORE rmx0 here.bypassErr0:* bypass associated w/ rm addr 0 doesn'terror;* seem to workq_ rmx1;t_rmx1_cm1;* this is the old, stable versionrmx1_t-t;* this is the new versiont_rmx1;* should use bypassed version of rmx1skpif[alu=0], rmx1_q;* RESTORE rmx1 here.bypassErr1:* bypass associated w/ rm addr 1 doesn'terror;* seem to workq_ rmx2;t_rmx2_cm1;* this is the old, stable versionrmx2_t-t;* this is the new versiont_rmx2;* should use bypassed version of rmx2skpif[alu=0], rmx2_q;* RESTORE rmx2 here.bypassErr2:* bypass associated w/ rm addr 2 doesn'terror;* seem to workq_ rmx4;t_rmx4_cm1;* this is the old, stable versionrmx4_t-t;* this is the new versiont_rmx4;* should use bypassed version of rmx4skpif[alu=0], rmx4_q;* RESTORE rmx4 here.bypassErr4:* bypass associated w/ rm addr 4 doesn'terror;* seem to workq_ rmx10;t_rmx10_cm1;* this is the old, stable versionrmx10_t-t;* this is the new versiont_rmx10;* should use bypassed version of rmx10skpif[alu=0], rmx10_q;* RESTORE rmx10 here.bypassErr10:* bypass associated w/ rm addr 10 doesn'terror;* seem to work%This section of the test works by changing Rbase.%RBASE _ 2s;t_rmx0_cm1;* this is the old, stable versionrmx0_t-t;* this is the new versiont_rmx0;* should use bypassed version of rmx0skpif[alu=0];bypassErr20:* bypass associated w/ rm addr 20 doesn'terror;* seem to workfp +X=vN bq `p_qq ]k Z Y WpUq TyR +!Qq+O+%Ni+ Lp +q(Ka+ HYF +!EQ+C+%BI+ @p +q(?A+ <8: +!90+7+%6(+ 4p +q(3 + 0. +!-+++%*+ (p +q('+ #"s +! +k+&+ cp +q)+ [1 S K +!+C+% ;p +q) +  C^+kernel1.mcSeptember 22, 1986%15RBASE _ 4s;t_rmx0_cm1;* this is the old, stable versionrmx0_t-t;* this is the new versiont_rmx0;* should use bypassed version of rmx0skpif[alu=0];bypassErr40:* bypass associated w/ rm addr 40 doesn'terror;* seem to workRBASE _ 10s;t_rmx0_cm1;* this is the old, stable versionrmx0_t-t;* this is the new versiont_rmx0;* should use bypassed version of rmx0skpif[alu=0];bypassErr100:* bypass associated w/ rm addr 100 doesn'terror;* seem to workbypassXit:RBASE _ rbase[defaultRegion];fp +X=vNbq ` +!_+]+%\ Zp +q)Y+ U Ty +!R+Qq+%O Nip +q*L+ Kap HYq F9"!}jkernel1.mcSeptember 22, 1986%16% August 30, 1977 6:29 PM TEST XOR USING ALU=0.Generally, T _ RSCR_ someFFconstant;T _ T#(RSCR)IF T is non zero, there was an error: one bits in T indicatethe problem.%* TEST XOR USING ALU=0. CHECK BYPASS.xorBypass:t_(rscr)_B0;t_t#(rscr);skpif[ALU=0];error;* (T _ B0 xor (RSCR) ) NE 0t_(rscr)_B1;t_t#(rscr);skpif[ALU=0];error;* (T _ B1 xor (RSCR) ) NE 0t_(rscr)_B2;t_t#(rscr);skpif[ALU=0];xorBypass2:error;* (T _ B2 xor (RSCR) ) NE 0t_(rscr)_B3;t_t#(rscr);skpif[ALU=0];error;* (T _ B3 xor (RSCR) ) NE 0t_(rscr)_B4;t_t#(rscr);skpif[ALU=0];xorBypass4:error;* (T _ B4 xor (RSCR) ) NE 0t_(rscr)_B5;t_t#(rscr);skpif[ALU=0];error;* (T _ B5 xor (RSCR) ) NE 0t_(rscr)_B6;t_t#(rscr);skpif[ALU=0];xorBypassB6:error;* (T _ B6 xor (RSCR) ) NE 0t_(rscr)_B7;t_t#(rscr);skpif[ALU=0];error;* (T _ B7 xor (RSCR) ) NE 0t_(rscr)_B8;fp +X=vN `q _ ]Z$Y W<U R Qq% NipqKa I HY F+C BI @ ?A+<8 : 90 7p q6(+3 1 0 .++ * ( 'p q%|+"s  k + [  Sp q+ C   ;+ 3 N 1>^kernel1.mcSeptember 22, 1986%17t_t#(rscr);skpif[ALU=0];xorBypassB8:error;* (T _ B8 xor (RSCR) ) NE 0t_(rscr)_B9;t_t#(rscr);skpif[ALU=0];error;* (T _ B9 xor (RSCR) ) NE 0t_(rscr)_B10;t_t#(rscr);skpif[ALU=0];xorBypassB10:error;* (T _ B10 xor (RSCR) ) NE 0t_(rscr)_B11;t_t#(rscr);skpif[ALU=0];error;* (T _ B11 xor (RSCR) ) NE 0t_(rscr)_B12;t_t#(rscr);skpif[ALU=0];xorBypassB12:error;* (T _ B12 xor (RSCR) ) NE 0t_(rscr)_B13;t_t#(rscr);skpif[ALU=0];error;* (T _ B13 xor (RSCR) ) NE 0t_(rscr)_B14;t_t#(rscr);skpif[ALU=0];xorBypassB14:error;* (T _ B14 xor (RSCR) ) NE 0t_(rscr)_B15;t_t#(rscr);skpif[ALU=0];error;* (T _ B15 xor (RSCR) ) NE 0rscr _ t-t;rscr _ 1c;skpif[R ODD], rscr;RoddByPassErr0:* fast branch r odd bypass doesn't workerror;* Rscr has 1 in itrscr _ t-t;skpUnless[R ODD], rscr;RoddByPassErr1:* fast branch r odd bypass doesn't work.error;* rscr has zero in it.fp +X=vNbq ` _p q]+Z Y W U+R Qq O Nip qL+I HY F EQ+BI @ ?A =p q<8+90 7 6( 4+1 0 . -p q++( ' %| #+    p+q' +  p+q(w+f (7^Xkernel1.mcSeptember 22, 1986%18* August 30, 1977 6:29 PM%TEST ALU ADDITION AND SUBTRACTION:A+1A+BA-1 A-B%Aplus1:t_(r0)+1;* 1=t_r0+1t_(r1)#t;skpif[alu=0];error;Aplus1b:t_(rm1)+1;* 0=t_rm1+1skpif[alu=0];error;Aplus1c:rscr_CM2;t_(rscr)+1;t_t#(rm1);* (T=-1)=-2+1skpif[alu=0];error;Aplus1d:rscr_5C;t_(rscr)+1;rscr_6C;t_t#(rscr);* (T=6)=5+1skpif[alu=0];error;AplusB:t_r0;t_t+(r0);* 0=0+0skpif[alu=0];error;AplusBb:t_r1;t_t+(r0);t_t#(r1);* 1=1+0skpif[alu=0];error;AplusBc:t_r0;t_t+(r1);t_t#(r1);* 1=0+1skpif[alu=0];error;AplusBd:t_rm1;t_t+(r0);t_t#(rm1);* -1=-1+0skpif[alu=0];error;fp +X=vN bq `_"]  Z YpqW+ UTy R OpqNi + L Ka HYpqFEQ C + BI @ =pq<8: 907 + 6( 4 1pq0.+- + (pq'%|#+"s   pqc[+ S KpqC + ;  B )^kernel1.mcSeptember 22, 1986%19AplusBe:t_rm1;t_t+(rm1);rscr_177776C;t_t#(rscr);* -2=-1+-1skpif[alu=0];error;AplusBf:t_rm1;t_t+(r1);* 0=-1+1skpif[alu=0];error;AplusBg:t_r1;t_t+(rm1);* 0=1+-1skpif[alu=0];error;AplusBh:t_r01;t_t+(r10);t_t#(rm1);* -1=52525+125252skpif[alu=0];error;AplusBi:t_r10;t_t+(r01);t_t#(rm1);* -1=125252+52525skpif[alu=0];error;AplusBj:t_rhigh1;t_t+(rhigh1);*0=100000+100000skpif[alu=0];error;AplusBk:t_rhigh1;t_t+(rm1);rscr_77777C;t_t#(rscr);* 77777=100000+177777skpif[alu=0];error;AplusBl:t_rm1;t_t+(rhigh1);rscr_77777C;t_t#(rscr);* 77777=177777+100000skpif[alu=0];error;fp +X=vN bq`_ ] \ + Z Y UpqTyR+Qq O LpqKaI +HY F CpqBI@ ?A += <8 90pq76( 4 +3 1 .pq-+ +* ( %|pq#"s  k + c [pqS  K + CR x/aYkernel1.mcSeptember 22, 1986%20* August 9, 1977 12:30 PM%TEST A-1%Aminus1:rscr_r0;Aminus1L:* CHECK A-1 IN A LOOP FOR ALL 16 BIT VALUES.t_(rscr)-1;t_t+1;t_t#(rscr);* t_ (rscr-1+1) xor rscrskpif[alu=0];error;rscr_(rscr)+1;* rscr IS LOOP CTRLdblBranch[.+1,Aminus1L,ALU=0];fp +X=vN bq `_ ] ZpqY Wpq+,U TyR +Qq ONi +L KA~Skernel1.mcSeptember 22, 1986%21*%TEST A-B%aMinusB:t_r0;t_t-(r1);* T _ 0 -1t_t#(rm1);skpif[alu=0];error;* T SHOULD HAVE BEEN -1aMinusBb:t_r0;t_t-(rm1);* t_0 - (-1)t_t#(r1);skpif[alu=0];error;* T SHOULD HAVE BEEN 1aMinusBc:t_r0;t_t-(rhigh1);* t_ 0 - (100000)t_t#(rhigh1);skpif[alu=0];error;* T SHOULD HAVE BEEN 100000aMinusBd:t_100C;t_t-(r1);* t _ 100 -1rscr_77C;t_t#(rscr);skpif[alu=0];error;* T SHOULD HAVE BEEN 77aMinusBe:t_rscr_17C;t_t-(rscr);* t _ 17 - 17t_t#(r0);skpif[alu=0];error;* T SHOULD HAVE BEEN 0aMinusBf:t_rscr_177C;t_t-(rscr);* t _ 177 - 177t_t#(r0);skpif[alu=0];error;* T SHOULD HAVE BEEN 0aMinusBg:t_rscr_377C;t_t-(rscr);* t _ 377 - 377t_t#(r0);skpif[alu=0];error;* T SHOULD HAVE BEEN 0aMinusBh:t_rscr_400C;t_t-(rscr);* t _ 400 - 400t_t#(r0);skpif[alu=0];fp +X=vN bq `_ ] \pqZY+ W U Ty+ QqpqONi + LKa I+ FpqEQC +BI @ ?A+ <8pq:90+ 76( 4 3 + 0pq. - + +* (+ %|pq# "s + k + pq[  +S K+ Cpq  ; +  3  5V^kernel1.mcSeptember 22, 1986%22error;* T SHOULD HAVE BEEN 0aMinusBi:t_rscr_777C;t_t-(rscr);* t _ 777 - 777t_t#(r0);skpif[alu=0];error;* T SHOULD HAVE BEEN 0aMinusBj:t_rscr_1777C;t_t-(rscr);* t _ 1777 - 1777t_t#(r0);skpif[alu=0];error;* T SHOULD HAVE BEEN 0fp +X=vNbq+ _pq] \ +ZY W+ TypqR Qq +ONi L+ H1Skernel1.mcSeptember 22, 1986%23* January 18, 1979 5:24 PM%TEST FAST BRANCH CONDITION: CARRYFIRST TEST WHEN WE KNOW THERE IS NO CARRY, THEN TRY TOGENERATE A CARRY AND BRANCH ON IT. NOTE: THIS CODE DEPENDS UPONTHE ALU FUNCTIONS PLUS AND MINUS WORKING.%carryNo:t_(r0)+(r0);skpUnless[carry];error;* r0 + r0 SHOULD NOT CAUSE CARRYcarryNob:t_rm1;t_t+(r0);skpUnless[carry];error;* rm1 + r0 SHOULD NOT CAUSE CARRYcarryNoc:t_r10;t_t+(r01);skpUnless[carry];error;* r10 + r01 SHOULD NOT CAUSE CARRYcarryNod:t_77777C;t_t+(r0);skpUnless[carry];error;* 77777C + r0 SHOULD NOT CAUSE CARRYcarryNoe:t_r0;t_t+(r1);skpUnless[carry];error;* r0 + r1 SHOULD NOT CAUSE CARRYcarryNof:t_r01;t_t-(r10);skpUnless[carry];error;* r01 - r10 SHOULD NOT CAUSE CARRYcarryNog:t_r0;t_t-(r10);skpUnless[carry];error;* r0 + r10 SHOULD NOT CAUSE CARRY* NOW TRY SOMETHINGS THAT SHOULD GENERATE A CARRYcarryYes:t_rm1;t_t-(r1);skpif[carry];error;* -1 -(+1) SHOULD CAUSE CARRYcarryYesb:fp +X=vN bq `_!\6Z?Y) U TypqR QqO+ LpqKaIHYF+! CpqBI@ ?A=+" :pq9076(4+$ 1pq0.-++ (pq'%| #"s+" kpqc [+! S1 KpqC  ;+ 3pq =6^kernel1.mcSeptember 22, 1986%24t_rm1;t_t+(rhigh1);skpif[carry];error;* -1 + 100000 SHOULD CAUSE CARRYcarryYesc:t_rm1;t_t+(r1);skpif[carry];error;* -1 + 1 SHOULD CAUSE CARRYcarryYesd:t_rhigh1;t_t-(r01);skpif[carry];error;* 100000 - r01 SHOULD CAUSE CARRYcarryYese:t_rhigh1;t_t+(rhigh1);skpif[carry];error;* 100000 + 100000 SHOULD CAUSE CARRY* NOW COMPLICATE THINGS INTERLEAVING ALU OPS W/ TESTScarryOps:t_r0;t_t-(r1);* t_0-1skpUnless[carry],t_t+(rm1);* t_-1+-1error;* 0-1 SHOULD NOT CAUSE CARRYcarryOpsb:skpif[carry], t_t+(rhigh1);* T _ -2+100000error;* -1+-1 SHOULD CAUSE CARRYcarryOpsc:skpif[carry],t_t+(rhigh1);* t_ 77776 + 100000error;* -2 + 100000 SHOULD CAUSE CARRYcarryOpsd:skpUnless[carry];error;* 77776 + 100000 SHOULD NOT CAUSE CARRYcarryOpse:t_rm1;t_t-(r1);* t_ -1-(+1)skpif[carry],t_t-(r01);* t_ -2 -r01error;* -1-1 SHOULD CAUSE CARRYcarryOpsf:skpif[carry];error;* 177776 - 52525 SHOULD CAUSE CARRYfp +X=vNbq` _ ]+ ZpqYWU Ty+ QqpqONi L Ka+! HYpqFEQ C BI+$ ?A5 <8pq:90+7+6(+ 3 pq1+0+ -pq++*+ 'pq%|#+' pqk+ c+ + pqS +# ?%Ukernel1.mcSeptember 22, 1986%25* March 10, 1979 6:42 PM* test the branch conditions when reschedule is ONreschedule;t_r0;t_t-(r1);* t_0-1skpUnless[carry],t_t+(rm1);* t_-1+-1error;* 0-1 SHOULD NOT CAUSE CARRYcarryOpsRb:skpif[carry], t_t+(rhigh1);* T _ -2+100000error;* -1+-1 SHOULD CAUSE CARRYcarryOpsRc:skpif[carry],t_t+(rhigh1);* t_ 77776 + 100000error;* -2 + 100000 SHOULD CAUSE CARRYcarryOpsRd:skpUnless[carry];error;* 77776 + 100000 SHOULD NOT CAUSE CARRYcarryOpsRe:t_rm1;t_t-(r1);* t_ -1-(+1)skpif[carry],t_t-(r01);* t_ -2 -r01error;* -1-1 SHOULD CAUSE CARRYcarryOpsRf:skpif[carry];error;* 177776 - 52525 SHOULD CAUSE CARRYt_r0;skpif[ALU=0];rescheq0br:error;t_r1;skpif[ALU#0];reschne0br:error;skpif[r even], B_r0;reschevenbr:error;skpif[r odd], B_r1;reschoddbr:error;t_rhigh1;skpif[alu<0];reschlt0br:error;t_r0;skpif[alu>=0];reschge0br:error;noreschedule;fp +X=vN bq `2] \Z+Y+W+ Up qTy+R+ Op qNi+L+ Ip qHYF+' Cp qBI@+ ?A+ =+ :p q90 7+#43 1p q0.- +p q*( 'p q%|# "sp q k cp q[ Sp qC ^ ?%[kernel1.mcSeptember 22, 1986%26* September 15, 1978 11:38 AM%TEST FREEZEBC FUNCTIONGenerate the two different branch conditions and freeze them. Force thecarry to be explicitly different, see if the frozen branch is still there.Unfreeze and make sure the expected results happen.%freezeBCtest:t_rm1;t_t+(r1);* t_ 0 _ -1+1 (SHOULD CAUSE carry)skpif[carry],t_t+(r1),freezeBC;* FREEZE[carry=1]error;* carry WAS FROZEN. CONTINUE THAT WAY (carry_1, RESULt_0)freezeBC1a:skpif[alu=0],freezeBC;* ( result was ZERO)error;t_(rm1)+(rm1),freezeBC;* Would normally CAUSE RESULT <0skpif[alu>=0],freezeBC;* ( result was ZERO)error;freezeBC1b:t_(r1)+(r1),freezeBC;* t_ 0+1 (carry Would NORMALLY BE ZERO)skpif[carry],freezeBC;error;t_tAND(rm1),freezeBC;* t_1 and -1 (TEST IT A FEW MORE TIMES)skpif[carry],freezeBC;error;* carry SHOULD HAVE BEEN 1freezeBC1c:t_t+(r0),freezeBC;* t_1+0skpif[carry],freezeBC;error;* carry SHOULD HAVE BEEN 1* ALLOW A NEW alu RESULT CONDITION, KEEP carry THE SAME(carry=1, RESULT=77777)freezeBC2a:t_rm1,freezeBC;t_t+(rhigh1);* carry_1, RESULt_77777t_(r0)+(r0),freezeBC;skpif[alu#0],freezeBC;* result was 77777error;freezeBC2b:t_t+(r0),freezeBC;* Would normally ZERO carryskpif[carry],freezeBC;* carry SHOULD BE ONEerror;freezeBC2c:t_rm1,freezeBC;t_t+(r0),freezeBC;skpif[alu>=0],freezeBC;* result was 77777error;* FORCE carry_0, RESULt_0fp +X=vN bq `_ \G ZJ Y3 Ty Rp q1Qq1O"1Ni" 1L I9 HYp q1F1EQ1BI!1@1?A <8p q1:'1901714'13 11' .p q1-1+1*' 'N %|p q1#1"s 1 1k1 p q1[11S Kp q11C11 ; 3F <^kernel1.mcSeptember 22, 1986%27t_r0,freezeBC;t_t+(r0);* t_0+0 (SHOULD CAUSE carry_0, RESULt_0)t_(rhigh1)+(rhigh1),freezeBC;* Would NORMALLY CAUSE carry_1freezeBC3a:skpUnless[carry],freezeBC;* FREEZE IT AT ZEROerror;* EXPECTED 0 carry GOT 1 carryt_(r1)+(r1),freezeBC;skpif[alu=0],freezeBC;* test it again just to seeerror;freezeBC3b:t_(rm1)+(rm1),freezeBC;skpif[alu>=0],freezeBC;* test it again just to seeerror;* FORCE carry_0, RESULT _ -1t_(rm1)+(rm1);t_t+(r1);* -2+1 ==> carry_0, RESULt_-1freezeBC4a:t_t+(r1),freezeBC;* -1+1 Would normally CAUSE carry_1skpUnless[carry],freezeBC;error;freezeBC4b:t_(r1)+(r1),freezeBC;*Would normally CAUSE alu>=0skpUnless[alu>=0],freezeBC;error;freezeBC4c:skpUnless[alu=0];error;fp +X=vN1bq 1`(1_"  \p q1Z1Y'1U1Ty1R Op q1Ni1L1Ka HY1F 1EQ BIp q1@#1?A1= :p q1901716( 3 p q1110 .M.[9kernel1.mcSeptember 22, 1986%28* March 26, 1979 11:04 AM%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++overflowTestPerform an exhaustive test of the overflow condition. Even though we expect the arithmetic result of RM+T to beidentical to T+RM, we test all possible combinations since the arithmetic gets implemented inside a rathercomplicated chip.The tables below show the aluA and aluB inputs, and the carry out values for b0, b1. Notice the contents of the tableare not the sum of a,b, but the carry out values. The subtraction table shows the original input for B and then itsconverted value after the number gets converted to a twos complement value (the chip converts it to the twoscomplement form, then adds).For AdditionB input=00011011A input00000000000100010011Notice these values represent thecarry out values1000001010for b0,b1 during addition. Theypresume carry-in to1100111011b1 is zero%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++mc[x01, 40000];mc[x10, 100000];mc[x11, 140000];overflowTest:t _ t-t;t _ t + t;skpif[overflow'];overflErr0:* 0+0 should not cause overflowerror;t_t-t;t_t+(x01);skpif[overflow'];overflErr1:* see 0 + 01 entryerror;t _ t-t;t _ t + (x10);skpif[overflow'];overflErr2:* see 0 + 10 entryerror;t_t-t;t_t+(x11);skpif[overflow'];overflerr3: * see 0 + 11 entryerror;t_rscr_x01;* keep x01 in rscr for a whilet _ t + (0c);skpif[overflow'];overflErr4:* see 01 + 0 entryerror;t_rscr;t _ t + (x01);skpif[overflow];* FIRST TRY FOR OVERFLOWoverflErr5:* see 01 + 01 entryerror;t_rscr;fp +X=vN bq `2 _ *M]p \qp Zj Y W4pq" Ut Tyl R*YQqp 1Oq@Ni@L '@Ka '7)ukernel2.mcSeptember 22, 1986 5:41 PM%13* October 19, 1978 8:54 PM%TEST STKP: READ AND WRITEFOR I IN[0..377B] DOSTKP_I;t_TIOA&STKP[]t_t and (stkpMask);t_t XOR I;IF T # 0 THEN error;ENDLOOP;%STKPtestRW:t_r0;rscr_t;* rscr = values loaded into stackprscr2 _ t_377C;* MASK TO ISOLATE STACKPcnt_t;* mask just happens to be count, toostkpL:STKP_rscr;* LOAD STKP FROM rscrt _ (TIOA&STKP);t_t AND (rscr2);* READ AND MASK THE VALUEt_t#(rscr);skpif[ALU=0];stkpErr:error;* error: DIDN'T READ WHAT WE LOADEDdblBranch[.+1,stkpL,CNT=0&-1],rscr_(rscr)+1;fp (-X@]N bq `_\ZY WU TyR Qq Nip qLKa+"I+HY+$ EQpqC +BI@+?A = <8p:q+#90, 7e<20kernel2.mcSeptember 22, 1986 5:41 PM%14* October 26, 1978 12:03 PM%rstkFFTest the FF operation that replaces rstk with a value from theFF field during rm Writing. Test each bitpath only.%rstkFF:q _ rmx0;* save rmx0rmx0 _ t-t;* background test rm location w/ zerot _ rmx7 _ cm1;* KEEP -1 IN RMX7, AND Trmx0 _ rmx7;* write into RM w/ rstk from FF fieldt # (rmx0);* compare target RM w/ expected valueskpif[alu=0];rstkFF0Err:* can't write into rstk0 w/ fferror;rmx0 _ q;* restore old valueq _ rmx1;* save rmx1rmx1 _ t-t;* background test rm location w/ zerormx1 _ rmx7;* write into RM w/ rstk from FF fieldt # (rmx1);* compare target RM w/ expected valueskpif[ALU=0];rstkFF1Err:* can't write into rstk1 w/ fferror;rmx1 _ q;* restore old valueq _ rmx2;* save rmx2rmx2 _ t-t;* background test rm location w/ zerormx2 _ rmx7;* write into RM w/ rstk from FF fieldt # (rmx2);* compare target RM w/ expected valueskpif[ALU=0];rstkFF2Err:* can't write into rstk2 w/ fferror;rmx2 _ q;* restore old valueq _ rmx4;* save rmx4rmx4 _ t-t;* background test rm location w/ zerormx4 _ rmx7;* write into RM w/ rstk from FF fieldt # (rmx7);* compare target RM w/ expected valueskpif[ALU=0];rstkFF4Err:* can't write rstk4 w/ fferror;rmx4 _ q;* restore old valueq _ rmx10;* save rmx10rmx10 _ t-t;* background test rm location w/ zerormx10 _ rmx7;* write into RM w/ rstk from FF fieldt # (rmx10);* compare target RM w/ expected valueskpif[ALU=0];rstkFF10Err:* can't write rstk10 w/ fferror;rmx10 _ q;fp (-X@]N bq `_p+q> ]rq \ ZpYq+ W +%U+Ty +%R +%Qq Op +qNiKa+I+ HY +%F +%EQ +%C BIp +q@=+<8+ : +%90 +%7 +%6( 4p +q3 0+.+ - +%+ +%* +%( 'p +q%|"s+ + k +% +%c +% [p +q  D&U kernel2.mcSeptember 22, 1986 5:41 PM%15* October 26, 1978 6:14 PM%rbaseFFtest the facility that changes the value of rbase when rm storingoccurs.%* sibling[FoosBrotherInRegion5, 5, foo]* declare FoosBrotherInRegion5 as an RM* location in rmRegion 5 with its rstk value the same as the one for foo. Eg., if foo is* located at rm addr 17,,12 (rbase = 17, rstk = 12) then FoosBrotherInRegion5 is located* at rm addr 5,,12m[sibling,rm[#1, add[lshift[#2,4], and[17,ip[#3]]]]];sibling[rb0rm0, 0, rmx0];sibling[rb1rm1, 1, rmx1];sibling[rb2rm2, 2, rmx2];sibling[rb4rm4, 4, rmx4]; sibling[rb10rm10, 10, rmx10];rbaseFF:rbase _ rbase[defaultRegion];q _ rmx0;* save current value for "source" rmrb0rm0 _ t-t;* zero "destination" rmrmx0 _ cm1;* t _ "source rm" _ -1rb0rm0 _ rmx0;* "destin" rm (different rbase)_ source rmrbase _ 0s;* check the result. First fetch the value int _ rmx0, RBASE _ rbase[defaultRegion];* the destination rm, then compare it tot # (rmx0);* the source rm. An error means we didn'tskpif[ALU=0];rbaseFF0Err:* succeed in writing rm with rbase_0 fromerror;* ff field. t = real val, rmx0=expected val.rmx0 _ q;* restore old valueq _ rmx1;* save current value for "source" rmt _ rmx1 _ cm1;* t _ "source rm" _ -1rb1rm1 _ t-t;* zero "destination" rmrb1rm1 _ rmx1;* "destin" rm (different rbase)_ source rmRBASE _ 1s;* check the result. First fetch the value int _ rmx1, RBASE _ rbase[defaultRegion];* the destination rm, then compare it tot # (rmx1);* the source rm. An error means we didn'tskpif[ALU=0];rbaseFF1Err:* succeed in writing rm with rbase_0 fromerror;* ff field. t = real val, rmx0=expected val.rmx1 _ q;* restore old valueq _ rmx2;* save current value for "source" rmt _ rmx2 _ cm1;* t _ "source rm" _ -1rb2rm2 _ t-t;* zero "destination" rmrb2rm2 _ rmx2;* "destin" rm (different rbase)_ source rmRBASE _ 2s;* check the result. First fetch the value int _ rmx2, RBASE _ rbase[defaultRegion];* the destination rm, then compare it tot # (rmx2);* the source rm. An error means we didn'tskpif[ALU=0];rbaseFF2Err:* succeed in writing rm with rbase_0 fromerror;* ff field. t = real val, rmx0=expected val.rmx2 _ q;* restore old valueq _ rmx4;* save current value for "source" rmt _ rmx4 _ cm1;* t _ "source rm" _ -1rb4rm4 _ t-t;* zero "destination" rmrb4rm4 _ rmx4;* "destin" rm (different rbase)_ source rmRBASE _ 4s;* check the result. First fetch the value int _ rmx4, RBASE _ rbase[defaultRegion];* the destination rm, then compare it tofp (-X@]N bq `_p+qA ] \ Z'+' YX WX U TypRq)Qq Opq pq )z pq Nipqpq KapqIHY+$F +EQ +C +*BI +,@'+(?A +)= <8p q+):+,7+6(+$4+3 +1 +*0 +,.'+(- +)+ *p q+)(+,%|+#+$"s+ +k +* +,c'+( +)[ p q+)S+,K++$C+ + ; +* +, 3'+( E ^Mkernel2.mcSeptember 22, 1986 5:41 PM%16t # (rmx4);* the source rm. An error means we didn'tskpif[ALU=0];rbaseFF4Err:* succeed in writing rm with rbase_0 fromerror;* ff field. t = real val, rmx0=expected val.rmx4 _ q;* restore old valueq _ rmx10;* save current value for "source" rmt _ rmx10 _ cm1;* t _ "source rm" _ -1rb10rm10 _ t-t;* zero "destination" rmrb10rm10 _ rmx10;RBASE _ 10s;* check the result. First fetch the value int _ rmx10,RBASE _ rbase[defaultRegion];* the destination rm, then compare it tot # (rmx10);* the source rm. An error means we didn'tskpif[ALU=0];rbaseFF10Err:* succeed in writing rm with rbase_0 fromerror;* ff field. t = real val, rmx0=expected val.%Test RSTK destination function:FOR I IN [0..7] DOFOR J IN [0..7] DORBASE[I]_RBASE[J];t_RBASE[I];IF T#RBASE[J] THEN error;ENDLOOP; ENDLOOP;Of course, this code is "expanded" inline rather than in a loop%*FOR I IN [0..7] DO RBASE[0] _ RBASE[I]; (EXCEPT FOR _RBASE[0])rstkTest0:rscr_3C;rscr2_4C;Q_r0;t_r0_r1;t#(Q);skpUnless[ALU=0], t_t#(r0);error;skpif[ALU=0];error;t_r0_rm1;t#(Q);skpUnless[ALU=0], t_t#(r0);rstkTest02:error;skpif[ALU=0];error;t_r0_r01;t#(Q);skpUnless[ALU=0], t_t#(r0);error;skpif[ALU=0];error;fp (-X@]Nbq +)` _p q+)]+,Z+Y +$W+U+TyR +,Qq'+(O +)Ni Lp q+)Ka+, F EQBI@@?A@= @<8: 7? 6( 3 > 1pq0.+*('%|# "skc p q[ SKC ;   9 ^kernel2.mcSeptember 22, 1986 5:41 PM%17t_r0_r10;t#(Q);skpUnless[ALU=0], t_t#(r0);rstkTest04:error;skpif[ALU=0];error;t_r0_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(r0);error;skpif[ALU=0];error;t_r0_rscr;t#(Q);skpUnless[ALU=0], t_t#(r0);rstkTest06:error;skpif[ALU=0];error;t_r0_rscr2;t#(Q);skpUnless[ALU=0], t_t#(r0);error;skpif[ALU=0];error;r0_Q;*FOR I IN [0..7] DO RBASE[1] _ RBASE[I]; (EXCEPT FOR _RBASE[1])rstkTest1:Q_r1;t_r1_r0;t#(Q);skpUnless[ALU=0], t_t#(r1);error;skpif[ALU=0];error;t_r1_rm1;t#(Q);skpUnless[ALU=0], t_t#(r1);rstkTest12:error;skpif[ALU=0];error;t_r1_r01;t#(Q);skpUnless[ALU=0], t_t#(r1);error;skpif[ALU=0];error;t_r1_r10;t#(Q);skpUnless[ALU=0], t_t#(r1);fp (-X@]Nbq`_ ]p q\Z YU TyRQqO NiKa IHY Fp qEQC BI?A =<8:90 76( 3 > 1pq0.-+*( '#"s  kp qc SK C ;  3 2^kernel2.mcSeptember 22, 1986 5:41 PM%18rstkTest14:error;skpif[ALU=0];error;t_r1_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(r1);error;skpif[ALU=0];error;t_r1_rscr;t#(Q);skpUnless[ALU=0], t_t#(r1);rstkTest16:error;skpif[ALU=0];error;t_r1_rscr2;t#(Q);skpUnless[ALU=0], t_t#(r1);error;skpif[ALU=0];error;r1_Q;*FOR I IN [0..7] DO RBASE[2] _ RBASE[I]; (EXCEPT FOR _RBASE[2])rstkTest2:Q_rm1;t_rm1_r0;t#(Q);skpUnless[ALU=0], t_t#(rm1);error;skpif[ALU=0];error;t_rm1_r1;t#(Q);skpUnless[ALU=0], t_t#(rm1);rstkTest22:error;skpif[ALU=0];error;t_rm1_r01;t#(Q);skpUnless[ALU=0], t_t#(rm1);error;skpif[ALU=0];error;t_rm1_r10;t#(Q);skpUnless[ALU=0], t_t#(rm1);rstkTest24:error;skpif[ALU=0];fp (-X@]N b q`_ ]Z YWUTy RO NiL Kap qIHY FC BI@?A= <8: 7> 6(pq43 10.- +('%| #p q"s kc [S  C ;p q  3  2^kernel2.mcSeptember 22, 1986 5:41 PM%19error;t_rm1_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(rm1);error;skpif[ALU=0];error;t_rm1_rscr;t#(Q);skpUnless[ALU=0], t_t#(rm1);rstkTest26:error;skpif[ALU=0];error;t_rm1_rscr2;t#(Q);skpUnless[ALU=0], t_t#(rm1);error;skpif[ALU=0];error;rm1_Q;*FOR I IN [0..7] DO RBASE[3] _ RBASE[I]; (EXCEPT FOR _RBASE[3])rstkTest3:Q_r01;t_r01_r0;t#(Q);skpUnless[ALU=0], t_t#(r01);error;skpif[ALU=0];error;t_r01_r1;t#(Q);skpUnless[ALU=0], t_t#(r01);rstkTest32:error;skpif[ALU=0];error;t_r01_rm1;t#(Q);skpUnless[ALU=0], t_t#(r01);error;skpif[ALU=0];error;t_r01_r10;t#(Q);skpUnless[ALU=0], t_t#(r01);rstkTest34:error;skpif[ALU=0];error;t_r01_rhigh1;fp (-X@]Nbq_ ]\ZY WTy RQq Op qNiL KaHY FEQCBI @?A <8> :pq9076(43 1 0-+* (p q'%| # kc [S K p qC  ; 3  2^kernel2.mcSeptember 22, 1986 5:41 PM%20t#(Q);skpUnless[ALU=0], t_t#(r01);error;skpif[ALU=0];error;t_r01_rscr;t#(Q);skpUnless[ALU=0], t_t#(r01);rstkTest36:error;skpif[ALU=0];error;t_r01_rscr2;t#(Q);skpUnless[ALU=0], t_t#(r01);error;skpif[ALU=0];error;r01_Q;*FOR I IN [0..7] DO RBASE[4] _ RBASE[I]; (EXCEPT FOR _RBASE[4])rstkTest4:Q_r10;t_r10_r0;t#(Q);skpUnless[ALU=0], t_t#(r10);error;skpif[ALU=0];error;t_r10_r1;t#(Q);skpUnless[ALU=0], t_t#(r10);rstkTest42:error;skpif[ALU=0];error;t_r10_r01;t#(Q);skpUnless[ALU=0], t_t#(r10);error;skpif[ALU=0];error;t_r10_rm1;t#(Q);skpUnless[ALU=0], t_t#(r10);rstkTest44:error;skpif[ALU=0];error;t_r10_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(r10);error;fp (-X@]Nbq`_] \Y WU Typ qRQq OL KaIHYF EQC @> ?Apq=<8:9076( 410. -p q+* (%| #"s k  [ Sp qK   ;  3 2^kernel2.mcSeptember 22, 1986 5:41 PM%21skpif[ALU=0];error;t_r10_rscr;t#(Q);skpUnless[ALU=0], t_t#(r10);rstkTest46:error;skpif[ALU=0];error;t_r10_rscr2;t#(Q);skpUnless[ALU=0], t_t#(r10);error;skpif[ALU=0];error;r10_Q;*FOR I IN [0..7] DO RBASE[5] _ RBASE[I]; (EXCEPT FOR _RBASE[5])rstkTest5:Q_rhigh1;t_rhigh1_r0;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);error;skpif[ALU=0];error;t_rhigh1_r1;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);rstkTest52:error;skpif[ALU=0];error;t_rhigh1_r01;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);error;skpif[ALU=0];error;t_rhigh1_r10;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);rstkTest54:error;skpif[ALU=0];error;t_rhigh1_rm1;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);error;skpif[ALU=0];error;fp (-X@]Nbq `] \Z Yp qWU TyQq ONiLKa IHY EQ> CpqBI@ ?A=<8: 906( 43  1p q0. -* ('%|# "sk c p q[ SK C ;   2^kernel2.mcSeptember 22, 1986 5:41 PM%22t_rhigh1_rscr;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);rstkTest56:error;skpif[ALU=0];error;t_rhigh1_rscr2;t#(Q);skpUnless[ALU=0], t_t#(rhigh1);error;skpif[ALU=0];error;rhigh1_Q;*FOR I IN [0..7] DO RBASE[6] _ RBASE[I]; (EXCEPT FOR _RBASE[6])rstkTest6:Q_rscr;t_rscr_r0;t#(Q);skpUnless[ALU=0], t_t#(rscr);error;skpif[ALU=0];error;t_rscr_r1;t#(Q);skpUnless[ALU=0], t_t#(rscr);rstkTest62:error;skpif[ALU=0];error;t_rscr_r01;t#(Q);skpUnless[ALU=0], t_t#(rscr);error;skpif[ALU=0];error;t_rscr_r10;t#(Q);skpUnless[ALU=0], t_t#(rscr);rstkTest64:error;skpif[ALU=0];error;t_rscr_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(rscr);error;skpif[ALU=0];error;t_rscr_rm1;t#(Q);skpUnless[ALU=0], t_t#(rscr);fp (-X@]Nbq `_ ]p q\Z YUTyRQqO NiL I> HYpqFEQ CBI@?A =: 907 6(p q43 1. -+*( '# "s  kp qc  SK C ;   3 2^kernel2.mcSeptember 22, 1986 5:41 PM%23rstkTest66:error;skpif[ALU=0];error;t_rscr_rscr2;t#(Q);skpUnless[ALU=0], t_t#(rscr);error;skpif[ALU=0];error;rscr_Q;*FOR I IN [0..7] DO RBASE[7] _ RBASE[I]; (EXCEPT FOR _RBASE[7])rstkTest7:Q_rscr2;t_rscr2_r0;t#(Q);skpUnless[ALU=0], t_t#(rscr2);error;skpif[ALU=0];error;t_rscr2_r1;t#(Q);skpUnless[ALU=0], t_t#(rscr2);rstkTest72:error;skpif[ALU=0];error;t_rscr2_r01;t#(Q);skpUnless[ALU=0], t_t#(rscr2);error;skpif[ALU=0];error;t_rscr2_r10;t#(Q);skpUnless[ALU=0], t_t#(rscr2);rstkTest74:error;skpif[ALU=0];error;t_rscr2_rhigh1;t#(Q);skpUnless[ALU=0], t_t#(rscr2);error;skpif[ALU=0];error;t_rscr2_rscr;t#(Q);skpUnless[ALU=0], t_t#(rscr2);rstkTest76:error;skpif[ALU=0];fp (-X@]N b q`_ ]Z YWUTy RQq Ni> LpqKaI HYFEQC BI?A =<8 :p q907 6(3 10.- +( '%| #p q"s kc[S  C ;p q  3  2^kernel2.mcSeptember 22, 1986 5:41 PM%24error;t_rscr2_rm1;t#(Q);skpUnless[ALU=0], t_t#(rscr2);error;skpif[ALU=0];error;rscr2_Q;goto[afterKernel2];fp (-X@]Nbq_ ]\ZY WU R Q*&8kernel3.mcNovember 13, 1978 10:43 AM%1* INSERT[D1ALU.MC];* TITLE[KERNEL3];top level;beginKernel3: noop;%TESTCONTENTSSHCtestRWRead and write SHCRlshtest RM shiftlmask, lsh r[i]; 0<=i<=15Tlshtest T shiftlmask, lsh t[i]; 0<=i<=15Rrshtest RM shiftlmask, rsh r[i]; 0<=i<=15Trshtest T shiftlmask, rsh t[i]; 0<=i<=15TRlcyTesttest T R lcy[i]; 0<=i<=15. (cycle 0,,1 and 177777,,177776)RTlcyTesttest R T lcy[i]; 0<=i<=15. (cycle 0,,1 and 177777,,177776)rcy16, lcy16test 16 bit cycles with selected bit valuescycleTestTest 32 bit cycles by generating possible r,t, count valuesRFWFtesttest RF_ and WF_aluRSHtest alu right shift (ie., H3 _ ALU rightshift 1)aluRCYtest alu right cycle (ie., H3 _ ALU rightCycle 1)aluARSHtest alu arithmetic right shift (ie., H3 _ ALU rightshift 1, sign preserved)aluLSHtest alu left shiftaluLCYtest alu left cyclealuSHTESTexhaustive test of alu shifts% fp +pXN bq ` _ ]p q Z Y W U& Ty% R& Qq% O: Ni: L + Ka; I HY1 F1 EQL C BI @ ?Aj ;8,kernel3.mcNovember 13, 1978 10:43 AM%2* August 9, 1977 12:33 PM%TEST SHC: READ AND WRITEFOR I IN[0..177777B] DOSHC_I;T_SHC XOR I;IF T#0 THEN ERROR;ENDLOOP;Note: ShC is a 16 bit register AND the upper three bits [0..2] are notused by the shifter!%SHCtestRW:rscr_r0;SHCRWL:SHC_rscr;t _ SHC;t_(rscr)#(t);branch[.+2,ALU=0];error;rscr_(rscr)+1;loopUntil[ALU=0,SHCRWL];% TEST THE SHIFTERMAKE SURE THAT ALL SHIFTS WORK PROPER AMOUNTMAKE SURE ALL MASKS WORKMAKE SURE SHIFTS AND MASKS WORK TOGETHERThese tests work by left (or right) shifting bit15 (bit 0) 0 thru15 times. rscr or rscr2 holds the expected value. The result is XOR'dwith the expected value and those bits are placed in T. If t #0 therehas been an error.test order:R shift leftT shift leftR shift rightT shift rightR T cycle leftT R cycle leftR T cycle rightT R cycle rightNote: The cycle tests are duplicated with the bits inverted (eg.,bit15 {bit0} is zero and all other bits are one.%Rlsh:t_r1;rscr_t;t_B15;rscr _ lsh[rscr,0];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B14; fp +pXN bq `_\ZY WURFQq O NipqL KapqIHYF EQCBI @ =<8,:90(7A6(E4E3 0 . - + * ' %| #"s Ak0  pq[SK  C ;  3 +^kernel3.mcNovember 13, 1978 10:43 AM%3rscr _ lsh[rscr,1];t_t#(rscr);skpif[ALU=0];error;Rlsh2:t_r1;rscr_t;t_B13;rscr _ lsh[rscr,2];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B12;rscr _ lsh[rscr,3];t_t#(rscr);skpif[ALU=0];error;Rlsh4:t_r1;rscr_t;t_B11;rscr _ lsh[rscr,4];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B10;rscr _ lsh[rscr,5];t_t#(rscr);skpif[ALU=0];error;Rlsh6:t_r1;rscr_t;t_B9;rscr _ lsh[rscr,6];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B8;rscr _ lsh[rscr,7];t_t#(rscr);skpif[ALU=0];error;Rlsh8:t_r1;rscr_t; fp +pXNbq` _ ] ZpqYWUTyR Qq OLKaIHYF EQ C @pq?A=<8:90 7 6(3 10.- + * 'pq%|#"s k  c[SK  C ;pq  3 ^kernel3.mcNovember 13, 1978 10:43 AM%4t_B7;rscr _ lsh[rscr,10];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B6;rscr _ lsh[rscr,11];t_t#(rscr);skpif[ALU=0];error;Rlsh10:t_r1;rscr_t;t_B5;rscr _ lsh[rscr,12];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B4;rscr _ lsh[rscr,13];t_t#(rscr);skpif[ALU=0];error;Rlsh12:t_r1;rscr_t;t_B3;rscr _ lsh[rscr,14];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t;t_B2;rscr _ lsh[rscr,15];t_t#(rscr);skpif[ALU=0];error;Rlsh14:t_r1;rscr_t;t_B1;rscr _ lsh[rscr,16];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_t; fp +pXNbq`_ ] \YWUTyR Qq O LpqKaIHYFEQ C BI?A=<8:90 7 6( 3 pq10.-+ * (%|#"s k  c [pqSK C   3 ^kernel3.mcNovember 13, 1978 10:43 AM%5t_RHIGH1;rscr _ lsh[rscr,17];t_t#(rscr);skpif[ALU=0];error; fp +pXNbq`_ ] \b X M(kernel3.mcNovember 13, 1978 10:43 AM%6* October 20, 1978 10:32 AMTlsh:t_rscr_B15;noop;t_lsh[t,0];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B14;t_lsh[t,1];t_t#(rscr);skpif[ALU=0];error;Tlsh2:t_r1;rscr_B13;t_lsh[t,2];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B12;t_lsh[t,3];t_t#(rscr);skpif[ALU=0];error;Tlsh4:t_r1;rscr_B11;t_lsh[t,4];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B10;t_lsh[t,5];t_t#(rscr);skpif[ALU=0];error;Tlsh6:t_r1;rscr_B9;t_lsh[t,6];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B8;t_lsh[t,7];t_t#(rscr); fp +pXN bq `pq] \Z Y W URQqO Ni L Ka HYpqFEQC BI @ ?A<8:90 7 6( 4 1pq0.- + * (%|#"s  k  pq[S  K  ;  3  ^kernel3.mcNovember 13, 1978 10:43 AM%7skpif[ALU=0];error;Tlsh8:t_r1;rscr_B7;t_lsh[t,10];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B6;t_lsh[t,11];t_t#(rscr);skpif[ALU=0];error;Tlsh10:t_r1;rscr_B5;t_lsh[t,12];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B4;t_lsh[t,13];t_t#(rscr);skpif[ALU=0];error;Tlsh12:t_r1;rscr_B3;t_lsh[t,14];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_B2;t_lsh[t,15];t_t#(rscr);skpif[ALU=0];error;Tlsh14:t_r1;rscr_B1;t_lsh[t,16];t_t#(rscr);skpif[ALU=0];error;t_r1;rscr_RHIGH1;t_lsh[t,17]; fp +pXNbq ` ]pq\ZY W U TyQqONi L Ka I FpqEQCBI @ ?A =:907 6( 4 3  0pq.-+ * ( '#"s k  c [pqS K  C ;  3  ^kernel3.mcNovember 13, 1978 10:43 AM%8t_t#(rscr);skpif[ALU=0];error; fp +pXNbq ` _F ]K  !kernel3.mcNovember 13, 1978 10:43 AM%9* October 20, 1978 10:12 AM%KEEP 100000 IN Q FOR THESE TESTS !!!%Rrsh:Q_RHIGH1;GOTO[Rrsh1];* Temporary EXPEDIENTrscr_Q;t_RHIGH1;rscr _ rsh[rscr,0];t_t#(rscr);skpif[ALU=0];error;Rrsh1:rscr_Q;t_B1;rscr _ rsh[rscr,1];t_t#(rscr);skpif[ALU=0];error;Rrsh2:rscr_Q;t_B2;rscr _ rsh[rscr,2];t_t#(rscr);skpif[ALU=0];error;rscr_Q;t_B3;rscr _ rsh[rscr,3];t_t#(rscr);skpif[ALU=0];error;Rrsh4:rscr_Q;t_B4;rscr _ rsh[rscr,4];t_t#(rscr);skpif[ALU=0];error;rscr_Q;t_B5;rscr _ rsh[rscr,5];t_t#(rscr);skpif[ALU=0];error;Rrsh6:rscr_Q;t_B6;rscr _ rsh[rscr,6];t_t#(rscr);skpif[ALU=0]; fp +pXN bq `_$ ] \pqZY +WUTyR Qq O LpqKaIHYF EQ C @pq?A=<8: 90 743 10 . - *pq('%|# "s  c[  S pqC ;  3 Z 0%^kernel3.mcNovember 13, 1978 10:43 AM%10error;rscr_Q;t_B7;rscr _ rsh[rscr,7];t_t#(rscr);skpif[ALU=0];error;Rrsh8:rscr_Q;t_B8;rscr _ rsh[rscr,10];t_t#(rscr);skpif[ALU=0];error;rscr_Q;t_B9;rscr _ rsh[rscr,11];t_t#(rscr);skpif[ALU=0];error;Rrsh10:rscr_Q;t_B10;rscr _ rsh[rscr,12];t_t#(rscr);skpif[ALU=0];error;rscr_Q;t_B11;rscr _ rsh[rscr,13];t_t#(rscr);skpif[ALU=0];error;Rrsh12:rscr_Q;t_B12;rscr _ rsh[rscr,14];t_t#(rscr);skpif[ALU=0];error;rscr_Q;t_B13;rscr _ rsh[rscr,15];t_t#(rscr);skpif[ALU=0];error;Rrsh14:rscr_Q;t_B14;rscr _ rsh[rscr,16];t_t#(rscr); fp +pXNbq_]\Z Y W TypqRQqONi L KaHYFEQC BI @ =pq<8:907 6( 410.- + * 'pq%|#"s k [S  K Cpq ;  3 * ^kernel3.mcNovember 13, 1978 10:43 AM%11skpif[ALU=0];error;rscr_Q;t_B15;rscr _ rsh[rscr,17];t_t#(rscr);skpif[ALU=0];error; fp +pXNbq `]\ZY W Uz T2 2kernel3.mcNovember 13, 1978 10:43 AM%12* October 20, 1978 10:13 AMTrsh:GOTO[Trshift1];* Temporary EXPEDIENTt_rscr_RHIGH1;NOOP;T_rsh[t,0];t_t#(rscr);skpif[ALU=0];error;Trshift1:t_rhigh1;rscr_B1;t_rsh[t,1];t_t#(rscr);skpif[ALU=0];error;Trsh2:t_rhigh1;rscr_B2;t_rsh[t,2];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B3;t_rsh[t,3];t_t#(rscr);skpif[ALU=0];error;Trsh4:t_rhigh1;rscr_B4;t_rsh[t,4];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B5;t_rsh[t,5];t_t#(rscr);skpif[ALU=0];error;Trsh6:t_rhigh1;rscr_B6;t_rsh[t,6];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B7; fp +pXN bq `pq]+\ ZY W U Ty QqpqONiL Ka I HY EQpqCBI@ ?A = <89076( 4 3 1 .pq-+* ( ' %|"s k  c  pqSK  C   32 0%^kernel3.mcNovember 13, 1978 10:43 AM%13t_rsh[t,7];t_t#(rscr);skpif[ALU=0];error;Trsh8:t_rhigh1;rscr_B8;t_rsh[t,10];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B9;t_rsh[t,11];t_t#(rscr);skpif[ALU=0];error;Trsh10:t_rhigh1;rscr_B10;t_rsh[t,12];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B11;t_rsh[t,13];t_t#(rscr);skpif[ALU=0];error;Trsh12:t_rhigh1;rscr_B12;t_rsh[t,14];t_t#(rscr);skpif[ALU=0];error;t_rhigh1;rscr_B13;t_rsh[t,15];t_t#(rscr);skpif[ALU=0];error;Trsh14:t_rhigh1;rscr_B14;t_rsh[t,16];t_t#(rscr);skpif[ALU=0];error;t_rhigh1; fp +pXNbq ` _ ] ZpqYWU Ty R QqNiLKa I HY F CpqBI@?A = <8 :76(4 3 1 0 -pq+*( ' %| # k c  [ SpqK C   ; 3 ^kernel3.mcNovember 13, 1978 10:43 AM%14rscr_B15;t_rsh[t,17];t_t#(rscr);skpif[ALU=0];error; fp +pXNbq` _ ] \\ ZC  (kernel3.mcNovember 13, 1978 10:43 AM%15* October 20, 1978 10:14 AM%These tests work by cycling by 0, 1, ...17B. The predicted resultis kept in RSCR2 and the actual result XOR's w/ predicted result iskept in T. Note that each test is done twice: once w/ one "1" bit and allthe rest "0" bits, and once w/ one "0" bit and all the rest "1" bits.FOR THESE TESTS WE WILL REDEFINE R01 TO BE RM2 (-2)!%TRlcyTest:RM[rm2,IP[R01]];rm2 _ CM2;t_r0;rscr2_B15;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,0];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB15;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,0];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B14;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,1];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB14;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,1];t_t#(rscr2);skpif[alu=0];error;TRlcy2:t_r0;rscr2_B13;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,2];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB13;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,2];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B12;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,3];t_t#(rscr2);skpif[alu=0];error; fp +pXN bq `_A]C\IZEW4 U TypqRQq NiL +Ka I HY FEQC +BI@ ?A =:90 +7 6( 4 3 10 +.- + * 'pq%|# +"s  k c +[ S C +  ;   3 5^kernel3.mcNovember 13, 1978 10:43 AM%16t_rm1;rscr2_NB12;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,3];t_t#(rscr2);skpif[alu=0];error;TRlcy4:t_r0;rscr2_B11;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,4];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB11;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,4];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B10;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,5];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB10;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,5];t_t#(rscr2);skpif[alu=0];error;TRlcy6:t_r0;rscr2_B9;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,6];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB9;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,6];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B8;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,7];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB8;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,7];t_t#(rscr2);skpif[alu=0]; fp +pXNbq` +_] \ Z WpqUTy +R Qq O NiLKa +IHY F EQBI@ +?A = <8 :907 +6(4 3 1 .pq-++* ( ' %|#"s + k  c[+S  K C + ;  3 B 5^kernel3.mcNovember 13, 1978 10:43 AM%17error;TRlcy8:t_r0;rscr2_B7;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,10];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB7;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,10];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B6;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,11];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB6;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,11];t_t#(rscr2);skpif[alu=0];error;TRlcy10:t_r0;rscr2_B5;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,12];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB5;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,12];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B4;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,13];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB4;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,13];t_t#(rscr2);skpif[alu=0];error;TRlcy12:t_r0;rscr2_B3;* RSCR2 _ PREDICTED RESULT fp +pXNbq _pq]\+ZY W UTyR +QqO Ni LIHY+FEQ C BI@?A +=<8 : 90 6(pq43 +10 . -+* +(' %| # k+c  [S +K  C ;pq  3+* 5^kernel3.mcNovember 13, 1978 10:43 AM%18t_lcy[t,r1,14];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB3;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,14];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B2;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,15];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB2;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,15];t_t#(rscr2);skpif[alu=0];error;TRlcy14:t_r0;rscr2_B1;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,16];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB1;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,16];t_t#(rscr2);skpif[alu=0];error;t_r0;rscr2_B0;* RSCR2 _ PREDICTED RESULTt_lcy[t,r1,17];t_t#(rscr2);skpif[alu=0];error;t_rm1;rscr2_NB0;* RSCR2 _ PREDICTED RESULTt_lcy[t,rm2,17];t_t#(rscr2);skpif[alu=0];error; fp +pXNbq` _ ]\Z +YW U TyQqO+NiL Ka IHYF +EQC BI @ =pq<8:+907 6( 43 1 +0. - +('+%|# "s  k +c [  5Ukernel3.mcNovember 13, 1978 10:43 AM%19**October 20, 1978 10:06 AMRTlcyTest:*RSCR2 HOLDS THE PREDICTED RESULT, T HOLDSACTUAL RESULTt_r1;* rscr2, T _ [0,1] LCY[0]rscr2_B15;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,0];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB15;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,0];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B14;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,1];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB14;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,1];t_t#(rscr2);skpif[alu=0];error;RTlcy2:t_r1;rscr2_B13;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,2];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB13;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,2];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B12;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,3];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB12;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,3];t_t#(rscr2);skpif[alu=0];error;RTlcy4: fp +pXN bq ` _pq+* ] Z+Y +W U Ty RQqO +NiL Ka IFEQ +C BI @ ?A=<8 +:90 7 6( 3 pq10 +. - + *(' +%|# "s  c + [  SK +C   ; 3pqh C^kernel3.mcNovember 13, 1978 10:43 AM%20t_r1;rscr2_B11;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,4];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB11;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,4];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B10;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,5];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB10;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,5];t_t#(rscr2);skpif[alu=0];error;RTlcy6:t_r1;rscr2_B9;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,6];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB9;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,6];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B8;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,7];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB8;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,7];t_t#(rscr2);skpif[alu=0];error;RTlcy8:t_r1;rscr2_B7;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,10];t_t#(rscr2);skpif[alu=0]; fp +pXNbq` +_ ] \ ZYW +UTy R QqNiL +Ka I HY FEQC +BI@ ?A = :pq907+6( 4 3 10. +-+ * (%|#+"s  k c +[ S  pqC+ ;  3 > 3^kernel3.mcNovember 13, 1978 10:43 AM%21error;t_rm2;rscr2_NB7;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,10];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B6;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,11];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB6;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,11];t_t#(rscr2);skpif[alu=0];error;RTlcy10:t_r1;rscr2_B5;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,12];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB5;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,12];t_t#(rscr2);skpif[alu=0];error;t_r1;rscr2_B4;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,13];t_t#(rscr2);skpif[alu=0];error;t_rm2;rscr2_NB4;* rscr2 _ PREDICTED RESULTt_lcy[rm1,t,13];t_t#(rscr2);skpif[alu=0];error;RTlcy12:t_r1;rscr2_B3;* rscr2 _ PREDICTED RESULTt_lcy[r0,t,14];t_t#(rscr2);skpif[alu=0];error;t_rm2;RSCR2_NB3;* RSCR2 _ PREDICTED RESULTt_lcy[rm1,t,14];t_t#(rscr2); fp +pXNbq`_ +]\ Z YUTy+RQq O NiLKa +IHY F EQ BIpq@?A+=<8 : 9076( +43 1 0-++*( ' %|#"s + k  c [pqS+K  C ; +  3 @ 5^kernel3.mcNovember 13, 1978 10:43 AM%22skpif[alu=0];error;t_r1;RSCR2_B2;* RSCR2 _ PREDICTED RESULTt_lcy[r0,t,15];t_t#(rscr2);skpif[alu=0];error;t_rm2;RSCR2_NB2;* RSCR2 _ PREDICTED RESULTt_lcy[rm1,t,15];t_t#(rscr2);skpif[alu=0];error;RTlcy14:t_r1;RSCR2_B1;* RSCR2 _ PREDICTED RESULTt_lcy[r0,t,16];t_t#(rscr2);skpif[alu=0];error;t_rm2;RSCR2_NB1;* RSCR2 _ PREDICTED RESULTt_lcy[rm1,t,16];t_t#(rscr2);skpif[alu=0];error;t_r1;RSCR2_B0;* RSCR2 _ PREDICTED RESULTt_lcy[r0,t,17];t_t#(rscr2);skpif[alu=0];error;t_rm2;RSCR2_NB0;* RSCR2 _ PREDICTED RESULTt_lcy[rm1,t,17];t_t#(rscr2);skpif[alu=0];error;RTlcyDone:r01 _ NOT(r10);* REDEFINE r01 !!!!!!! fp +pXNbq `]\+ZY W UTyR +QqO Ni L IpqHYF+EQC BI @?A= +<8: 90 743 +10 . -+* +(' %| # pqk+ 5Jkkernel3.mcNovember 13, 1978 10:43 AM%23* November 3, 1978 6:43 PM%rcy16, lcy16Test the 16 bit cycles with selectedbit values. This is not an exhaustive test.%rcyTest:* test 16 bit right cyclet _ rcy[r01, r01, 1];t # (r10);skpif[ALU=0];rcy16Err1:* r10 rcy 1 should be r01error;t _ r01;t _ rcy[t, t, 1];* try it again from tt # (r10);skpif[ALU=0];rcy16Err2:* r10 rcy 1 should be r01. (done fromerror;* t this time)t _ rcy[r1, r1, 1];t # (rhigh1);skpif[ALU=0];rcy16Err3:* 1 rcy 1 should be 100000Berror;t _ r1;t _ rcy[t, t, 1];t # (rhigh1);skpif[ALU=0];rcy16Err4:* 1 rcy 1 should be 100000B. (done from terror;* time).t _ rcy[r10, r10, 1];t # (r01);skpif[ALU=0];rcy16Err5:* r10 rcy 1 should be r01error;t _ r10;t _ rcy[t, t, 1];* t _ r10 rcy 1t # (r01);skpif[ALU=0];rcy16Err6:* r10 rcy 1 should be r01error;* done from t this time.t _ rcy[r01, r01, 2];t # (r01);skpif[ALU=0];rcy16Err7:* r01 rcy 2 should be r01error;t _ rcy[r01, r01, 3];t # (r10);skpif[ALU=0];rcy16Err8:* r01 rcy 3 should be r10error;t _ rcy[r01, r01, 10];t # (r01); fp +pXN bq `_p +q$ ]+ \ Zp+qYW U Typ +qRONi+L Ka Ip +q%HY+ EQC BI @p +q?A<8:90 7 6(p +q)4+10 . -p +q+('+%| # "sp +q +c  [p +qK  Cp +q  3  8^kernel3.mcNovember 13, 1978 10:43 AM%24skpif[ALU=0];rcy16Err9:* r01 rcy 10 should be r01error;lcyTest:t _ lcy[r01, r01, 1];t # (r10);skpif[ALU=0];lcy16Err1:* r01 lcy 1 should be r10error;t _ lcy[rhigh1, rhigh1, 1];t # (r1);skpif[ALU=0];lcy16Err2:* 100000B lcyd 1 should be 1error;t _ lcy[r1, r1, 1];t#(2c);skpif[ALU=0];lcy16Err3:* 1 lcy 1 should be 2error;t _ lcy[r10, r10, 1];* t _ r10 lcy 1t # (r01);skpif[ALU=0];lcy16Err4:* r10 lcy 1 should be r01error;t _ lcy[r10, r10, 2];t # (r10);skpif[ALU=0];lcy16Err5:* r10 lcy 2 should be r10error;t _ lcy[r10, r10, 3];t # (r01);skpif[ALU=0];lcy16Err6:* r10 lcy 3 should be r01error;t _ lcy[r10, r10, 4];t # (r10);skpif[ALU=0];lcy16Err7:* r10 lcy 4 should be r10error;t _ lcy[r10, r10, 10];t # (r10);skpif[ALU=0];lcy16Err8:* r10 lcy 10 should be r10error; fp +pXNbq `p +q_ \pZqY W Up +qTyQqONi Lp +qKaHYFEQ Cp +qBI?A+= <8 :p +q906(4 3 1p +q0-+ * (p +q'#"s  kp +q[  Sp +q 0Ukernel3.mcNovember 13, 1978 10:43 AM%25* November 13, 1978 10:40 AM%cycleTestTest the cycle machinery by generating all possible values forthe r, t, and count fields in Shc (6 bits). The 16-bit data patterns must test all possible starting positions (ie., bit 0, bit1, ...). Furthermore, set the "other word" to all 1s when single one-bits are being tested, and set it to all zeros whensingle zero bits are being tested. Since we test cycling, we don't set any of the mask fields in ShC.SHC: TYPE = MACHINE DEPENDENT RECORD[ShifterIgnores: IN[0..3],-- bits 0, 1a: IN [0..1],-- bit 2, shA select. 1 ==> "select T"b: IN [0..1],-- bit 3, shB select. 1 ==> "select T"Count: IN [0..17B],-- bits 4:7, shift countRMask: IN [0..17B],-- bits 8:11LMask: IN [0..17B],-- bits 12:15];shcVals: IN [0..77B];-- iterate thru all possible counts, sha, shbFOR pats IN NPats DOFOR shcVal In SHCVals DOShc.a _ shcVals AND 40B;Shc.b _ shcVals AND 20B;Shc.count _ shcVals AND 17B;r _ getPattern[pats];t _ IF numberOfZeroBitsGr1[r] THEN -1 ELSE 0;result _ doShift[];expected _ simulateCycle[t,r,shcVal];IF result # expected THEN SIGNAL BadShift[result, expected, shcVals];ENDLOOP;-- end of shcVals loopENDLOOP;-- end of pats loopsimulateCycle: PROCEDURE[t, r: WORD, shcVal: SHCVals] RETURNS [expected: WORD] =BEGINtCycle: CARDINAL = 60B;-- 2 highest bits in shcVal are 1rCycle: CARDINAL = 0;-- 2 hightest bits in shcVal are 0trCycle: CARDINAL = 40B;-- highest bit in shcVal is 1rtCycle: CARDINAL = 20BB;-- 2nd highest bit in ShcVal is 1shAB _ shcVal AND 60B;SELECT shAB INTOtCycle=> BEGINleft _right_t; END,rCycle=> BEGINleft _ right _ r; END,trCycle=> BEGINleft _ t, right _ r; END,rtCycle=> BEGINleft _ r;right _ t; END,END;shiftCount _ shcVal AND 17B;saveMask _ SELECT shiftCount INTO1=>100000;2=>140000B;3=>160000B;4=>170000B;5=>174000B;6=>176000B;7=>177000B;8=>177400B;9=>177600B;10=>177700B; fp +pXN bq `_p+q> ] \x Ze Wpq!U+ Ty +&R +&Qq+O+ Ni+ L Kapq +- HYFEQCBI@?A-=<8%:E90+7+ 6(p qB43 pq+!1pq +"0pq+.pq+!-+* (' %|#"s kc[! S  K  C   ;   3 T D^ kernel3.mcNovember 13, 1978 10:43 AM%2611=>177740B;12=>177760B;13=>177770B;14=>177774B;15=>177776B;0=>177777B,END;savedValue _ left AND saveMask;right _ LeftShift[right, shiftCount];savedValue _ RightShift[right, 16-shiftCount];result _ savedValue OR left;END;numberOfZeroBitsGr1: PROCEDURE[ x: WORD] RETURNS[result: BOOLEAN] =BEGINcount _ 0;FOR i IN [0..15] DOIF (x AND 1) =0 THEN count _ count + 1;x _ RightShift[x,1];ENDLOOP;result _ IF count >1 THEN TRUE ELSE FALSE;END;% fp +pXNbq ` _ ] \ Z YWU%Ty.RQq Opq/NiL KaI'HYFEQ*C @ >38)gkernel3.mcNovember 13, 1978 10:43 AM%27%November 17, 1978 2:39 PMTEST RF AND WFShC: TYPE = MACHINE DEPENDENT RECORD [IGNORE: TYPE = [0..7B]SHIFTCOUNT: TYPE = [0..37B]RMASK: TYPE = [0..17B]LMASK: TYPE = [0..17B]]MesaDescriptor: TYPE = MACHINE DEPENDENT RECORD[ -- this is the value stored w/ rf_, wf_IGNORE: TYPE = [0..377B] -- IGNORE FIRST BYTEPOS: TYPE = [0..17B]-- RIGHT SHIFT OF POS WILL RIGHT JUSTIFY THE FIELDSIZE: TYPE = [0..17B]-- LENGTH OF FIELD IN BITS]THIS TEST PROCEEDS BY WRITING ShC W/ ALL POSSIBLE RF AND WF VALUES. THENShC IS READ AND CHECKED TO MAKE SURE THAT IT WAS LOADED PROPERLY.FOR I IN [0..377B] DORF_I;RSCR_SHC;SIZE _ I AND 17B;POS _ BITSHIFT[I,-4] AND 17B;IF RSCR.LMASK # (16-SIZE-1) THEN ERROR;-- BAD LMASKIF RSCR.RMASK # 0 THEN ERROR;-- BAD RMASKIF RSCR.SHIFTCOUNT # (16+pos+size+1) THEN ERROR;-- BAD SHIFT COUNT (Actually this computation isn't quite right.* let count = 16+pos+size+1. realCount _ (count and 17b).* IF (realCount and 17b) #0 then realCount _ realCount OR 20B. This funny computation* accommodates hardware limitations associated w/ carry across boards.-- now test wfWF_I;RSCR_SHC;IF RSCR.RMASK # (16-POS-SIZE-1) THEN ERROR;-- BAD RMASKIF RSCR.LMASK NE POS THEN ERROR;-- BAD LMASKIF RSCR.SHIFTCOUNT # (16-pos-size-1) THEN ERROR;-- BAD SHIFT COUNTENDLOOP;%RM[r4BitMsk,IP[R01]];r4BitMsk _ 17C;* RENAME R01 AS r4BitMsk !!!RM[lastShC, IP[RSCR]];* RENAME RSCR AS lastShCRFWFtest:Q_R0;* Q WILL HOLD THE INDEX VARIABLEt_377C;CNT_t;* LOOP LIMITRFTESTL:t_Q;RF_t;lastShC_SHC;* CHECK LMASK fp +pXN bq ` ] Z&YWUTyR O4p$Niq-L 2Ka I FH EQABI@?A=<8:'5 90. 70< 6(. 49 3 U 1F. -+*+5 (. '0<# "s k + c+ [pq+S+ pqC ; 3  ?u^kernel3.mcNovember 13, 1978 10:43 AM%28T_ (r4BitMsk)AND (Q);* COMPUTE LMASK (= 16-SIZE-1) FROM INDEX VARrscr2_t;* rscr2 _ sizet_17C;* 16-1rscr2 _ t - (rscr2);* rscr2 _ expected Lmask = 16-size-1t _ (lastShC) and (17c);* t _ Lmask from ShCt # (rscr2);branch[.+2, ALU=0];RFLMASK:* t = Lmask from ShC, rscr2 = expected Lmaskerror;* LMASK FIELD WRONG IN ShC* CHECK RMASKt_(lastShC) and (360c);* t = isolated Rmask field of ShCskpif[ALU=0];RFRMASK:error;* RMASK FIELD NOT 0* CHECK SHIFT COUNT = 16+pos+size+1 (Actually this computation isn't quite right.* let count = 16+pos+size+1. realCount _ (count and 17b).* IF (realCount and 17b) #0 then realCount _ realCount OR 20B. This funny computation* accommodates hardware limitations associated w/ carry across boards.rscr2_ (Q);t_r4BitMsk;rscr2 _ rsh[rscr2,4];rscr2 _ t AND (rscr2);* rscr2 = POSt _ 21c;* 16 + 1t _ t + (rscr2);* 16 + 1 + posrscr2 _ q;rscr2 _ (rscr2) and (17c);* isolate sizerscr2 _ t + (rscr2);* rscr2 _ 16 + 1 + pos + sizerscr2 _ (rscr2) and (17c);* isolate to 17 bitsskpif[alu=0];* see if bit 0 of count is onerscr2 _ (rscr2) or (20c);* set bit0 of count if count[1:4]#0rscr2 _ (rscr2) and (17c);* isolate result to 5 bitst_ rsh[LastShC, 10];RFSHIFTC:t#(rscr2);* t=value from LastShC, rscr2 = computed valueskpif[ALU=0];error;* BAD SHIFT COUNT fp +pXNbq+,`+ _+]+$\+Z Y Wpq+,U+ R Qq+!O NipqL+ IQ HY9 FU EQFC BI @?A+ =+<8+ : 90+ 7+6(+4 +3 +#1+. -pq+ +.* (+ &CARkernel3.mcNovember 13, 1978 10:43 AM%29* June 28, 1978 5:06 PM* NOW TEST WFWFTEST:t_Q;WF_t;lastShC_SHC;* CHECK LMASK: COMPUTE posrscr2 _ q;noop;t _ rsh[rscr2,4];rscr2 _ t and (r4BitMsk);* isolate pos bits in rscr2t_lastShC;t _ t AND (r4BitMsk);* T_ LMASKWFLMASK:t#(rscr2);* t=LastShC's Lmask, rscr2 = computed valuebranch[.+2, ALU=0];error;* SHC'S LMASK # pos* CHECK THAT RMASK = 16 - pos - size -1rscr2 _ q;t _ (r4BitMsk) and (q);* isolate size in trscr2 _ rsh[rscr2,4];* rscr2 _ posrscr2 _ (rscr2) + t;* rscr2 _ pos + sizet _ 17c;* t _ 16 -1rscr2 _ t - (rscr2);* rscr2 _ 16 - pos - size - 1rscr2 _ (rscr2) and (17c);* isolate to 17 bitst _ rsh[lastShC,4];* t = ShC's shift countt _ t and (r4BitMsk);WFRMASK:t#(rscr2);* t = ShC's shift countskpif[ALU=0];* rscr2 = 16-pos-size-1error;* RMASK NE (16-POS-SIZE-1)* CHECK SHIFT COUNT=16-pos-size-1t _ rsh[lastShC,10];* put ShC's shift count into tt _ t and (37c);t#(rscr2);* t = ShC's shift countskpif[ALU=0];* rscr2 = 16-pos-size-1, as computed aboveWFSHIFTC:* for the Rmask checkerror;* SHC'S SHIFTCOUNT # POSrscr2_(R1) + (Q);loopUntil[CNT=0&-1,RFTESTL],Q_(rscr2);RFXITL:R01 _ NOT(R10);* RESET R01 !!!!!! fp +pXN bq ` ]pq\ZY UTy RQqO+L Ka+ IpqHY ++FEQ+ BI'@ ?A+=+ <8+:+ 90+7+6(+4 1pq0 +. +-+ *!'+%|# +"s +* pq+k+[& pq+ ;Ukernel3.mcNovember 13, 1978 10:43 AM%30* October 20, 1978 10:23 AM%TEST ALU SHIFT OPERATIONS%* TEST RESULT _ ALU RSH 1 (RESULT[0] _ 0)aluRSH:r01 _ not(r10);* RESET r01 !!!! INCASE WE SKIPPED RFXITLt_(PD_(r1))rsh 1;t_t#(r0);skpif[ALU=0];error;* 1 RSH[1] SHOULD BE 0t_(PD_(rm1))rsh 1;rscr_77777C;t_t#(rscr);skpif[ALU=0];error;* -1 RSH[1] SHOULD BE 77777Bt_(PD_r10)rsh 1;t_t#(r01);skpif[ALU=0];error;* (ALTERNATING 10) rsh 1 SHOULD BE (ALT. 01)* TEST RESULT _ ALU RCY[1] (RESULT[0]_ALU[15])aluRCY:t_(PD_rm1)rcy 1;t_t#(rm1);skpif[ALU=0];error;* -1 RCY[1] SHOULD BE -1t_(PD_r0)rcy 1;t_t#(r0);skpif[ALU=0];error;* 0 RCY[1] SHOULD BE 0t_(PD_r10)rcy 1;t_t#(r01);skpif[ALU=0];error;* (ALTERNATING 10) RCY[1] SHOULD BE (ALT 01)t_(PD_r01)rcy 1;t_t#(r10);skpif[ALU=0];error;* (ALT 01) RCY[1] SHOULD BE (ALT 10)* REST RESULT _ ALU Arsh 1 (RESULT[0] _ ALU[0]) (SIGN PRESERVING)aluARSH:t_(PD_rm1)Arsh 1;t_t#(rm1);skpif[ALU=0];error;* -1 ARSH SHOULD BE -1t_(PD_r0)Arsh 1;t_t#(r0);skpif[ALU=0];error;* 0 ARSH SHOULD BE 0t_(PD_rhigh1)Arsh 1; fp +pXN bq `_ \ Z) YpqW+)UTyR Qq+NiL Ka I HY+EQC BI @+, =. <8pq:90 7 6(+3 10 .++* ( '+,#"s  k+$ cA pq[ S +C  ;+ 3 A^kernel3.mcNovember 13, 1978 10:43 AM%31rscr_140000C;t_t#(rscr);skpif[ALU=0];error;* 100000 ARSH SHOULD BE 140000t_rhigh1;rscr_t+(r01);t_(PD_r10)Arsh 1;t_t#(rscr);skpif[ALU=0];error;* (ALT. 10) ARSH SHOULD BE(ALT. 01+100000)* TEST RESULT _ ALU lsh 1aluLSH:t_(PD_rhigh1)lsh 1;t_t#(r0);skpif[ALU=0];error;* 100000 LSH SHOULD BE 0aluLSHb:t_(PD_r1)lsh 1;rscr_(r1)+(r1);t_t#(rscr);skpif[ALU=0];error;* 1 LSH SHOULD BE 2aluLSHc:t_(PD_r01)lsh 1;t_t#(r10);skpif[ALU=0];error;* (ALT. 01) LSH SHOULD BE (ALT. 10)aluLSHd:t_(PD_rm1)lsh 1;rscr_CM2;t_t#(rscr);skpif[ALU=0];error;* -1 LSH SHOULD BE -2* TEST RESULT _ ALU LCY1aluLCY:t_(PD_rm1)lcy 1;t_t#(rm1);skpif[ALU=0];error;* -1 LCY SHOULD BE -1aluLCYb:t_(PD_r10)lcy 1;t_t#(r01);skpif[ALU=0];error;* (ALT. 10) LCY SHOULD BE (ALT. 01)aluLCYc:t_(PD_r01)lcy 1;t_t#(r10);skpif[ALU=0];error;* (ALT. 01) LCY SHOULD BE (ALT. 10)aluLCYd: fp +pXNbq ` _ ]+ZY WU Ty R+* O NipqLKaI HY+ EQpqCBI@ ?A =+ :pq907 6( 4+# 1pq0.- + *+ ' %|pq#"s  k+ cpq[  S+# KpqC   ;+# 3pqd ?^kernel3.mcNovember 13, 1978 10:43 AM%32t_(PD_r0)lcy 1;t_t#(r0);skpif[ALU=0];error;* 0 LCY SHOULD BE 0aluLCYe:t_(PD_r1)lcy 1;rscr_(r1)+(r1);t_t#(rscr);skpif[ALU=0];error;* 1 LCY SHOULD BE 2 fp +pXNbq`_ ]+ ZpqYWU Ty R+ Q*.?kernel3.mcNovember 13, 1978 10:43 AM%33* October 20, 1978 10:24 AM%EXHAUSTIVE TEST OF ALU SHIFT FUNCTIONSFOR Q IN[0..177777B] DOrscr2_Q rsh 1;t_predictedRSH[I];IF t_(T XOR rscr2) THEN ERROR;rscr2_Q )rcy 1;t_predictedRCY[I];IF t_(T XOR rscr2) THEN ERROR;rscr2_Q Arsh 1;t_predictedARSH[I];IF t_(T XOR rscr2) THEN ERROR;rscr2_Q lsh 1;t_predictedLSH[I];IF t_(T XOR rscr2) THEN ERROR;rscr2_Q rsh 1;t_predictedRSH[I];IF t_(T XOR rscr2) THEN ERROR;rscr2_Q lcy 1;t_predictedLCY[I];IF t_(T XOR rscr2) THEN ERROR;ENDLOOP;%aluSHTEST:Q_r0;* USE Q AS LOOP VARIABLEaluSHL:* TOP OF LOOP* RSH TESTrscr_Q;t_(PD_rscr)rsh 1;rscr_rsh[rscr,1];t_t#(rscr);branch[.+2,ALU=0];RSHER:error;* PREDICTED RESULT DIFFERENT FROM REAL ONE* RCY TESTrscr_Q;* Q IS LOOP VARIABLEt_(PD_rscr)rcy 1;rscr2_t;* REAL RESULT IN rscr2t_rsh[rscr,1];skpif[R EVEN], (PD_rscr);* ADD HIGH BIT IF NECESSARYt_t+(rhigh1);* PREDICTED RESULT IN Tt_t#(rscr2);branch[.+2,ALU=0];RCYER:error;* T _ (PREDICTED T) XOR rscr2* ARSH TESTrscr_Q;* Q IS LOOP VARIABLE fp +pXN bq `_& \Z YWTyRQqNiLKaHY FEQBI @?A<8 :906( 4 3 pq1+ .pq+ + *('%| # "spq +*  c+[+ S+ +K  Cpq+  3+ D8^kernel3.mcNovember 13, 1978 10:43 AM%34t_(PD_rscr)Arsh 1;rscr2 _ T;* rscr2 = ACTUAL RESULTt_rsh[rscr,1];PD_Q;* ADD SIGN BIT IF REQUIREDskpUnless[ALU<0];* ADD SIGN BIT IF REQUIREDt_t+(rhigh1);t_t#(rscr2);skpif[ALU=0];ARSHER:error;* t_(PREDICTED T) XOR rscr2* LSH TESTrscr_Q;* Q IS LOOP VARIABLErscr2_(PD_Q)lsh 1;* rscr2 = ACTUAL RESULTt_lsh[rscr,1];t_t#(rscr2);skpif[ALU=0];LSHER:error;* t_ (PREDICTED T) XOR rscr2* LCY TESTt_rscr _ Q;* Q IS LOOP VARIABLErscr2 _ (PD_t)lcy 1;* rscr2 = ACTUAL RESULTt_lsh[rscr,1];* t_ PREDICTED RESULTrscr_(rscr);skpUnless[ALU<0];t_t+(r1);* t_ T+ 1 FOR CYCLED BIT 0t_t#(rscr2);skpif[ALU=0];LCYER:error;* T _ (PREDICTED T) XOR rscr2t_(r1)+(Q);dblBranch[.+1,aluSHL,ALU=0],Q_t;goto[afterkernel3]; fp +pXNbq` +_ ]+\+Z W U TypqR+ O Ni+L+Ka I HY FpqEQ+ BI @ +?A+= +<8 :90+7 6( 4pq3 +0 . - +E4<kernel4.mcSeptember 22, 1986 6:03 PM%1%September 22, 1986 6:04 PMFix bug in label for stk&+4Err0 to be stk&plus4Err0July 14, 1979 4:53 PMFix bug in computation of correct value for stkp after performing stack+1_.May 8, 1979 11:53 AMAdd bypass checking to stack test.January 25, 1979 1:12 PMAdd call to checkTaskNum at beginKernel4 to skip the stack tests when we're not executing in task 0.%top level;%CONTENTSTESTDESCRIPTIONstkTesttest all stack operationscarry20Testtests CARRY20 functionxorCarryTesttest XORCARRY function (CIN to bit0, provided by ALUFM)useSavedCarrytest function (use aluCarry from preeceding instr as CINmultiplyTesttest multiply step fcn (affects Q, result. its a slowbranch, too)dividetest divide step fcn (affects Q, result)cdividetest divide step fcn (affects Q, result)slowBRtests 8-way slow dispatch%beginKernel4:call[checkTaskNum], t _ r0;skpif[ALU=0];branch[stkXitTopL];* don't try task 0 tests.Hold&TaskSim _ R0;*Turn off hold and task simulators to avoid errors in task 12.fp (-X@]N bq `_3 ]\K ZY" WU p qp q< Ty R ONi Ka HY` F ` EQ `7 C `8 BI `A @`( ?A`( =` <8 :p 90q7 6(+4+> 1UCT6kernel4.mcSeptember 22, 1986 6:03 PM%2* May 8, 1979 11:53 AM%TEST STKP PUSH AND POP OPERATIONS-- I AND STKP SHOULD BE INCREMENTING TOGETHER.-- notation: stack&+1[stkp] _ val : place val into stack[stkp], then increment stkp by 1-- stack+1[stkp] _ val : increment stkp by one, then place val into stack[stkp]-- The stragegy for this test is to perform all the various stack manipulations (+1, +2, +3,-- -1, -2, -3, -4, &+1, &+2, &+3, &-1, &-2, &-3, &-4) for every value of stkp that won't-- cause a hardware error (underflow). The test knows what to expect in RM by setting-- each rm location to its address (stack[i] _ i).%fp (-X@]N bq `1_! \. Zrq6 Yrq9 W\ UX TyV R2 Or N"4Gkernel4.mcSeptember 22, 1986 6:03 PM%3* July 14, 1979 4:53 PM%stkTestTest the various stack operations%mc[stkPMaxXC, 77];mc[pointers.stkOvf, b8];mc[pointers.stkUnd, b9];mc[pointers.stkErr, b8, b9];stkTest:* initialize the top2bits loopcall[iTopStkBits];stkTopL:* top of "top 2 bits of stkp" loopcall[nextTopStkBits];skpif[ALU#0];branch[stkXitTopL];noop;* This code writes the current stack with the address (stack[stkP] _ stkP).* It also checks that stkp_, _stack work properly.call[iStkPAddr];* initialize stack index [1..maxStkXC]stkIL:call[nextStkPAddr];* top of stk init loop. here we check stkp_ and _stack.skpif[ALU#0];branch[stkiXit];stkp _ t;* load stkpcall[chkStkErr];skpif[ALU=0];stkiErr0:* got stack underflow or overflowerror;call[getRealStkAddr], rscr _ t;t # (rscr);* compare real stkp with value we loadedskpif[ALU=0];stkiErr1:* t = tskp, rscr = value we loadederror;* This is a limited test of the bits in the stack memory: write zero, -1, alternating 10, 01t _ stack _ t-t;t _ t #(Q_stack) ;skpif[ALU=0];stkiErr2:* wrote zero, got back something elseerror;* Q = value from stackt _ rm1;stack _ t;t _ t #(Q_stack) ;skpif[ALU=0];stkiErr3:* wrote -1 got back something else.error;* t = bad bits Q = value from stackt _ r01;stack _ t;t _ t #(Q_stack) ;skpif[ALU=0];stkiErr4:* wrote r01 got back something else.error;* t = bad bits. Q = value from stackt _ r10;stack _ t;t _ t #(Q_stack) ;fp (-X@]N bq `@_p&q! ] \pq Zpq Ypq Wpq Up&q@Ty Rp&q"@Qq@O @Ni@L IK HY2@F&& EQp@Cq&7@BI @@@?A& @=@<8 :p&q!@90@6(@4 &(@3 1p&q"@0 -\@+@*@( 'p&q%@%|&@"s@ @k@ cp&q#@&#@@S @@K p&q$@C&$@ ;@ @ 3| :^kernel4.mcSeptember 22, 1986 6:03 PM%4skpif[ALU=0];stkiErr5:* wrote r10 got back something else.error;* t = bad bits. Q = value from stackt _ rscr;* t _ current indexstack_t;* stack[i] _i, then check itt # (Q_stack);skpif[ALU=0];stkiErr6:* wrote stkp from rscr. Q = value from stackerror;* read it into t. they aren't the samebranch[stkiL];stkiXit:noop;fp (-X@]N@bq `p&q$@_&$@\&@Z&@Y @W Up&q,@Ty&&@R Qqp@Oqb N"4Skernel4.mcSeptember 22, 1986 6:03 PM%5* July 14, 1979 4:53 PM* We have successfully written the stack using non incrementing and non decrementing* operations. Now we test stack&+1_, stack&-1_, stack+1_, stack-1_call[iStkPAddr];* init the main loop for the main teststkTestL:* top of main loopcall[nextStkPAddr];* get next stack index or exit loopskpif[alu#0];branch[stkTestXitL];stkp _ t;* stackP _ icall[chkStkErr];skpif[ALU=0];stkpErr10:* got stack underflow or overflowerror;rscr _ t and (77c);* isolate the index (exclude top 2 bits)(rscr)-(stkPMaxXC);* skip this test if it would cause overflowbranch[afterStkTest1, ALU=0];t # (Q_stack);* see if stack[stkp] = stkpskpif[ALU=0];* if not, an earlier execution of this loop clobberedstkpErr1:* the stack entry at location in t, or this is first timeerror;* thru, and the initialization didn't work properly.*Q=value from stack* stack&+1 stack&+1 stack&+1 stack&+1 stack&+1 stack&+1 stack&+1 stack&+1stack&+1 _ cm1;* stack[stackP] _ -1, then stackP _ stackP+1call[chkStkErr];skpif[ALU=0];stk&Plus1Err0:* got stack underflow or overflowerror;call[getRealStkAddr], rscr_t+1;* compare stackPAddr from Pointers w/ expected valt #(rscr);skpif[ALU=0];stkP1AddrErr:* auto increment of StackP failed. rscr = expected value,error;* t = value from Pointerst _ t # (Q_stack);skpif[ALU=0];stkP1ValErr:* value at stackp is bad. Q = value from stackerror;* t = expected val, rscr = stack's val from Pointerst _ rscr;* restore t* stack&-1 stack&-1 stack&-1 stack&-1 stack&-1 stack&-1 stack&-1 stack&-1 stack&-1stack&-1 _ t;* stack["i+1"] _ i+1, stackp _ i.call[chkStkErr];skpif[ALU=0];stkpErr12:* got stack underflow or overflowerror;call[getRealStkAddr], rscr _ t-1;t # (rscr);* compare expected stkP (rscr) withskpif[ALU=0];* actual stkp (t)stkM1AddrErr:* auto decrement failedfp (-X@]N bq `T _B@\&& Zp&q@Y&#@W @U@Ty& @Qq@O Nip &q!@L@I&(@HY&+@F@C &@BI &5 @p&q9@?A&4 =@ :pI@7q&,@6(@4 3 p &q!@1@.&2@- @+ *p &q9@(&@%|@# "sp &q.@ &4@k& cpR@[q &!@S@ Kp &q!@@!@ ; &#@ & 3p &q ;^kernel4.mcSeptember 22, 1986 6:03 PM%6error;t _ cm1;t _ t # (Q_stack);skpif[ALU=0];* see if original stack&+1 _ cm1 workedstkP1ValErr2:* stack&+1 seems to have clobbered theerror;* (i+1)th value. t = bad bits. Q = value from stackt _ rscr;* restore t(stack)_ t;* reset stk[stkp] to contain stkpcall[chkStkErr];skpif[ALU=0];stkpErr13:* got stack underflow or overflowerror;rscr _ t _ t+1;stkp _ t;* check the data modified during "stack&-1" instructiont _ t # (Q_stack);* compare tos with expected valuskpif[ALU=0];stkM1ValErr:*. Q = value from stackerror;* t = bad bits, rscr = expected valuet _ rscr _ (rscr)-1;* t, rscr _ "i"stkp _ t;* stkp is at i+1 now. Fix it.call[chkStkErr];skpif[ALU=0];stkpErr14:* got stack underflow or overflowerror;Q _ stack;* save stack valuestack _ t-t;PD_(stack);skpif[ALU=0];stkByPassErr0:* didn't notice that we just zeroed the stackerror;t _ cm1;stack _ cm1;PD _ (stack) # t;skpif[ALU=0];stkByPassErr1:* didn't notice that we just put all oneserror;* in the stack.stack _ Q;* restore stack* stack+1 stack+1 stack+1 stack+1 stack+1 stack+1 stack+1 stack+1 stack+1 stack+1rscr _ (rscr)+1;* compute expected stkp valuet _ cm1;stack+1 _ t;* stkp _ i+1, stack[stkp] _ -1call[chkStkErr];skpif[ALU=0];stkpErr15:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;fp (-X@]N@bq@_@]@\ &' Zp &q&@Y&3@U& @Ty &!@Qq@O Nip &q!@L@I@HY&7@F&@EQ Cp &q@BI&%@?A&@=&@:@90 7p &q!@6(@3 &@1 @0 @. -p &q-@+@*@( @'@%| #p &q)@"s&@k & cpQ@[q&@@S &@K@ Cp &q!@@ @ 3  ;(^kernel4.mcSeptember 22, 1986 6:03 PM%7skpif[ALU=0];stkP1AddrErr2:* expected Rscr, got stackp in t, they're differenterror;t _ cm1;t _ t # (Q_stack);* check that we loaded -1 into incremented stack locationskpif[ALU=0];* Q = value from stackstkP1ValErr3:* t = bad bitserror;t _ rscr;* restore t* stack-1 stack-1 stack-1 stack-1 stack-1 stack-1 stack-1 stack-1 stack-1 stack-1stack _ t;* reset stack which was clobbered by "stack+1_cm1"call[chkStkErr];skpif[ALU=0];stkpErr16:* got stack underflow or overflowerror;rscr _ t-1;* compute expected value of rscrt _ cm1;stack-1 _ t;* (stack-1) _ "-1"call[chkStkErr];skpif[ALU=0];stkpErr17:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;* see if real stkp (t) matches expected stkp (rscr)skpif[ALU=0];stkM1AddrErr2:error;t _ cm1;t _ t # (Q_stack);* compare tos with -1skpif[ALU=0];stkM1ValErr2:* Q = value from stackerror;* t = bad bits, expected -1t _ rscr;* restore t(stack) _ t;* restore addr as value in stack: stack[stkp]_stkpcall[chkStkErr];skpif[ALU=0];stkpErr18:* got stack underflow or overflowerror;noop;* for placementafterStkTest1:fp (-X@]N@bq `p &q3@_@\@Z&9@Y & Wp &q @U@Ty& QqpQ@Niq &2@Ka@I HYp &q!@F@C &@BI@@ &@=@<8 :p &q!@90@6(@4 &3@3 1p @0q@-@+&@* (p &q@'&@#& @"s &2@k@ cp &q!@@[& Sp V ;Skernel4.mcSeptember 22, 1986 6:03 PM%8* November 30, 1978 6:07 PM%remember, don't execute if i=1, if i+2=77%call[getStkPAddr];rscr _ t and (77c);* isolate the index (exclude top 2 bits)rscr _ (rscr)+1;(rscr)-(stkPMaxXC);* skip this test if it would cause overflowbranch[afterStkTest2, ALU>=0];t # (Q_stack);* see if stack[stkp] = stkpskpif[ALU=0];* if not, an earlier execution of this loop clobberedstkpErr21:* the stack entry at location in t, or this is first timeerror;* thru, and the initialization didn't work properly.*Q=value from stack* stack&+2 stack&+2 stack&+2 stack&+2 stack&+2 stack&+2 stack&+2 stack&+2stack&+2 _ cm1;* stack[stackP] _ -1, then stackP _ stackP+2call[chkStkErr];skpif[ALU=0];stk&Plus2Err0:* got stack underflow or overflowerror;call[getRealStkAddr], rscr_t+(2c);* compare stackPAddr from Pointers w/ expected valt #(rscr);skpif[ALU=0];stkP2AddrErr:* auto increment of StackP failed. rscr = expected value,error;* t = value from Pointerst _ t # (Q_stack);skpif[ALU=0];stkP2ValErr:* value at stackp is bad. Q = value from stackerror;* t = expected val, rscr = stack's val from Pointerst _ rscr;* restore t* stack&-2 stack&-2 stack&-2 stack&-2 stack&-2 stack&-2 stack&-2 stack&-2 stack&-2stack&-2 _ t;* stack["i+2"] _ i+2, stackp _ i.call[chkStkErr];skpif[ALU=0];stkpErr22:* got stack underflow or overflowerror;call[getRealStkAddr], rscr _ t-(2c);t # (rscr);* compare expected stkP (rscr) withskpif[ALU=0];* actual stkp (t)stkM2AddrErr:* auto decrement failederror;t _ cm1;t _ t # (Q_stack);skpif[ALU=0];* see if original stack&+2 _ cm1 workedstkP2ValErr2:* stack&+2 seems to have clobbered theerror;* (i+2)th value. t = bad bits. Q = value from stackt _ rscr;* restore t(stack)_ t;* reset stk[stkp] to contain stkpcall[chkStkErr];fp (-X@]N bq `p*@_q@]&(@\@Z&+@Y@U &@Ty &5 Rp &q9@Qq&4 O@ LpI@Iq&,@HY@F EQp &q!@C@@"&2@?A @= <8p &q9@:&@7@6( 4p &q.@3 &4@1& .pR@+q &!@(@' %|p &q!@#@ $@k &#@ & cp &q@@@S@ &' Kp &q&@&3@& @ ; &!@ 3 ;^kernel4.mcSeptember 22, 1986 6:03 PM%9skpif[ALU=0];stkpErr23:* got stack underflow or overflowerror;rscr _ t _ t+(2C);stkp _ t;* check the data modified during "stack&-2" instructiont _ t # (Q_stack);* compare tos with expected valuskpif[ALU=0];stkM2ValErr:*. Q = value from stackerror;* t = bad bits, rscr = expected value* stack+2 stack+2 stack+2 stack+2 stack+2 stack+2 stack+2 stack+2 stack+2 stack+2t _ rscr _ (rscr)-(2c);* t, rscr _ "i"stkp _ t;* stkp is at i+2c now. Fix it.call[chkStkErr];skpif[ALU=0];stkpErr24:* got stack underflow or overflowerror;rscr _ t+(2c);* compute expected stkp valuet _ cm1;stack+2 _ t;* stkp _ i+2, stack[stkp] _ -1call[chkStkErr];skpif[ALU=0];stkpErr25:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;skpif[ALU=0];stkP2AddrErr2:* expected stackP t, got stackp in Rscr, they're differenterror;t _ cm1;t _ t # (Q_stack);* check that we loaded -1 into incremented stack locationskpif[ALU=0];* Q = value from stackstkP2ValErr3:* t = bad bitserror;t _ rscr;* restore t* stack-2 stack-2 stack-2 stack-2 stack-2 stack-2 stack-2 stack-2 stack-2 stack-2stack _ t;* reset stack which was clobbered by "stack+2_cm1"call[chkStkErr];skpif[ALU=0];stkpErr26:* got stack underflow or overflowerror;rscr _ t-(2c);* compute expected value of rscrt _ cm1;stack-2 _ t;* (stack-2) _ "-1"call[chkStkErr];skpif[ALU=0];stkpErr27:* got stack underflow or overflowfp (-X@]N@bq `p &q!@_@\@Z&7@Y&@W Up &q@Ty&% QqpQ@Niq&@L&@I@HY Fp &q!@EQ@BI &@@@?A &@<8@: 90p &q!@7@4@3 @1 0p &q:@.@+@*&9@( & 'p &q @%|@#& pQ@q &2@@[ p &q!@S@K &@@C &@ ;@ 3p &q!x ;^kernel4.mcSeptember 22, 1986 6:03 PM%10error;call[getRealStkAddr];(rscr) # t;* see if real stkp (t) matches expected stkp (rscr)skpif[ALU=0];stkM2AddrErr2:error;t _ cm1;t _ t # (Q_stack);* compare tos with -1skpif[ALU=0];stkM2ValErr2:* Q = value from stackerror;* t = bad bits, expected -1t _ rscr;* restore t(stack) _ t;* restore addr as value in stack: stack[stkp]_stkpcall[chkStkErr];skpif[ALU=0];stkpErr228:* got stack underflow or overflowerror;noop;* for placementafterStkTest2:fp (-X@]N@bq@_@] &3@\ Zp @Yq@U@Ty&@R Qqp &q@O&@L& @Ka &2@HY@F EQp &q!@C@BI& ?Ap  =u6*pkernel4.mcSeptember 22, 1986 6:03 PM%11* December 1, 1978 3:19 PM%remember, don't execute if i=1, if i+3>=77%noop;* placement for afterStkTest2 branchcall[getStkPAddr];rscr _ t and (77c);* isolate the index (exclude top 2 bits)rscr _ (rscr)+(2c);(rscr)-(stkPMaxXC);* skip this test if it would cause overflowbranch[afterStkTest3, ALU>=0];t # (Q_stack);* see if stack[stkp] = stkpskpif[ALU=0];* if not, an earlier execution of this loop clobberedstkpErr31:* the stack entry at location in t, or this is first timeerror;* thru, and the initialization didn't work properly.*Q=value from stack* stack&+3 stack&+3 stack&+3 stack&+3 stack&+3 stack&+3 stack&+3 stack&+3stack&+3 _ cm1;* stack[stackP] _ -1, then stackP _ stackP+3call[chkStkErr];skpif[ALU=0];stk&Plus3Err0:* got stack underflow or overflowerror;call[getRealStkAddr], rscr_t+(3c);* compare stackPAddr from Pointers w/ expected valt #(rscr);skpif[ALU=0];stkP3AddrErr:* auto increment of StackP failed. rscr = expected value,error;* t = value from Pointerst _ t # (Q_stack);skpif[ALU=0];stkP3ValErr:* value at stackp is bad. Q = value from stackerror;* t = expected val, rscr = stack's val from Pointerst _ rscr;* restore t* stack&-3 stack&-3 stack&-3 stack&-3 stack&-3 stack&-3 stack&-3 stack&-3 stack&-3stack&-3 _ t;* stack["i+3"] _ i+3, stackp _ i.call[chkStkErr];skpif[ALU=0];stkpErr32:* got stack underflow or overflowerror;call[getRealStkAddr], rscr _ t-(3c);t # (rscr);* compare expected stkP (rscr) withskpif[ALU=0];* actual stkp (t)stkM3AddrErr:* auto decrement failederror;t _ cm1;t _ t # (Q_stack);skpif[ALU=0];* see if original stack&+3 _ cm1 workedstkP3ValErr2:* stack&+3 seems to have clobbered theerror;* (i+3)th value. t = bad bits. Q = value from stackt _ rscr;* restore t(stack)_ t;* reset stk[stkp] to contain stkpfp (-X@]N bq `p+@_q&$@]@\&(@Z@Y&+@W@Ty &@R &5 Qqp &q9@O&4 Ni@ KapI@HYq&,@F@EQ Cp &q!@BI@?A"&2@= @<8 :p &q9@90&@6(@4 3 p &q.@1&4@0& -pR@*q &!@'@%| #p &q!@"s@k$@ &#@c & p &q@[@S@@K &' p &q&@C&3@ ;& @ &! ;^kernel4.mcSeptember 22, 1986 6:03 PM%12call[chkStkErr];skpif[ALU=0];stkpErr33:* got stack underflow or overflowerror;rscr _ t _ t+(3C);stkp _ t;* check the data modified during "stack&-3" instructiont _ t # (Q_stack);* compare tos with expected valuskpif[ALU=0];stkM3ValErr:*. Q = value from stackerror;* t = bad bits, rscr = expected value* stack+3 stack+3 stack+3 stack+3 stack+3 stack+3 stack+3 stack+3 stack+3 stack+3t _ rscr _ (rscr)-(3c);* t, rscr _ "i"stkp _ t;* stkp is at i+3c now. Fix it.call[chkStkErr];skpif[ALU=0];stkpErr34:* got stack underflow or overflowerror;rscr _ t+(3c);* compute expected stkp valuet _ cm1;stack+3 _ t;* stkp _ i+3, stack[stkp] _ -1call[chkStkErr];skpif[ALU=0];stkpErr35:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;skpif[ALU=0];stkP3AddrErr2:* expected stackP t, got stackp in Rscr, they're differenterror;t _ cm1;t _ t # (Q_stack);* check that we loaded -1 into incremented stack locationskpif[ALU=0];* Q = value from stackstkP3ValErr3:* t = bad bitserror;t _ rscr;* restore t* stack-3 stack-3 stack-3 stack-3 stack-3 stack-3 stack-3 stack-3 stack-3 stack-3stack _ t;* reset stack which was clobbered by "stack+3_cm1"call[chkStkErr];skpif[ALU=0];stkpErr36:* got stack underflow or overflowerror;rscr _ t-(3c);* compute expected value of rscrt _ cm1;stack-3 _ t;* (stack-3) _ "-1"call[chkStkErr];skpif[ALU=0];fp (-X@]N@bq@` _p &q!@]@Z@Y&7@W&@U Typ &q@R&% OpQ@Lq&@Ka&@HY@F EQp &q!@C@@ &@?A@= &@:@90 7p &q!@6(@3 @1 @0 .p &q:@-@*@(&9@' & %|p &q @#@"s& kpQ@cq &2@[@ Sp &q!@@ &@C@ &@ @ 3 ^ ;^kernel4.mcSeptember 22, 1986 6:03 PM%13stkpErr37:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;* see if real stkp (t) matches expected stkp (rscr)skpif[ALU=0];stkM3AddrErr2:error;t _ cm1;t _ t # (Q_stack);* compare tos with -1skpif[ALU=0];stkM3ValErr2:* Q = value from stackerror;* t = bad bits, expected -1t _ rscr;* restore t(stack) _ t;* restore addr as value in stack: stack[stkp]_stkpcall[chkStkErr];skpif[ALU=0];stkpErr38:* got stack underflow or overflowerror;noop;* for placementafterStkTest3:fp (-X@]N b &q!@`@]@\ &3@Z Yp @Wq@Ty@R&@Qq Op &q@Ni&@Ka& @I &2@F@EQ Cp &q!@BI@@& =p  ;6,vkernel4.mcSeptember 22, 1986 6:03 PM%14* December 1, 1978 4:57 PM%remember, don't execute if i=1, if i+4>=77%noop;* placement for the afterStkTest3 checkcall[getStkPAddr];rscr _ t and (77c);* isolate the index (exclude top 2 bits)rscr _ (rscr)+(3c);(rscr)-(stkPMaxXC);* skip this test if it would cause overflowbranch[afterStkTest4, ALU>=0];t # (Q_stack);* see if stack[stkp] = stkpskpif[ALU=0];* if not, an earlier execution of this loop clobberedstkpErr41:* the stack entry at location in t, or this is first timeerror;* thru, and the initialization didn't work properly.*Q=value from stack* Simulate stack&+4 -- hardware can perform stack&+3 as maximum incrementstack&+3 _ cm1;* stack[stackP] _ -1, then stackP _ stackP+4stkp+1;* simulate +4call[chkStkErr];skpif[ALU=0];stk&Plus4Err0:* got stack underflow or overflowerror;call[getRealStkAddr], rscr_t+(4c);* compare stackPAddr from Pointers w/ expected valt #(rscr);skpif[ALU=0];stkP4AddrErr:* auto increment of StackP failed. rscr = expected value,error;* t = value from Pointerst _ t # (Q_stack);skpif[ALU=0];stkP4ValErr:* value at stackp is bad. Q = value from stackerror;* t = expected val, rscr = stack's val from Pointerst _ rscr;* restore t* stack&-4 stack&-4 stack&-4 stack&-4 stack&-4 stack&-4 stack&-4 stack&-4 stack&-4stack&-4 _ t;* stack["i+4"] _ i+4, stackp _ i.call[chkStkErr];skpif[ALU=0];stkpErr42:* got stack underflow or overflowerror;call[getRealStkAddr], rscr _ t-(4c);t # (rscr);* compare expected stkP (rscr) withskpif[ALU=0];* actual stkp (t)stkM4AddrErr:* auto decrement failederror;t _ cm1;t _ t # (Q_stack);skpif[ALU=0];* see if original stack&+4 _ cm1 workedstkP4ValErr2:* stack&+4 seems to have clobbered theerror;* (i+4)th value. t = bad bits. Q = value from stackt _ rscr;* restore t(stack)_ t;* reset stk[stkp] to contain stkpfp (-X@]N bq `p+@_q&'@]@\&(@Z@Y&+@W@Ty &@R &5 Qqp &q9@O&4 Ni@ KapI@HYq&,@F& @EQ@C BIp &q!@@@="&2@<8 @: 90p &q9@7&@4@3 1p &q.@0&4@.& +pR@(q &!@%|@# "sp &q!@ @$@c &#@ & [p &q@@@K@ &' Cp &q&@&3@ & @ 3 &! ;^ kernel4.mcSeptember 22, 1986 6:03 PM%15call[chkStkErr];skpif[ALU=0];stkpErr43:* got stack underflow or overflowerror;rscr _ t _ t+(4C);stkp _ t;* check the data modified during "stack&-4" instructiont _ t # (Q_stack);* compare tos with expected valuskpif[ALU=0];stkM4ValErr:*. Q = value from stackerror;* t = bad bits, rscr = expected value* stack+4 stack+4 stack+4 stack+4 stack+4 stack+4 stack+4 stack+4 stack+4 stack+4t _ rscr _ (rscr)-(4c);* t, rscr _ "i"stkp _ t;* stkp is at i+4c now. Fix it.call[chkStkErr];skpif[ALU=0];stkpErr44:* got stack underflow or overflowerror;rscr _ t+(4c);* compute expected stkp valuet _ cm1;stkp+1;* simulate stack+4stack+3 _ t;* stkp _ i+4, stack[stkp] _ -1call[chkStkErr];skpif[ALU=0];stkpErr45:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;skpif[ALU=0];stkP4AddrErr2:* expected stackP t, got stackp in Rscr, they're differenterror;t _ cm1;t _ t # (Q_stack);* check that we loaded -1 into incremented stack locationskpif[ALU=0];* Q = value from stackstkP4ValErr3:* t = bad bitserror;t _ rscr;* restore t* stack-4 stack-4 stack-4 stack-4 stack-4 stack-4 stack-4 stack-4 stack-4 stack-4stack _ t;* reset stack which was clobbered by "stack+4_cm1"call[chkStkErr];skpif[ALU=0];stkpErr46:* got stack underflow or overflowerror;rscr _ t-(4c);* compute expected value of rscrt _ cm1;stack-4 _ t;* (stack-4) _ "-1"fp (-X@]N@`q@_ ]p &q!@\@Y@W&7@U&@Ty Rp &q@Qq&% Nipqpqpqpqpqpqpqpqpqpq@Ka&@I&@F@EQ Cp &q!@BI@?A &@=@<8&@: &@7@6( 4p &q!@3 @0@. @- +p &q:@*@'@%|&9@# & "sp &q @ @k& cpQ@[q &2@S@ Kp &q!@@ &@ ;@ &Z ;^kernel4.mcSeptember 22, 1986 6:03 PM%16call[chkStkErr];skpif[ALU=0];stkpErr47:* got stack underflow or overflowerror;call[getRealStkAddr];(rscr) # t;* see if real stkp (t) matches expected stkp (rscr)skpif[ALU=0];stkM4AddrErr2:error;t _ cm1;t _ t # (Q_stack);* compare tos with -1skpif[ALU=0];stkM4ValErr2:* Q = value from stackerror;* t = bad bits, expected -1t _ rscr;* restore t(stack) _ t;* restore addr as value in stack: stack[stkp]_stkpcall[chkStkErr];skpif[ALU=0];stkpErr48:* got stack underflow or overflowerror;noop;* for placementafterStkTest4:branch[stkTestL];stkTestXitL:branch[stkTopL];fp (-X@]N@bq@` _p &q!@]@Z@Y &3@W Up @Tyq@Qq@O&@Ni Lp &q@Ka&@HY& @F &2@C@BI @p &q!@?A@=& :p @90q 7p @6(qZ 4]63kernel4.mcSeptember 22, 1986 6:03 PM%17* November 27, 1978 10:31 AM.iStkPAddr: subroutine;return, stackPAddr _ t-t;* first valid index is one.nextStkPAddr: subroutine;* stack indeces are 6 bits long.*Return (stackPaddr OR stackPtopBits) in T. It's an 8 bit address.*ALU#0 =>valid value.klink _ link;t _ stackPAddr _ (stackPAddr) + 1;* increment the indext and (77c);* check for 6 bit overflowskpif[ALU=0], t _ t + (stackPTopBits);* OR the top two bits into returned valueskip, rscr _ 1c;* indicate valid valuerscr _ t-t;* indicate invalid valuereturnAndBranch[klink, rscr];getStkPAddr: subroutine;t _ stackPAddr;return, t _ t + (stackPTopBits);iTopStkBits: subroutine;t _ (r0) - (100c);return, stackPTopBits _ t;* first valid index is zero.nextTopStkBits: subroutine;klink _ link;top level;t _ stackPTopBits _ (stackPTopBits)+(100c);t - (400c);skpif[ALU#0], rscr _ 1c;rscr _ t-t;returnAndBranch[klink, rscr];getRealStkAddr: subroutine;t _ TIOA&Stkp;return, t _ t and (377c);chkStkErr: subroutine;* rtn w/ ALU#0 ==> stk (underflow or overflow).* Clobber rscr2 _ Pointers[]rscr2 _ Pointers[];return, rscr2 _ (rscr2) AND (pointers.stkErr);top level;stkXitTopL:fp (-X@]N bq _p q @]& Zp q & Y@A W@@Ty @R"&@Qq &@O&')@Ni&@L &@Ka HYp q @F@EQ BIp q @@@?A& =pq @<8 @: @90+@7 @6(@4 @3  0pq @. @- *p q &/ (@'@%|.@# "sp  $9Hkernel4.mcSeptember 22, 1986 6:03 PM%18* September 3, 1977 2:25 PM%TEST CARRY20 FUNCTIONThis function causes a 1 go be or'd into the carry out bit that is usedas input to bit 11 in the alu. Given that there was not already a carry, thisfunction has the effect of adding 20B to the value in the alu.%carry20Test:t_rscr_17C;t_t+(r0),CARRY20;rscr2 _ 37C;t_t#(rscr2);skpif[ALU=0];error;* T NE 17B + 0 + CARRY20t_rscr;t_t+(r1),CARRY20;* t_17B+1+CARRY20rscr2_20C;t_t#(rscr2);skpif[ALU=0];error;* T NE 17B+1=20(=17B+1+CARRY20)t_r0;t_t+(r0),CARRY20;* t_0+0+CARRY20rscr2_20C;t_t#(rscr2);skpif[ALU=0];error;* T NE 20B=0+0+CARRY20t_r0;t_t-(rscr2);* t_-20B=(0-20B)t_t+(r0),CARRY20;skpif[ALU=0];error;fp (-X@]N bq `_\G ZM Y> U Typ qR QqO Ni L Ka+HYF+EQ C BI @+=<8+: 90 7 6(+3 1 +0. - +E:=<kernel4.mcSeptember 22, 1986 6:03 PM%19* September 11, 1977 1:57 PM%TEST XORCARRY FUNCTIONXORCARRY causes the carry in bit for bit 15 of the alu to be xor'd.Normally this bit is 0. When the bit is one, alu arithmetic functions willsee a carry into bit 0. For A-B the ALUFM is programmed to provide a oneand XORCARRY will leave a result one less than expected.%xorCarryTest:t_(r0)+(r0),XORCARRY;t_t#(r1);skpif[ALU=0];error;* 1 = 0+0+XORCARRYt_r1;t_t+(r0),XORCARRY;t_t#(2C);skpif[ALU=0];xorCarryb:error;* 2= 0+1+XORCARRYt_r1;t_t+(r1),XORCARRY;t_t#(3C);skpif[ALU=0];xorCarryc:error;* 3= 1+1+XORCARRYt_RM1;t_t+(r0),XORCARRY;skpif[ALU=0];xorCarryd:error;* 0= -1+XORCARRYt_(r0)AND(r0),XORCARRY;skpif[ALU=0];xorCarrye:error;* CIN SHOULD BE IGNORED ON LOGICAL OPS!t_(r1)AND(r1),XORCARRY;t_t#(r1);skpif[ALU=0];xorCarryf:error;* SHOULD BE 1. CIN IGNORED ON LOGICAL OPSt_(RM1)OR(RM1),XORCARRY;t_t#(RM1);skpif[ALU=0];xorCarryg:error;* SHOULD BE -1. CIN IGNORED ON LOGICAL OPSt_(r1)-(r1),XORCARRY;t_t#(RM1);skpif[ALU=0];xorCarryh:error;* BWL SEZ THIS SHOULD BE -1. IE.,* R1-R1 causes 1+1777777, but xorcarry causes the op to become,* 1+177776 because "A-B" uses carryin = 1, and xorcarry causes it to befp (-X@]N bq `_\C ZJ YH W8 U Typ qRQqO Ni+KaIHYF EQpqC+@?A=<8 :pq90+6(43 1pq0+-+ *pq(+'%|#"s pqk+)c [ pqS+*K C pq ;+! ? 3G A^kernel4.mcSeptember 22, 1986 6:03 PM%20* zero!fp (-X@]N bq0 `S&kernel4.mcSeptember 22, 1986 6:03 PM%21* September 12, 1977 9:52 AM%TEST USESAVEDCARRYThis function causes the alu carry bit from the last instruction to be used asthe carry in bit to bit 15 during the current instruction. This bit is usuallyprovided by the alufm and is usually zero (its the bit complemented by thexorcarry function).%%commented outsavedCarry:T_(RHIGH1)+(RHIGH1);* T_0, CARRY_1T_T+(R0),USESAVEDCARRY;* T_0+0+LAST CARRYT_T#(R1);SKPIF[ALU=0];ERROR;* EXPECTED 1, USED LASTCARRY=1T_(RM1)+(RM1);* T_-2, CARRY _1T_T+(R1),USESAVEDCARRY;* T_-2+1+LAST CARRYSKPIF[ALU=0];savedCarryB:ERROR;* EXPECTED 0, USED LASTCARRY=1T_(R0)+(R0);* T_0, CARRY_0T_(R1)+(R1),USESAVEDCARRY;* T_1+1+LAST CARRYT_T#(2C);SKPIF[ALU=0];savedCarryC:ERROR;* EXPECTED 2, USED LASTCARRY=0T_(R0)+(R0);* T_0, CARRY_0T_(RM1)+(RM1),USESAVEDCARRY;* T_(-1)+(-1)+LAST CARRYT_T#(177776C);SKPIF[ALU=0];savedCarryD:ERROR;* EXPECTED -2, USED LASTCARRY=0T_(RM1)+(RM1);* T_-2, CARRY_1T_(R1)+(R1),USESAVEDCARRY;* T_1+1+LAST CARRYT_T#(3C);SKPIF[ALU=0];savedCarryE:ERROR;* EXPECTED 3, USED LASTCARRY=1commented out%fp (-X@]N bq `_ \N ZN YJ W U Ty+p R qQq+ O+NiL Ka+HY +F+EQ Cp qBI+?A + =+<8: 90p q7+4 + 3 +1 0 .p q-+* +(+'%| #p q"s++ p 8 9Jkkernel4.mcSeptember 22, 1986 6:03 PM%22* September 14, 1977 12:03 PM%TEST MULTIPLY STEP.MULTIPLY works as follows:H3[0:15] _ CARRY,,ALU[0:14] ==> CARRY,,ALU/2Q[0:15] _ ALU[15],,Q[0:14] ==> ALU[15],,Q/2Q[14] OR'D INTO TNIA[10] AS SLOW BRANCH! ==> ADDR OR'D 2 IF Q[14]=1These tests invoke mulCheck, a subroutine that performs two services:1) T_T+RSCR,MULTIPLY2) RSCR2_1 IF Q[14] BRANCH IS TAKEN (ZERO OTHERWISE)ERRORS are numbered 1 thru 3:mulXerr1 ==> T value wrong (H3)mulXerr2 ==> Q[14] branch wrongmulXerr3 ==> Q value wrong%multiplyTest:* Q[14]=0, CARRY=0, ALU15=0t_Q_r0;rscr_t;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_0, CARRY_0skpif[R EVEN],rscr2_rscr2;mulAerr1:error;* TOOK Q[14]=1 BRANCHt_t;skpif[ALU=0];mulAerr2:error;* CARRY,,(0+0)/2 SHOULD BE ZEROt_Q;skpif[ALU=0];mulAerr3:error;* ALU15,,Q[0:14] SHOULD BE ZERO*Q[14]=0, CARRY=1, ALU15=0multiplyB:* Q=0; t_-1+1,MULTIPLYQ_r0;rscr_r1;call[mulCheck],t_rm1;* t_t+rscr,MULTIPLY==>ALU_0, CARRY_1skpif[R EVEN], rscr2_rscr2;mulBerr1:error;* TOOK Q[14]=1 BRANCHt_t#(rhigh1);*-1+1 GENERATES CARRY BITskpif[ALU=0];mulBerr2:error;* CARRY,,(0+0)/2 SHOULD BE 100000t_Q;* -1+1 WOULD LEAVE ALU15=0skpif[ALU=0];mulBerr3:error;* ALU15,,Q[0:14] SHOULD BE ZERO*Q[14]=0, CARRY=0, ALU15=1multiplyC:* Q=0; t_0+1,MULTIPLYt_Q_r0;fp (-X@]N bq `_ \Z-Y-WC TyERQq5NiLKaI HY Fp q EQCBI@$?A =pq<8907 6(pq410 .pq- * (pq'%|# $"s pqkc  [pq!K pqC ; pq 3 7_^kernel4.mcSeptember 22, 1986 6:03 PM%23rscr_r1;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_1, CARRY_0skpif[R EVEN], rscr2_rscr2;mulCerr1:error;* TOOK Q[14]=1 BRANCHt_t;* 0+1==> CARRY_0skpif[ALU=0];mulCerr2:error;* CARRY,,(0+1)/2 SHOULD BE 0t_(rhigh1)#(Q);* 0+1 WOULD LEAVE ALU15=1skpif[ALU=0];mulCerr3:error;* ALU15,,Q[0:14] SHOULD BE 100000*Q[14]=0, CARRY=1, ALU15=1multiplyD:* Q=0; t_100001+100000,MULTIPLYQ_r0;t_rscr_rhigh1;call[mulCheck],t_t+(r1);* t_t+rscr,MULTIPLY==>ALU_1, CARRY_1skpif[R EVEN], rscr2_rscr2;mulDerr1:error;* TOOK Q[14]=1 BRANCHt_t#(rhigh1);* 1000001+100000==> CARRY_1skpif[ALU=0];mulDerr2:error;* CARRY,,(1000001+100000)/2 SHOULD BE 100000t_(rhigh1)#(Q);* 1000001+100000 WOULD LEAVE ALU15=1skpif[ALU=0];mulDerr3:error;* ALU15,,Q[0:14] SHOULD BE 100000multiplyE:* Q[14]=1, CARRY=0, ALU15=0t_(r1)+(r1);Q_t;* Q[14]_1t_r0;rscr_t;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_0, CARRY_0skpif[R ODD],rscr2_rscr2;mulEerr1:error;* DIDN'T TAKE Q[14]=1 BRANCHt_t;skpif[ALU=0];mulEerr2:error;* CARRY,,(0+0)/2 SHOULD BE ZEROt_(r1)#(Q);skpif[ALU=0];mulEerr3:error;* ALU15,,Q[0:14] SHOULD BE 1*Q[14]=1, CARRY=1, ALU15=0multiplyF:* Q=1; t_-1+1,MULTIPLYt_(r1)+(r1);fp (-X@]Nbq`$_ ]pq\YW UpqTyQq O NipqL! I HYpqFEQ C $BI @pq?A<8 : 90pq7,4 $3 1pq0! -pq ++* (+'%|#+$"s pqk+c [pq+ K pqC+ ;+ pq+ 3  >^ kernel4.mcSeptember 22, 1986 6:03 PM%24Q_t;* Q[14]_1rscr_r1;call[mulCheck],t_rm1;* t_t+rscr,MULTIPLY==>ALU_0, CARRY_1skpif[R ODD], rscr2_rscr2;mulFerr1:error;* DIDN'T TAKE Q[14]=1 BRANCHt_t#(rhigh1);*-1+1 GENERATES CARRY BITskpif[ALU=0];mulFerr2:error;* CARRY,,(0+0)/2 SHOULD BE 100000t_(r1)#(Q);* -1+1 WOULD LEAVE ALU15=0skpif[ALU=0];mulFerr3:error;* ALU15,,Q[0:14] SHOULD BE 1*Q[14]=1, CARRY=0, ALU15=1multiplyG:* Q=1; t_0+1,MULTIPLYt_(r1)+(r1);Q_t;* Q[14]_1t_r0;rscr_r1;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_1, CARRY_0skpif[R ODD], rscr2_rscr2;mulGerr1:error;* DIDN'T TAKE Q[14]=1 BRANCHt_t;* 0+1==> CARRY_0skpif[ALU=0];mulGerr2:error;* CARRY,,(0+1)/2 SHOULD BE 0t_(rhigh1)+1;* 0+1 WOULD LEAVE ALU15=1t_t#(Q);skpif[ALU=0];mulGerr3:error;* ALU15,,Q[0:14] SHOULD BE 100001*Q[14]=1, CARRY=1, ALU15=1multiplyH:* Q=2; t_100001+100000,MULTIPLYt_(r1)+(r1);Q_t;* Q[14]_1t_rscr_rhigh1;call[mulCheck],t_t+(r1);* t_t+rscr,MULTIPLY==>ALU_1, CARRY_1skpif[R ODD], rscr2_rscr2;mulHerr1:error;* DIDN'T TAKE Q[14]=1 BRANCHt_t#(rhigh1);* 1000001+100000==> CARRY_1skpif[ALU=0];mulHerr2:error;* CARRY,,(1000001+100000)/2 SHOULD BE 100000t_(rhigh1)+1;* 1000001+100000 WOULD LEAVE ALU15=1t_t#(Q);skpif[ALU=0];mulHerr3:error;* ALU15,,Q[0:14] SHOULD BE 100001fp (-X@]Nbq+`_+$] \pqZ+W +U TypqR+!O +Ni LpqKa+ HY+ Fpq+EQ C+BI@?A+$= <8pq:+7+6( 4pq3 +0 +.- +pq*+! '+ %|pq+# "s+ k+$ cpq+ +S pqK+,C +$ ; pq 3+! @^kernel4.mcSeptember 22, 1986 6:03 PM%25multiplyJ:* Q_r01=>Q[14]=0; CARRY=0,ALU15=0t_r01;Q_t;* Q[14]_0t_r0;rscr_t;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_0, CARRY_0skpif[R EVEN],rscr2_rscr2;mulJerr1:error;* TOOK Q[14]=1 BRANCHt_t;skpif[ALU=0];mulJerr2:error;* CARRY,,(0+0)/2 SHOULD BE ZEROt_(r01) RSH 1;t_t#(Q);skpif[ALU=0];mulJerr3:error;* ALU15,,Q[0:14] SHOULD BE (r01) RSH 1multiplyK:* Q_r10=>Q[14]=1; CARRY=0,ALU15=0t_r10;Q_t;* Q[14]_1t_r0;rscr_t;call[mulCheck];* t_t+rscr,MULTIPLY==>ALU_0, CARRY_0skpif[R ODD],rscr2_rscr2;mulKerr1:error;* DIDN'T TAKE Q[14]=1 BRANCHt_t;skpif[ALU=0];mulKerr2:error;* CARRY,,(0+0)/2 SHOULD BE ZEROt_(r10) RSH 1;t_t#(Q);skpif[ALU=0];mulKerr3:error;* ALU15,,Q[0:14] SHOULD BE (r10) RSH 1mulDone: BRANCH[afterMul];fp (-X@]N `q _+]\+ZYW+$U TypqR+ONi LpqKa+HY FEQ CpqBI+& ?Apq =+<8:+9076(+$4 3 pq1+.- +pq*+' %|# "spq +& c >Mskernel4.mcSeptember 22, 1986 6:03 PM%26* September 11, 1977 2:46 PM%MULCHECKThis subroutine performs,t_t+(rscr),MULTIPLY;It sets rscr2=0 IF Q[14] branch DID NOT HAPPEN.It sets rscr2=1 IF Q[14] branch DID HAPPENT and rscr2 ARE CLOBBERED! IT ASSUMES r0=0, r1=1.%SUBROUTINE;mulCheck:t_t+(rscr),MULTIPLY, GLOBAL, AT[700];GOTO[.+1];rscr2_r0,AT[701];RETURN;rscr2_r1,AT[703];RETURN;TOP LEVEL;afterMul:noop;fp (-X@]N bq `_ \Z W/ U* R1 Qq O NipqL%Ka IHYFEQ C @pq?A =u&*ckernel4.mcSeptember 22, 1986 6:03 PM%27* September 14, 1977 12:03 PM%DIVIDE TESTH3 _ ALU[1:15],,Q[0] ==> H3_ 2*ALU,,Q[0]Q _ Q[1:15], CARRY ==> Q _ 2*Q,,CARRY%divideTest:*Q0=0, CARRY=0Q_r0;t_(r1)+(r1),DIVIDE;*t_1+1,DIVIDE==> CARRY_0,t_t#(4C);skpif[ALU=0];error;* 2*(1+1)=4, Q0=0t_Q;skpif[ALU=0];error;* CARRY WAS ZERO, Q SHOULD BE ZEROdivB:*Q0=0, CARRY=1Q_r0;t_rhigh1;t_t+(r1);* T = 100001t_t+(rhigh1),DIVIDE;* t_100001+100000,DIVIDE==>ALU=1, CARRY=1t_t#(2C);skpif[ALU=0];error;* 2*(1+1)=4, Q0=0t_(r1)#(Q);skpif[ALU=0];error;* 2*0,,CARRY SHOULD BE 1divC:*Q0=1, CARRY=0Q_rhigh1;t_(r1)+(r1),DIVIDE;* t_1+1,DIVIDE==>ALU=2, CARRY=0t_t#(5C);skpif[ALU=0];error;* 2*(2),,Q[0]=5t_(Q);skpif[ALU=0];error;* Q[1:15],,CARRY SHOULD BE ZEROdivD:*Q0=1, CARRY=1t_Q_rhigh1;* SET Q[0] TO ONEt_t+(r1);* T = 100001t_t+(rhigh1),DIVIDE;* t_100001+100000,DIVIDE==>ALU=1, CARRY=1t_t#(3C);skpif[ALU=0];error;* 2*(1),,Q[0]=3t_(r1)#(Q);skpif[ALU=0];error;* 2*0,,CARRY SHOULD BE 1fp (-X@]N bq `_ \)Z( Y Wp q U+ TyR+QqO Ni+KaI HY+" EQpq C+ BI@?A+ =+)<8: 90+6( 4 3 + .pq -+ +*+(' %|+"s k+ cpq + [ ++ S+)K +  ;  + B^kernel4.mcSeptember 22, 1986 6:03 PM%28divE:*Q_r01=>Q0=0, CARRY=1Q_r01;t_(rhigh1)+1;* T = 100001t_t+(rhigh1),DIVIDE;* t_100001+100000,DIVIDE==>ALU=1, CARRY=1t_t#(2C);skpif[ALU=0];error;* 2*(1),,Q[0]=2t_(r01) LSH 1;t_t+(r1);* ADD ONE FOR CARRYt_t#(Q);skpif[ALU=0];error;* 2*r01,,CARRY SHOULD BE ((r01)LSH 1)+1fp (-X@]N bq `+_] + \+)ZY W+Ty R+QqO Ni+'6 LBmSkernel4.mcSeptember 22, 1986 6:03 PM%29* May 1, 1909 1:09 PM%CDIVIDE TESTH3 _ ALU[1:15],,Q[0] ==> H3_ 2*ALU,,Q[0]Q _ Q[1:15], CARRY ==> Q _ 2*Q,,CARRY' (COMPLEMENTED CARRY)%CdivideTest:*Q0=0, CARRY=0Q_r0;t_(r1)+(r1),CDIVIDE;*t_1+1,DIVIDE==> CARRY_0t_t#(4C);skpif[ALU=0];error;* 2*(1+1)=4, Q0=0t_(r1)#(Q);skpif[ALU=0];error;* CARRY' WAS 1, Q SHOULD BE 1CdivB:*Q0=0, CARRY=1Q_r0;t_rhigh1;t_t+(r1);* T = 100001t_t+(rhigh1),CDIVIDE;* t_100001+100000,DIVIDE==>ALU=1, CARRY=1t_t#(2C);skpif[ALU=0];error;* 2*(1+1)=4, Q0=0t_(Q);skpif[ALU=0];error;* 2*0,,CARRY' SHOULD BE 0CdivC:*Q0=1, CARRY=0Q_rhigh1;t_(r1)+(r1),CDIVIDE;* t_1+1,DIVIDE==>ALU=2, CARRY=0t_t#(5C);skpif[ALU=0];error;* 2*(1),,Q[0]=3t_(r1)#(Q);skpif[ALU=0];error;* Q[1:15],,CARRY' SHOULD BE 1CdivD:*Q0=1, CARRY=0T_Q_rhigh1;* SET Q[0] TO ONET_T+(R1);* T = 100001T_T+(rhigh1),CDIVIDE;* T_100001+100000,DIVIDE==>ALU=1, CARRY=1T_T#(3C);skpif[ALU=0];ERROR;* 2*(1),,Q[0]=3T_(Q);skpif[ALU=0];ERROR;* 2*0,,CARRY' SHOULD BE 0fp (-X@]N bq `_ \)Z> Y Wp q U+ TyR+QqO Ni+Ka I HY+ EQpq C+ BI@?A+ =+)<8: 90+6(4 3 + .pq -+ +*+(' %|+"s  k+ cpq + [ ++ S+)K + ;  + B{^kernel4.mcSeptember 22, 1986 6:03 PM%30CdivE:*Q_R01=>Q0=0, CARRY=1Q_R01;T_(rhigh1)+1;* T = 100001T_T+(rhigh1),CDIVIDE;* T_100001+100000,CDIVIDE==>ALU=1, CARRY=1T_T#(2C);skpif[ALU=0];ERROR;* 2*(1),,Q[0]=2T_(R01) LSH 1;T_T#(Q);skpif[ALU=0];ERROR;* 2*R01,,CARRY' SHOULD BE (R01)LSH 1fp (-X@]N bq `+_] + \+*ZY W+Ty RQq O+$ KCxNkernel4.mcSeptember 22, 1986 6:03 PM%31* September 9, 1977 5:09 PM%TEST 8 WAY SLOW B DISPATCHGo thru the loop 16 times to make sure that only the low 3 bits areor'd into next pc. keep counter in Q, loop control in CNT.%slowBr:cnt_17s;t_q_r0;rscr2_7C;* THIS WILL BE A 3 BIT MASKslowBrL:* TOP OF LOOPt_rm1;rscr_t;t_q;BDISPATCH_t;* DO DISPATCH W/ BITS IN T (=Q)branch[BDTbl];slowBRnoBr:* should have branched and didn'terror;bdConverge:t_(rscr2)AND(q);* MASK DISPATCH VALUEt_t#(rscr);branch[.+2,ALU=0];slowBRbadBr:error;* DIDN'T GO WHERE WE EXPECTEDt_(r1)+(q);* GET NEXT VALUE FOR DISPATCHloopChk[slowBrL,CNT#0&-1],q_t;afterBD:goto[afterKernel4];SET[BDTblLoc,5110];BDTbl:goto[bdConverge], rscr_r0, AT[BDTblLoc];goto[bdConverge], rscr_r1, AT[BDTblLoc,1];goto[bdConverge], rscr_2C, AT[BDTblLoc,2];goto[bdConverge], rscr_3C, AT[BDTblLoc,3];goto[bdConverge], rscr_4C, AT[BDTblLoc,4];goto[bdConverge], rscr_5C, AT[BDTblLoc,5];goto[bdConverge], rscr_6C, AT[BDTblLoc,6];goto[bdConverge], rscr_7C, AT[BDTblLoc,7];goto[bdConverge], rscr_10C, AT[BDTblLoc,10];* shouldn't be heregoto[bdConverge], rscr_11C, AT[BDTblLoc,11];* shouldn't be heregoto[bdConverge], rscr_12C, AT[BDTblLoc,12];* shouldn't be heregoto[bdConverge], rscr_13C, AT[BDTblLoc,13];* shouldn't be heregoto[bdConverge], rscr_14C, AT[BDTblLoc,14];* shouldn't be heregoto[bdConverge], rscr_15C, AT[BDTblLoc,15];* shouldn't be heregoto[bdConverge], rscr_16C, AT[BDTblLoc,16];* shouldn't be heregoto[bdConverge], rscr_17C, AT[BDTblLoc,17];* shouldn't be herefp (-X@]N bq `_\C Z: Y WpqUTyR+ Opq+ NiLKaI +HY Fp +q!EQ BIp q@+?A = <8p :q+7 +6( 3 pq1 . -pq+(**(*'*%|*#*"s* *k,5,5c,5,5[,5,5S,5,5 8Vkernel5.mcOctober 14, 1986 4:15 PM1%set[TaskCodeloc, 7000];mc[TaskCodelocC, TaskCodeloc];set[TaskErrorloc, 6400];mc[TaskErrorlocC, TaskErrorloc];set[Task17loc, 7400];mc[Task17locC, Task17loc];set[Tasktestloc, 6000];mc[TasktestlocC, Tasktestloc];set[JunkTaskloc, 5400];mc[JunkTasklocC, JunkTaskloc];Toplevel;beginKernel5:call[checkTaskNum], t _ R0;skpif[ALU=0];branch[AfterKernel5];*Don't try if not in Task 0TaskingOff;T _ R0;hold&tasksim_t;*This will turn off the Task Simulator (Task12).Cnt _ RM1;Kernel5Delay:Skpif[cnt=0&-1];Goto[Kernel5Delay];*Try to give Task 12 some time to stop. set[xtask,0];InitTPC: *Inititialize all task tpc's to TaskError codeRscr2 _ 1c;*Set Rscr2 to 1 for the first task numberQ _ (RM1);*Set Q = 177777, the successful task running will set it back to 0InitTPCL:cnt _ 16S;rscr _ 1C;InitTPCL1:TaskingOff;T _ TaskErrorlocC;*Init TPC,s 1 - 17 to TaskError location.Link _ T;ldTPC _ (Rscr);Rscr _ (Rscr)+1;Skpif[cnt=0&-1];Branch[InitTPCL1];fp )fXN bq_']'\'Z'Y'W Typ RqQq O'Ni LKa'0HY Fp EQqCp q'(BI @p'q.?A ')= 'B :p90q 7 4p 3 q 1')0.-+* (=A?kernel5.mcOctober 14, 1986 4:15 PM2%TaskSwitch will Notify each task from 1 to 17.The check for Q=0 would indicate that Q was zeroed by the TaskCode, indicating that the switch happened. Ireinitialize all of the TPC's after each test.All of the unused TPC's are set to TaskError this is a place we should never goto.We should go to TaskError only when something went wrong like Notifying task 7 and we actually went to task 5.%TaskSwitch:T _ TaskCodelocC;*TaskSwitch code is run in Task 0.Link _ T;ldTPC _ (Rscr2);*Task number is in Rscr2Noop;Noop;TaskingOn;T _ (Rscr2);Call[NotifyTask];noop;noop;*We should notify Task in Rscr2 then block back to task 0 "Q"*should be 0 if the correct task number that was notified.T _ Q;*This is the first instruction to run after TaskCode blocksSkpif[Alu=0];TaskSwitchErr:Error;Rscr2 _ (Rscr2)+1;*Increment task number Q _ (RM1);*Update Q to the current task number(Rscr2) # (20C);*Stop testing when we try to test task 20Skpif[Alu=0];Branch[InitTPCL];*Reinitialize all task tpc's for next testnoop;Branch[TaskPreempt];set[xtask,17];TaskCode:T _ 0C, at[TaskCodeloc];*Put a breakpoint here to ovserve each task being Notifiedhold&tasksim_t;*This will turn off TestTW just in case it is a problem.Q _ T;*Put a 0 into Q to prove we went to Taskcode.Branch[TaskCode], Block;TaskError:Noop, at[TaskErrorLoc];*We should never get to here, check Rscr2 for the taskError;*number we were setting. Check TPC 0 for the last*microinstruction the EMU ran.fp )fXN bq `p. _k ]. \R Zo Yq Up Tyq'"RQq'ONiL Ka IHYF'='EQ:BI';@ ?Ap =q<8'rq : '$90')7 6('*43 0 .p-q':+'8*'-( %|p #q'6"s'1'  $B$Hkernel5.mcOctober 14, 1986 4:15 PM3%TaskPreempt will Notify each task. The TaskTest code will then notify task 17 there by setting each task's Readyflip/flop using the preempting logic on the ContA board. The Task17 Code will Block back to the TaskTest codewhere Q will be set to 0.%TaskPreempt:Rscr2 _ 1c;*Set Rscr2 to 1 for the first task number to test.Q _ (RM1);*Set Q to 177777InitTPCL2:Cnt _ 16S;Rscr _ 1C;InitTPCL21:TaskingOff;T _ TaskErrorlocC;*Init all task tpc's to TaskError codeLink _ T;ldTPC _ (Rscr);Rscr _ (Rscr)+1;Skpif[cnt=0&-1];Branch[InitTPCL21];Preempt:T _ TaskTestlocC;*Preempt code is run in Task 0.Link _ T;ldTPC _ (Rscr2);*Task number is in Rscr2TaskingOn;T _ (Rscr2);*NotifyTask in a subroutine in Postamble.mc T=Task number.Call[NotifyTask];*This will cause the TaskTest code to be run.T _ Q;*We will return here from TaskTest code blocking.Skpif[Alu=0];*Q is set to 0 in the Task Test code.PreemptErr:*The task we were testing is in Rscr2. If Q=0 Testing is ok.Error;*If Q=17 the task under test did not set it's Ready FF when itRscr2 _ (Rscr2)+1;*was preempted in the TaskTest code. Q _ (RM1);(Rscr2) # (17C);*Stop testing when we get to task 17.Skpif[Alu=0];Branch[InitTPCL2];*Reinitialize all task tpc's to TaskError location for the next test.Goto[Junktasktest];TaskTest:TaskingOff, at[TaskTestloc];T _ Task17locC;Link _ T;T _ (17s);ldTPC _ (T);*Task number is 17. Task17 code will be run.TaskingOn;*Notify task number 17. This will preempt this task and setCall[NotifyTask];*It's Ready FF to indicate it was preempted.T _ Q;*Task 17 should block back to here with 17 in the Q reg.(T) # (17C);Skpif[Alu=0];TaskTestErr:Error;*If Q is not = 17 then task 17 code didn't run.T _ 0C;Q _ T;Branch[TaskTest], Block;set[xtask,17];Task17:T _ 17C, at[Task17loc];*Set Q to a 17 to prove we went to task 17.Q _ T;*Put a breakpoint here to observe each ready FF being setBranch[Task17], Block;*as a result of the code at TaskTest preempting its own task.fp )fXN bq `pp _m ] \q Zp Yq '2W ' Up Tyq R Qqp Oq Ni'q&LKaIHYF EQpCq'BI@'?A = ':<8'pq90'17 '% 6(p 'q<4'>3 'rqpq 1 0'%. -'E+ *p(q'%|# "s 'pq ';k',c'8 [ p Sq'/KC p ;q'+ '9 3'> B!^&kernel5.mcOctober 14, 1986 4:15 PM4%This is a test of the 16us. Pendulum signal coming from the Baseboard to the Ifu board on pin number <176>. Thelogic is on page 15 of the IFU board. The Pendulum signal is a 16 us square wave.The JunkTw is tied to Task 2 on the Conta Board and can be scoped at pin number <13> on the IFU board. The signalat pin <13> should be about 32 us. This test is ignored if the IFU board is not installed in the computer.%JunkTaskTest:TaskingOff;IFUMRH_(R01);*Check to see if IFU board installed.Rscr_IFUMRH';T _ (R10);*IFUMRH comes in inverted.T # (Rscr);Skpif[Alu=0];Goto[Kernel5Exit];*No IFU board installed goto Kernel5Exit.T _ JunkTasklocC;*Set up Tpc 2 for 5400.Link _ T;*5400 = JunkTask.T _ (2s);ldTPC _ (T);*Junk Task is task number is 2.Q_(R0);Cnt _ RM1;AckJunkTW _ (RM1);TaskingOn;JunkTaskSpin:*See if we can wake up the Junk Task for 1 count.T_ (Q);T _ T # (R0);Skpif[Alu=0];Goto[JunkTaskStart];*This code will also syschronize the Counter with the microcodeSkpif[cnt=0&-1];Goto[JunkTaskSpin];PendulumDead:*Check pin #<176> on the BaseboardError;JunkTaskStart:Cnt _ RM1;JunkTaskL:Skpif[cnt=0&-1];Goto[JunkTaskL];*Patch JunktaskL+2 to be LongGo[JunktaskL] to scope board.TaskingOff;T _ (0c);AckJunkTW _ (T);*Just to be sure we turn off JunkTW.T _ Q;*T and Q will have the count the JunkTask wakeups.Rscr _ 200c;*Normal count in Q is 404 with clocks set to 31.7ns.Rscr2 _ T - (Rscr);SkpUnless[Alu<0];JunkTaskErrSlow:Error;*An error here says the counter is too slow!Rscr _ 1000c;Rscr2 _ T - (Rscr);Skpif[Alu<0];JunkTaskErrFast:Error;*An error here says the counter is too fast!Goto[TestTW];JunkTask:Noop, at[JunkTaskloc];T _ (1c);AckJunkTW _ (T);T _ Q;*Set Q to +1 to count the times we ran the JunkTask code.T _ (T)+1;Q _ T;Branch[JunkTask], Block;fp )fXN bq `po _T ]q \n Zq Yp qW U '%Ty R 'Qq O Ni')L'Ka'IHY 'FEQ CBI @p 'q1?A= <8 :'rq>907 6(p 'q"4q 3 p 1q 0p .q-';+ *('q$''2%| '4#"s pkq', c [pq',S pKqC'9 ;   3 D^kernel5.mcOctober 14, 1986 4:15 PM5%This is a test of the TestTW circuit on page 26 of the ProcH board.The Counter is loaded with a FF=154 (Hold&TaskSim_B) function.If this test fails the F-16 at location A03 or A04 is usually at fault.%TestTW:TaskingOff;T _ TaskCodelocC;*Set up Tpc 12 for 7000.Link _ T;*7000 = TaskCode.T _ (12s);ldTPC _ (T);*TestTW is task number is 12.TaskingOn;Q _ (RM1);*Set Q = 177777, the successful task running will set it back to 0T _ (400C);hold&tasksim_t;*This will set the A04 chip to the smallest count.Cnt _ (T);TestTWL:Skpif[cnt=0&-1];Goto[TestTWL];*Wait for a while to let task 12 wake-up and zero the Q register.T _ Q;Skpif[Alu=0];*Q is set to 0 in the Task Test code.TestTWError:Error;*The TestTW logic on Page 26 of the ProcH board is not working.Kernel5Exit:Goto[AfterKernel5];fp )fXN bq `pC _> ]G \q YpWq U'Ty'R Qq 'O Ni 'BL Ka'2I HYpFqEQ 'ABI@ '% ?Ap =q'@ :p 90q2 7eB0 TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN GACHA  ,"'-/379M= A:FlIMRTY']Ha&e%j(nsAvy{4X*F'c/-%%oXc~))-)-!)$)')p,+0.3/681;1=?*B1EG.J1MOSVY6\_beIh l2ouw{:%")]f + vEl6 :T3 yat.memo.he[Xlpromblowerlables.bravo.77 7 <)<3 77E767M66466!165/45/@;N6Xnez(?zep&*1<./0 9*0t#0t#3t#1.#rj/ ]? Kernel.PressVest15-Oct-86 12:56:38 PDT